MIPS per-cpu "shadow interrupts" (?)

[Jonas Gorski]

Hi,

On Wed, Jan 29, 2025 at 11:27 PM Caleb James DeLisle <cjd at cjdns.fr> wrote:
>
> Hello folks,
>
>
> I'm working on what I hope will be my first contribution, support for EcoNet EN75xx MIPS 34K SoCs.
>
> I ran into something I've never seen before and I wanted some advice on it. On this platform there
> is something I've taken to calling "shadow interrupts", they never fire but they provide a way to
> control one (v)CPU's view of a per-cpu interrupt. For example: Masking int 30 causes int 31 to stop
> firing on the 2nd CPU.
>
> I'd be fine to write econet,shadow-interrupts = [ 1e 1f ] in the DTS file and call it a day, but I
> don't want to be treating this like alien tech if it actually isn't.
>
> So my question: Is this a known thing? Does it have a name? Is there some term I can search for, or
> some existing PIC driver I can look at and copy from?

Sounds like a way of setting IRQ affinity to me. IRQ affinity does not
necessarily need to support more than one CPU at the same time.

Are these the MIPS CPU interrupts, or is this a separate IRQ controller?

Is this something you expect to be able change at runtime, or would
this be statically setup?

E.g. bmips sets up something like this statically and routes (CPU) IRQ
2 to CPU0 and IRQ 3 to CPU1, since a chained IRQ controller uses these
as configurable output interrupts for its 32-128 input interrupts
(where the "real" interrupt sources live).

Best Regards,
Jonas