MIPS per-cpu "shadow interrupts" (?)

[Caleb James DeLisle]

Hello,

On 05/02/2025 14:49, Jonas Gorski wrote:
> Hi,
>
> On Wed, Jan 29, 2025 at 11:27 PM Caleb James DeLisle <cjd at cjdns.fr> wrote:
>> Hello folks,
>>
>>
>> I'm working on what I hope will be my first contribution, support for EcoNet EN75xx MIPS 34K SoCs.
>>
>> I ran into something I've never seen before and I wanted some advice on it. On this platform there
>> is something I've taken to calling "shadow interrupts", they never fire but they provide a way to
>> control one (v)CPU's view of a per-cpu interrupt. For example: Masking int 30 causes int 31 to stop
>> firing on the 2nd CPU.
>>
>> I'd be fine to write econet,shadow-interrupts = [ 1e 1f ] in the DTS file and call it a day, but I
>> don't want to be treating this like alien tech if it actually isn't.
>>
>> So my question: Is this a known thing? Does it have a name? Is there some term I can search for, or
>> some existing PIC driver I can look at and copy from?
> Sounds like a way of setting IRQ affinity to me. IRQ affinity does not
> necessarily need to support more than one CPU at the same time.


This controller does have affinity, but it's one bit per interrupt so by default every interrupt is 
bound to CPU0 and the only change you can make is to bind it to CPU1 instead. These "shadow 
interrupts" exist for interrupts which really must be receivable by either.


>
> Are these the MIPS CPU interrupts, or is this a separate IRQ controller?


It's a separate controller.


>
> Is this something you expect to be able change at runtime, or would
> this be statically setup?


I'm pretty confident there's no way to change it at runtime, I suspect it's a capability that's part 
of the controller IP core and it's wired by the SoC integrator when they wire the hardware 
interrupts. So it's quite plausible that another SoC will have the same controller but with 
different per-cpu shadows.


>
> E.g. bmips sets up something like this statically and routes (CPU) IRQ
> 2 to CPU0 and IRQ 3 to CPU1, since a chained IRQ controller uses these
> as configurable output interrupts for its 32-128 input interrupts
> (where the "real" interrupt sources live).


Thanks for the tip, I took a look through bmips controllers but didn't see anything quite like this. 
It's possible that it exists in some controllers but is unsupported because most 34K ports are not 
trying to support MT SMP, so for them it's just a dead IRQ number.

My instinct is to let it be configured in the DTS.


Thanks,

Caleb

>
> Best Regards,
> Jonas