[PATCH v3] cn913x: add support for iEi Puzzle-M901/Puzzle-M902

Josef Schlehofer josef.schlehofer at nic.cz
Sun Jul 25 14:52:49 PDT 2021


Hello,

Are you going to send all these DTS files into kernel?

Regards,
Josef

On 02. 07. 21 13:16, eveans2002 at gmail.com wrote:
> From: Ian Chang <ianchang at ieiworld.com>
>
>  Hardware specification
>  ----------------------
>  * CN9130 SoC, Quad-core ARMv8 Cortex-72 @ 2200 MHz
>  * 4 GB DDR
>  * 4 GB eMMC
>  * mmcblk0
> 	- mmcblk0p1    64M  kernel_1
> 	- mmcblk0p2    64M  kernel_2
> 	- mmcblk0p3   512M  rootfs_1
> 	- mmcblk0p4   512M  rootfs_2
> 	- mmcblk0p5   512M  Reserved
> 	- mmcblk0p6    64M  Reserved
> 	- mmcblk0p7   1.8G  rootfs_data
>
>  * 4 MB (SPI Flash)
>  * 6 x 2.5 Gigabit  ports (Puzzle-M901)
>     - External PHY with 6 ports (AQR112R)
>  * 6 x 2.5 Gigabit ports (Puzzle-M902)
>     - External PHY with 6 ports (AQR112R)
>    3 x 10 Gigabit ports (Puzzle-M902)
>     - External PHY with 3 ports (AQR113R)
>
>  * 4 x Front panel LED
>  * 1 x USB 3.0
>  * Reset button on Rear panel
>  * UART (115200 8N1,header on PCB)
>
>  Flash instructions:
> 	The original firmware is based on OpenWrt.
> 	Flash firmware using LuCI and CLI
>
> Signed-off-by: Ian Chang <ianchang at ieiworld.com>
> ---
>  .../base-files/etc/board.d/02_network         |   6 +
>  .../cortexa72/base-files/lib/upgrade/emmc.sh  |  40 +++
>  .../base-files/lib/upgrade/platform.sh        |   8 +
>  .../boot/dts/marvell/cn9130-puzzle-m901.dts   | 216 ++++++++++++++++
>  .../boot/dts/marvell/cn9130-puzzle-m902.dts   | 236 ++++++++++++++++++
>  .../arm64/boot/dts/marvell/cn9130-puzzle.dtsi |  37 +++
>  .../boot/dts/marvell/cn9131-puzzle-m901.dts   | 153 ++++++++++++
>  .../boot/dts/marvell/cn9131-puzzle-m902.dts   | 136 ++++++++++
>  .../boot/dts/marvell/cn9132-puzzle-m902.dts   | 209 ++++++++++++++++
>  target/linux/mvebu/image/cortexa72.mk         |  20 ++
>  10 files changed, 1061 insertions(+)
>  create mode 100644 target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m901.dts
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m902.dts
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle.dtsi
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m902.dts
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
>
> diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> index 9ab3c8174d..f3c3cda977 100755
> --- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> +++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> @@ -21,6 +21,12 @@ marvell,armada8040-db)
>  marvell,armada7040-db)
>  	ucidef_set_interfaces_lan_wan "eth0 eth2" "eth1"
>  	;;
> +iei,cn9131-puzzle-m901)
> +	ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
> +	;;
> +iei,cn9132-puzzle-m902)
> +	ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5 eth10 eth11 eth12" "eth0"
> +	;;
>  *)
>  	ucidef_set_interface_lan "eth0"
>  	;;
> diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
> new file mode 100644
> index 0000000000..bd7eea5c22
> --- /dev/null
> +++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
> @@ -0,0 +1,40 @@
> +platform_do_upgrade_emmc() {
> +	local board=$(board_name)
> +	local diskdev partdev
> +
> +	export_bootdevice && export_partdevice diskdev 0 || {
> +		v "Unable to determine upgrade device"
> +	return 1
> +	}
> +
> +	sync
> +
> +	if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
> +		get_partitions "/dev/$diskdev" bootdisk
> +
> +		v "Extract boot sector from the image"
> +		get_image_dd "$1" of=/tmp/image.bs count=1 bs=512b
> +
> +		get_partitions /tmp/image.bs image
> +	fi
> +
> +	#iterate over each partition from the image and write it to the boot disk
> +	while read part start size; do
> +		if export_partdevice partdev $part; then
> +			if [ "$partdev" = "mmcblk0p2" ]; then
> +				v "Writing image mmcblk0p3 for /dev/$partdev  $start $size"
> +				get_image_dd "$1" of="/dev/mmcblk0p3" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
> +		  elif [ "$partdev" = "mmcblk0p1" ]; then
> +				v "Writing image mmcblk0p1 for /dev/$partdev $start $size"
> +				get_image_dd "$1" of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
> +			fi
> +		else
> +			v "Unable to find partition $part device, skipped."
> +		fi
> +	done < /tmp/partmap.image
> +
> +	v "Writing new UUID to /dev/$diskdev..."
> +	get_image_dd "$1" of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
> +
> +	sleep 1
> +}
> diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
> index 04ea634097..ea01b11be8 100755
> --- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
> +++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
> @@ -9,6 +9,8 @@ REQUIRE_IMAGE_METADATA=1
>  
>  platform_check_image() {
>  	case "$(board_name)" in
> +	iei,cn9131-puzzle-m901|\
> +	iei,cn9132-puzzle-m902|\
>  	marvell,armada8040-mcbin-doubleshot|\
>  	marvell,armada8040-mcbin-singleshot)
>  		platform_check_image_sdcard "$1"
> @@ -25,6 +27,10 @@ platform_do_upgrade() {
>  	marvell,armada8040-mcbin-singleshot)
>  		platform_do_upgrade_sdcard "$1"
>  		;;
> +	iei,cn9131-puzzle-m901|\
> +	iei,cn9132-puzzle-m902)
> +		platform_do_upgrade_emmc "$1"
> +		;;
>  	*)
>  		default_do_upgrade "$1"
>  		;;
> @@ -32,6 +38,8 @@ platform_do_upgrade() {
>  }
>  platform_copy_config() {
>  	case "$(board_name)" in
> +	iei,cn9131-puzzle-m901|\
> +	iei,cn9132-puzzle-m902|\
>  	marvell,armada8040-mcbin-doubleshot|\
>  	marvell,armada8040-mcbin-singleshot)
>  		platform_copy_config_sdcard
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m901.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m901.dts
> new file mode 100644
> index 0000000000..8e2ba97697
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m901.dts
> @@ -0,0 +1,216 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9130-DB board.
> + */
> +
> +#include "cn9130-puzzle.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "iEi Puzzle-M901";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	aliases {
> +		i2c0 = &cp0_i2c0;
> +		ethernet0 = &cp0_eth0;
> +		ethernet1 = &cp0_eth1;
> +		ethernet2 = &cp0_eth2;
> +		gpio1 = &cp0_gpio1;
> +		gpio2 = &cp0_gpio2;
> +		spi1 = &cp0_spi0;
> +		spi2 = &cp0_spi1;
> +		serial1 = &cp0_uart0;
> +	};
> +
> +	memory at 00000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>;
> +	};
> +
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&cp0_uart0 {
> +	status = "okay";
> +};
> +
> +/* on-board eMMC - U9 */
> +&ap_sdhci0 {
> +	pinctrl-names = "default";
> +	bus-width = <8>;
> +	status = "okay";
> +	mmc-ddr-1_8v;
> +	mmc-hs400-1_8v;
> +	/* vqmmc-supply = <&ap0_reg_sd_vccq>; */
> +};
> +
> +&cp0_crypto {
> +	status = "okay";
> +};
> +
> +&cp0_xmdio {
> +	status = "okay";
> +	phy0: ethernet-phy at 0 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	phy1: ethernet-phy at 1 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	phy2: ethernet-phy at 2 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp0_ethernet {
> +	status = "okay";
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp0_eth0 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy2 0>;
> +	/* phy = <&phy0>; */
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth1 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy4 1>;
> +	/* phy = <&phy1>; */
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth2 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy5 2>;
> +	/* phy = <&phy2>; */
> +	managed = "in-band-status";
> +};
> +
> +&cp0_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp0_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp0_i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_i2c0_pins>;
> +	status = "okay";
> +	clock-frequency = <100000>;
> +	rtc at 32 {
> +		compatible = "epson,rx8130";
> +		reg = <0x32>;
> +		wakeup-source;
> +	};
> +};
> +
> +
> +/* SLM-1521-V2, CON6 */
> +&cp0_pcie0 {
> +	status = "okay";
> +	num-lanes = <2>;
> +	num-viewport = <8>;
> +	/* Generic PHY, providing serdes lanes */
> +	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
> +};
> +
> +/* U55 */
> +&cp0_spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_spi0_pins>;
> +	reg = <0x700680 0x50>,          /* control */
> +	      <0x2000000 0x1000000>;    /* CS0 */
> +	status = "okay";
> +
> +	spi-flash at 0 {
> +		#address-cells = <0x1>;
> +		#size-cells = <0x1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0x0>;
> +		/* On-board MUX does not allow higher frequencies */
> +		spi-max-frequency = <40000000>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			partition at 0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x1f0000>;
> +			};
> +			partition at 1f0000 {
> +				label = "U-Boot ENV Factory";
> +				reg = <0x1f0000 0x10000>;
> +			};
> +			partition at 200000 {
> +				label = "Reserved";
> +				reg = <0x200000 0x1f0000>;
> +			};
> +			partition at 3f0000 {
> +				label = "U-Boot ENV";
> +				reg = <0x3f0000 0x10000>;
> +			};
> +		};
> +	};
> +};
> +
> +&cp0_syscon0 {
> +	cp0_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +
> +		cp0_i2c0_pins: cp0-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp0_i2c1_pins: cp0-i2c-pins-1 {
> +			marvell,pins = "mpp35", "mpp36";
> +			marvell,function = "i2c1";
> +		};
> +		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
> +			marvell,pins = "mpp0", "mpp1", "mpp2",
> +				       "mpp3", "mpp4", "mpp5",
> +				       "mpp6", "mpp7", "mpp8",
> +				       "mpp9", "mpp10", "mpp11";
> +			marvell,function = "ge0";
> +		};
> +		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
> +			marvell,pins = "mpp44", "mpp45", "mpp46",
> +				       "mpp47", "mpp48", "mpp49",
> +				       "mpp50", "mpp51", "mpp52",
> +				       "mpp53", "mpp54", "mpp55";
> +			marvell,function = "ge1";
> +		};
> +		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
> +			marvell,pins = "mpp43";
> +			marvell,function = "gpio";
> +		};
> +		cp0_sdhci_pins: cp0-sdhi-pins-0 {
> +			marvell,pins = "mpp56", "mpp57", "mpp58",
> +				       "mpp59", "mpp60", "mpp61";
> +			marvell,function = "sdio";
> +		};
> +		cp0_spi0_pins: cp0-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +	};
> +};
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m902.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m902.dts
> new file mode 100644
> index 0000000000..ab60dbec57
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle-m902.dts
> @@ -0,0 +1,236 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9130-DB board.
> + */
> +
> +#include "cn9130-puzzle.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "iEi Puzzle-M902";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	aliases {
> +		i2c0 = &cp0_i2c0;
> +		ethernet0 = &cp0_eth0;
> +		ethernet1 = &cp0_eth1;
> +		ethernet2 = &cp0_eth2;
> +		gpio1 = &cp0_gpio1;
> +		gpio2 = &cp0_gpio2;
> +		spi1 = &cp0_spi0;
> +		spi2 = &cp0_spi1;
> +		serial1 = &cp0_uart0;
> +	};
> +
> +	memory at 00000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&cp0_uart0 {
> +	status = "okay";
> +};
> +
> +/* on-board eMMC - U9 */
> +&ap_sdhci0 {
> +	pinctrl-names = "default";
> +	bus-width = <8>;
> +	status = "okay";
> +	mmc-ddr-1_8v;
> +	mmc-hs400-1_8v;
> +	/* vqmmc-supply = <&ap0_reg_sd_vccq>;*/
> +};
> +
> +
> +&cp0_crypto {
> +	status = "okay";
> +};
> +
> +&cp0_xmdio {
> +	status = "okay";
> +	phy0: ethernet-phy at 0 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	phy1: ethernet-phy at 1 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	phy2: ethernet-phy at 2 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp0_ethernet {
> +	status = "okay";
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp0_eth0 {
> +	status = "okay";
> +	phy-mode = "10gbase-kr";
> +	phys = <&cp0_comphy2 0>;
> +        /* phy = <&phy0>; */
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth1 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy4 1>;
> +	/* phy = <&phy1>; */
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth2 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy1 2>;
> +	/* phy = <&phy2>; */
> +	managed = "in-band-status";
> +};
> +
> +&cp0_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp0_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp0_i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_i2c0_pins>;
> +	status = "okay";
> +	clock-frequency = <100000>;
> +	rtc at 32 {
> +		compatible = "epson,rx8130";
> +		reg = <0x32>;
> +		wakeup-source;
> +	};
> +};
> +
> +&cp0_i2c1 {
> +	clock-frequency = <100000>;
> +};
> +
> +
> +
> +/* SLM-1521-V2, CON6 */
> +&cp0_sata0 {
> +	status = "okay";
> +	sata-port at 1 {
> +		status = "okay";
> +		phys = <&cp0_comphy0 1>;
> +	};
> +};
> +
> +&cp0_pcie2 {
> +	status = "okay";
> +	num-lanes = <1>;
> +	num-viewport = <8>;
> +	/* Generic PHY, providing serdes lanes */
> +	phys = <&cp0_comphy5 2>;
> +};
> +
> +/* U55 */
> +&cp0_spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_spi0_pins>;
> +	reg = <0x700680 0x50>,          /* control */
> +	      <0x2000000 0x1000000>;    /* CS0 */
> +	status = "okay";
> +
> +        spi-flash at 0 {
> +		#address-cells = <0x1>;
> +		#size-cells = <0x1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0x0>;
> +		/* On-board MUX does not allow higher frequencies */
> +		spi-max-frequency = <40000000>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			partition at 0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x1f0000>;
> +			};
> +		partition at 1f0000 {
> +				label = "U-Boot ENV Factory";
> +				reg = <0x1f0000 0x10000>;
> +			};
> +		partition at 200000 {
> +				label = "Reserved";
> +				reg = <0x200000 0x1f0000>;
> +			};
> +		partition at 3f0000 {
> +				label = "U-Boot ENV";
> +				reg = <0x3f0000 0x10000>;
> +			};
> +		};
> +	};
> +};
> +
> +&cp0_syscon0 {
> +	cp0_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +
> +		cp0_i2c0_pins: cp0-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp0_i2c1_pins: cp0-i2c-pins-1 {
> +			marvell,pins = "mpp35", "mpp36";
> +			marvell,function = "i2c1";
> +		};
> +		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
> +			marvell,pins = "mpp0", "mpp1", "mpp2",
> +				       "mpp3", "mpp4", "mpp5",
> +				       "mpp6", "mpp7", "mpp8",
> +				       "mpp9", "mpp10", "mpp11";
> +			marvell,function = "ge0";
> +		};
> +		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
> +			marvell,pins = "mpp44", "mpp45", "mpp46",
> +				       "mpp47", "mpp48", "mpp49",
> +				       "mpp50", "mpp51", "mpp52",
> +				       "mpp53", "mpp54", "mpp55";
> +			marvell,function = "ge1";
> +		};
> +		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
> +			marvell,pins = "mpp43";
> +			marvell,function = "gpio";
> +		};
> +		cp0_sdhci_pins: cp0-sdhi-pins-0 {
> +			marvell,pins = "mpp56", "mpp57", "mpp58",
> +				       "mpp59", "mpp60", "mpp61";
> +			marvell,function = "sdio";
> +		};
> +		cp0_spi0_pins: cp0-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +	};
> +};
> +
> +&cp0_usb3_1 {
> +	status = "okay";
> +	/* usb-phy = <&cp0_usb3_0_phy1>; */
> +	phys = <&cp0_comphy3 1>;
> +	phy-names = "usb";
> +};
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle.dtsi
> new file mode 100644
> index 0000000000..a2b7e5ec97
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-puzzle.dtsi
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9130 SoC.
> + */
> +
> +#include "armada-ap807-quad.dtsi"
> +
> +/ {
> +	model = "Marvell Armada CN9130 SoC";
> +	compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
> +		     "marvell,armada-ap807";
> +};
> +
> +/*
> + * Instantiate the internal CP115
> + */
> +
> +#define CP11X_NAME		cp0
> +#define CP11X_BASE		f2000000
> +#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
> +						    0xe0000000 + ((iface - 1) * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
> +#define CP11X_PCIE0_BASE	f2600000
> +#define CP11X_PCIE1_BASE	f2620000
> +#define CP11X_PCIE2_BASE	f2640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
> new file mode 100644
> index 0000000000..d34baf9585
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
> @@ -0,0 +1,153 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9131-DB board.
> + */
> +
> +#include "cn9130-puzzle-m901.dts"
> +
> +/ {
> +	model = "iEi Puzzle-M901";
> +	compatible = "iei,cn9131-puzzle-m901",
> +		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> +	aliases {
> +		i2c0 = &cp1_i2c0;
> +		ethernet3 = &cp1_eth0;
> +		ethernet4 = &cp1_eth1;
> +		ethernet5 = &cp1_eth2;
> +		gpio3 = &cp1_gpio1;
> +		gpio4 = &cp1_gpio2;
> +	};
> +
> +};
> +
> +/*
> + * Instantiate the first connected CP115
> + */
> +
> +#define CP11X_NAME		cp1
> +#define CP11X_BASE		f6000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE	f6600000
> +#define CP11X_PCIE1_BASE	f6620000
> +#define CP11X_PCIE2_BASE	f6640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp1_crypto {
> +	status = "okay";
> +};
> +
> +&cp1_xmdio {
> +	status = "okay";
> +	cp1_nbaset_phy0: ethernet-phy at 3 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp1_nbaset_phy1: ethernet-phy at 4 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp1_nbaset_phy2: ethernet-phy at 5 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp1_ethernet {
> +	status = "okay";
> +};
> +
> +/* CON50 */
> +&cp1_eth0 {
> +	status = "okay";
> +	/* phy = <&cp1_nbaset_phy0>; */
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth1 {
> +	status = "okay";
> +	/* phy = <&cp1_nbaset_phy1>; */
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth2 {
> +	status = "okay";
> +	/* phy = <&cp1_nbaset_phy2>; */
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy5 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_sata0 {
> +	status = "okay";
> +	sata-port at 1 {
> +		status = "okay";
> +		phys = <&cp1_comphy0 1>;
> +	};
> +};
> +
> +&cp1_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp1_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp1_i2c0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp1_i2c0_pins>;
> +	clock-frequency = <100000>;
> +};
> +
> +&cp1_syscon0 {
> +	cp1_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +		cp1_i2c0_pins: cp1-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp1_spi0_pins: cp1-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
> +			marvell,pins = "mpp3";
> +			marvell,function = "gpio";
> +		};
> +		cp1_sfp_pins: sfp-pins {
> +			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
> +			marvell,function = "gpio";
> +		};
> +		cp1_pcie_reset_pins: cp1-pcie-reset-pins {
> +			marvell,pins = "mpp0";
> +			marvell,function = "gpio";
> +		};
> +	};
> +};
> +
> +/* CON58 */
> +&cp1_usb3_1 {
> +	status = "okay";
> +	/* usb-phy = <&cp1_usb3_0_phy1>; */
> +	phys = <&cp1_comphy3 1>;
> +	phy-names = "usb";
> +};
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m902.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m902.dts
> new file mode 100644
> index 0000000000..54098d8021
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m902.dts
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9131-DB board.
> + */
> +
> +#include "cn9130-puzzle-m902.dts"
> +
> +/ {
> +	model = "iEi Puzzle-M902";
> +	compatible = "iei,cn9132-puzzle-m902",
> +		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> +	aliases {
> +		i2c0 = &cp1_i2c0;
> +		ethernet3 = &cp1_eth0;
> +		ethernet4 = &cp1_eth1;
> +		ethernet5 = &cp1_eth2;
> +		gpio3 = &cp1_gpio1;
> +		gpio4 = &cp1_gpio2;
> +	};
> +};
> +
> +/*
> + * Instantiate the first connected CP115
> + */
> +
> +#define CP11X_NAME		cp1
> +#define CP11X_BASE		f4000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE	f4600000
> +#define CP11X_PCIE1_BASE	f4620000
> +#define CP11X_PCIE2_BASE	f4640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp1_crypto {
> +	status = "okay";
> +};
> +
> +&cp1_xmdio {
> +	status = "okay";
> +	cp1_nbaset_phy0: ethernet-phy at 3 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp1_nbaset_phy1: ethernet-phy at 4 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp1_nbaset_phy2: ethernet-phy at 5 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp1_ethernet {
> +	status = "okay";
> +};
> +
> +/* CON50 */
> +&cp1_eth0 {
> +	status = "okay";
> +	/* phy = <&cp1_nbaset_phy0>; */
> +	phy-mode = "10gbase-kr";
> +	phys = <&cp1_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth1 {
> +	status = "okay";
> +	/* phy = <&cp1_nbaset_phy1>; */
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth2 {
> +	status = "okay";
> +	/* phy = <&cp1_nbaset_phy2>; */
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy1 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp1_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp1_i2c0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp1_i2c0_pins>;
> +	clock-frequency = <100000>;
> +};
> +
> +&cp1_syscon0 {
> +	cp1_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +		cp1_i2c0_pins: cp1-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp1_spi0_pins: cp1-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
> +			marvell,pins = "mpp3";
> +			marvell,function = "gpio";
> +		};
> +		cp1_sfp_pins: sfp-pins {
> +			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
> +			marvell,function = "gpio";
> +		};
> +		cp1_pcie_reset_pins: cp1-pcie-reset-pins {
> +			marvell,pins = "mpp0";
> +			marvell,function = "gpio";
> +		};
> +	};
> +};
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
> new file mode 100644
> index 0000000000..2398585ef2
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
> @@ -0,0 +1,209 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9132-DB board.
> + */
> +
> +#include "cn9131-puzzle-m902.dts"
> +
> +/ {
> +	model = "iEi Puzzle-M902";
> +	compatible = "iei,cn9132-puzzle-m902",
> +		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> +	aliases {
> +		gpio5 = &cp2_gpio1;
> +		gpio6 = &cp2_gpio2;
> +		ethernet6 = &cp2_eth0;
> +		ethernet7 = &cp2_eth1;
> +		ethernet8 = &cp2_eth2;
> +	};
> +
> +	cp2_reg_usb3_vbus0: cp2_usb3_vbus at 0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "cp2-xhci0-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	cp2_usb3_0_phy0: cp2_usb3_phy0 {
> +		compatible = "usb-nop-xceiv";
> +		vcc-supply = <&cp2_reg_usb3_vbus0>;
> +	};
> +
> +	cp2_reg_usb3_vbus1: cp2_usb3_vbus at 1 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "cp2-xhci1-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	cp2_usb3_0_phy1: cp2_usb3_phy1 {
> +		compatible = "usb-nop-xceiv";
> +		vcc-supply = <&cp2_reg_usb3_vbus1>;
> +	};
> +
> +	cp2_reg_sd_vccq: cp2_sd_vccq at 0 {
> +		compatible = "regulator-gpio";
> +		regulator-name = "cp2_sd_vcc";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
> +		states = <1800000 0x1 3300000 0x0>;
> +	};
> +
> +	cp2_sfp_eth0: sfp-eth0 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&cp2_sfpp0_i2c>;
> +		los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
> +		tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
> +		tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
> +		/*
> +		 * SFP cages are unconnected on early PCBs because of an the I2C
> +		 * lanes not being connected. Prevent the port for being
> +		 * unusable by disabling the SFP node.
> +		 */
> +		status = "disabled";
> +	};
> +};
> +
> +/*
> + * Instantiate the second connected CP115
> + */
> +
> +#define CP11X_NAME		cp2
> +#define CP11X_BASE		f6000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE	f6600000
> +#define CP11X_PCIE1_BASE	f6620000
> +#define CP11X_PCIE2_BASE	f6640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp2_crypto {
> +	status = "okay";
> +};
> +
> +&cp2_ethernet {
> +	status = "okay";
> +};
> +
> +&cp2_xmdio {
> +	status = "okay";
> +	cp2_nbaset_phy0: ethernet-phy at 6 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp2_nbaset_phy1: ethernet-phy at 7 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp2_nbaset_phy2: ethernet-phy at 8 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp2_eth0 {
> +	status = "okay";
> +	/* phy = <&cp2_nbaset_phy0>; */
> +	phy-mode = "10gbase-kr";
> +	phys = <&cp2_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp2_eth1 {
> +	status = "okay";
> +	/* phy = <&cp2_nbaset_phy1>; */
> +	phy-mode = "2500base-x";
> +	phys = <&cp2_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp2_eth2 {
> +	status = "okay";
> +	/* phy = <&cp2_nbaset_phy2>; */
> +	phy-mode = "2500base-x";
> +	phys = <&cp2_comphy1 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp2_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp2_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp2_i2c0 {
> +	clock-frequency = <100000>;
> +	/* SLM-1521-V2 - U3 */
> +	i2c-mux at 72 {
> +		compatible = "nxp,pca9544";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0x72>;
> +		cp2_sfpp0_i2c: i2c at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0>;
> +		};
> +
> +		i2c at 1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +			/* U12 */
> +			cp2_module_expander1: pca9555 at 21 {
> +				compatible = "nxp,pca9555";
> +				pinctrl-names = "default";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x21>;
> +			};
> +		};
> +	};
> +};
> +
> +/* CON 2 on SLM-1683 - microSD */
> +&cp2_sdhci0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp2_sdhci_pins>;
> +	bus-width = <4>;
> +	cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
> +	vqmmc-supply = <&cp2_reg_sd_vccq>;
> +};
> +
> +&cp2_syscon0 {
> +	cp2_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +
> +		cp2_i2c0_pins: cp2-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp2_sdhci_pins: cp2-sdhi-pins-0 {
> +			marvell,pins = "mpp56", "mpp57", "mpp58",
> +				       "mpp59", "mpp60", "mpp61";
> +			marvell,function = "sdio";
> +		};
> +	};
> +};
> +
> diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
> index 1440c07a0b..5b4195f856 100644
> --- a/target/linux/mvebu/image/cortexa72.mk
> +++ b/target/linux/mvebu/image/cortexa72.mk
> @@ -43,3 +43,23 @@ define Device/marvell_macchiatobin-singleshot
>    SUPPORTED_DEVICES := marvell,armada8040-mcbin-singleshot
>  endef
>  TARGET_DEVICES += marvell_macchiatobin-singleshot
> +
> +define Device/iei_cn9131-puzzle-m901
> +  $(call Device/Default-arm64)
> +  DEVICE_VENDOR := iEi
> +  DEVICE_MODEL := Puzzle-M901
> +  DEVICE_DTS := cn9131-puzzle-m901
> +  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
> +  SUPPORTED_DEVICES := iei,cn9131-puzzle-m901
> +endef
> +TARGET_DEVICES += iei_cn9131-puzzle-m901
> +
> +define Device/iei_cn9132-puzzle-m902
> +  $(call Device/Default-arm64)
> +  DEVICE_VENDOR := iEi
> +  DEVICE_MODEL := Puzzle-M902
> +  DEVICE_DTS := cn9132-puzzle-m902
> +  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
> +  SUPPORTED_DEVICES := iei,cn9132-puzzle-m902
> +endef
> +TARGET_DEVICES += iei_cn9132-puzzle-m902

-- 
Josef Schlehofer
Turris Developer Team

CZ.NIC, z. s. p. o.
Milešovská 5, 130 00 Praha 3
https://www.nic.cz/


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