[OpenWrt-Devel] [PATCH 1/2] mvebu: add kernel 4.19 support
Kabuli Chana
anome at shaw.ca
Wed Jun 5 14:14:44 EDT 2019
On 2019-06-05 8:31 a.m., Tomasz Maciej Nowak wrote:
> From: Marko Ratkaj <marko.ratkaj at sartura.hr>
>
> Cc: Vladimir Vid <vladimir.vid at sartura.hr>
> Signed-off-by: Marko Ratkaj <marko.ratkaj at sartura.hr>
> [added sfp related patches from Russell King]
> Signed-off-by: Marek Behún <marek.behun at nic.cz>
> [rebase; rework patches; separate and cleanup kernel configs;
> add espessobin dts; adjust venom dts]
> Signed-off-by: Tomasz Maciej Nowak <tomek_n at o2.pl>
> ---
> target/linux/mvebu/Makefile | 1 +
> target/linux/mvebu/config-4.19 | 501 ++++++++++++
> .../cortexa53/{config-default => config-4.14} | 0
> target/linux/mvebu/cortexa53/config-4.19 | 114 +++
> .../cortexa72/{config-default => config-4.14} | 0
> target/linux/mvebu/cortexa72/config-4.19 | 122 +++
> .../arm/boot/dts/armada-385-linksys-venom.dts | 213 +++++
> .../marvell/armada-3720-espressobin-emmc.dts | 28 +
> .../armada-3720-espressobin-v7-emmc.dts | 43 +
> .../marvell/armada-3720-espressobin-v7.dts | 31 +
> .../patches-4.19/002-add_powertables.patch | 770 ++++++++++++++++++
> .../patches-4.19/003-add_switch_nodes.patch | 40 +
> .../004-add_sata_disk_activity_trigger.patch | 39 +
> ...5-linksys_hardcode_nand_ecc_settings.patch | 17 +
> ...Mangle-bootloader-s-kernel-arguments.patch | 201 +++++
> .../patches-4.19/100-find_active_root.patch | 60 ++
> .../patches-4.19/102-revert_i2c_delay.patch | 15 +
> .../205-armada-385-rd-mtd-partitions.patch | 19 +
> .../206-ARM-mvebu-385-ap-Add-partitions.patch | 35 +
> .../210-clearfog_switch_node.patch | 21 +
> .../220-disable-untested-dsa-boards.patch | 30 +
> ...-armada-xp-linksys-mamba-broken-idle.patch | 10 +
> .../300-mvneta-tx-queue-workaround.patch | 35 +
> ...dicate-failure-to-enter-deeper-sleep.patch | 40 +
> ...-pci-mvebu-time-out-reset-on-link-up.patch | 60 ++
> ...-call-mac_config-during-resolve-when.patch | 44 +
> ...ink-ensure-inband-AN-works-correctly.patch | 59 ++
> ...etdev-sfp_bus-and-use-for-start-stop.patch | 39 +
> ...5-net-phy-marvell10g-add-SFP-support.patch | 155 ++++
> .../406-sfp-add-sfp-compatible.patch | 24 +
> ...7-sfp-display-SFP-module-information.patch | 297 +++++++
> .../408-sfp-more-cotsworks-fixes.patch | 44 +
> ...da388-clearfog-emmc-on-clearfog-base.patch | 87 ++
> ...rmada388-clearfog-document-MPP-usage.patch | 124 +++
> .../patches-4.19/450-reprobe_sfp_phy.patch | 94 +++
> ...l-armada37xx-Add-emmc-sdio-pinctrl-d.patch | 40 +
> ...l-armada-37xx-Enable-emmc-on-espress.patch | 49 ++
> ...ts-marvell-armada37xx-Add-eth0-alias.patch | 20 +
> ...da-3720-espressobin-correct-spi-node.patch | 58 ++
> ...l-armada-3720-espressobin-add-ports-.patch | 26 +
> ...rdvark-Convert-to-use-pci_host_probe.patch | 44 +
> ...-device-to-the-same-MAX-payload-size.patch | 138 ++++
> ...ardvark-disable-LOS-state-by-default.patch | 55 ++
> ...ark-allow-to-specify-link-capability.patch | 43 +
> ...-3720-espressobin-set-max-link-to-ge.patch | 73 ++
> 45 files changed, 3958 insertions(+)
> create mode 100644 target/linux/mvebu/config-4.19
> rename target/linux/mvebu/cortexa53/{config-default => config-4.14} (100%)
> create mode 100644 target/linux/mvebu/cortexa53/config-4.19
> rename target/linux/mvebu/cortexa72/{config-default => config-4.14} (100%)
> create mode 100644 target/linux/mvebu/cortexa72/config-4.19
> create mode 100644 target/linux/mvebu/files-4.19/arch/arm/boot/dts/armada-385-linksys-venom.dts
> create mode 100644 target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts
> create mode 100644 target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts
> create mode 100644 target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts
> create mode 100644 target/linux/mvebu/patches-4.19/002-add_powertables.patch
> create mode 100644 target/linux/mvebu/patches-4.19/003-add_switch_nodes.patch
> create mode 100644 target/linux/mvebu/patches-4.19/004-add_sata_disk_activity_trigger.patch
> create mode 100644 target/linux/mvebu/patches-4.19/005-linksys_hardcode_nand_ecc_settings.patch
> create mode 100644 target/linux/mvebu/patches-4.19/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
> create mode 100644 target/linux/mvebu/patches-4.19/100-find_active_root.patch
> create mode 100644 target/linux/mvebu/patches-4.19/102-revert_i2c_delay.patch
> create mode 100644 target/linux/mvebu/patches-4.19/205-armada-385-rd-mtd-partitions.patch
> create mode 100644 target/linux/mvebu/patches-4.19/206-ARM-mvebu-385-ap-Add-partitions.patch
> create mode 100644 target/linux/mvebu/patches-4.19/210-clearfog_switch_node.patch
> create mode 100644 target/linux/mvebu/patches-4.19/220-disable-untested-dsa-boards.patch
> create mode 100644 target/linux/mvebu/patches-4.19/230-armada-xp-linksys-mamba-broken-idle.patch
> create mode 100644 target/linux/mvebu/patches-4.19/300-mvneta-tx-queue-workaround.patch
> create mode 100644 target/linux/mvebu/patches-4.19/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
> create mode 100644 target/linux/mvebu/patches-4.19/401-pci-mvebu-time-out-reset-on-link-up.patch
> create mode 100644 target/linux/mvebu/patches-4.19/402-net-phylink-only-call-mac_config-during-resolve-when.patch
> create mode 100644 target/linux/mvebu/patches-4.19/403-net-phylink-ensure-inband-AN-works-correctly.patch
> create mode 100644 target/linux/mvebu/patches-4.19/404-sfp-provide-netdev-sfp_bus-and-use-for-start-stop.patch
> create mode 100644 target/linux/mvebu/patches-4.19/405-net-phy-marvell10g-add-SFP-support.patch
> create mode 100644 target/linux/mvebu/patches-4.19/406-sfp-add-sfp-compatible.patch
> create mode 100644 target/linux/mvebu/patches-4.19/407-sfp-display-SFP-module-information.patch
> create mode 100644 target/linux/mvebu/patches-4.19/408-sfp-more-cotsworks-fixes.patch
> create mode 100644 target/linux/mvebu/patches-4.19/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
> create mode 100644 target/linux/mvebu/patches-4.19/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
> create mode 100644 target/linux/mvebu/patches-4.19/450-reprobe_sfp_phy.patch
> create mode 100644 target/linux/mvebu/patches-4.19/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
> create mode 100644 target/linux/mvebu/patches-4.19/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
> create mode 100644 target/linux/mvebu/patches-4.19/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
> create mode 100644 target/linux/mvebu/patches-4.19/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
> create mode 100644 target/linux/mvebu/patches-4.19/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
> create mode 100644 target/linux/mvebu/patches-4.19/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
> create mode 100644 target/linux/mvebu/patches-4.19/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
> create mode 100644 target/linux/mvebu/patches-4.19/526-PCI-aardvark-disable-LOS-state-by-default.patch
> create mode 100644 target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch
> create mode 100644 target/linux/mvebu/patches-4.19/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
>
> diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile
> index a920f6db7d..f39573c002 100644
> --- a/target/linux/mvebu/Makefile
> +++ b/target/linux/mvebu/Makefile
> @@ -13,6 +13,7 @@ SUBTARGETS:=cortexa9 cortexa53 cortexa72
> MAINTAINER:=Imre Kaloz <kaloz at openwrt.org>
>
> KERNEL_PATCHVER:=4.14
> +KERNEL_TESTING_PATCHVER:=4.19
>
> include $(INCLUDE_DIR)/target.mk
>
> diff --git a/target/linux/mvebu/config-4.19 b/target/linux/mvebu/config-4.19
> new file mode 100644
> index 0000000000..2c996d4dcb
> --- /dev/null
> +++ b/target/linux/mvebu/config-4.19
> @@ -0,0 +1,501 @@
> +CONFIG_AHCI_MVEBU=y
> +CONFIG_ALIGNMENT_TRAP=y
> +CONFIG_ARCH_CLOCKSOURCE_DATA=y
> +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
> +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
> +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
> +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
> +CONFIG_ARCH_HAS_KCOV=y
> +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
> +CONFIG_ARCH_HAS_PHYS_TO_DMA=y
> +CONFIG_ARCH_HAS_SET_MEMORY=y
> +CONFIG_ARCH_HAS_SG_CHAIN=y
> +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
> +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
> +CONFIG_ARCH_HAS_TICK_BROADCAST=y
> +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
> +CONFIG_ARCH_HIBERNATION_POSSIBLE=y
> +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
> +CONFIG_ARCH_MULTIPLATFORM=y
> +CONFIG_ARCH_MULTI_V6_V7=y
> +CONFIG_ARCH_MULTI_V7=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_ARCH_NR_GPIO=0
> +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
> +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
> +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
> +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
> +CONFIG_ARCH_SUPPORTS_UPROBES=y
> +CONFIG_ARCH_SUSPEND_POSSIBLE=y
> +CONFIG_ARCH_USE_BUILTIN_BSWAP=y
> +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
> +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
> +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
> +CONFIG_ARM=y
> +CONFIG_ARMADA_370_CLK=y
> +CONFIG_ARMADA_370_XP_IRQ=y
> +CONFIG_ARMADA_370_XP_TIMER=y
> +CONFIG_ARMADA_38X_CLK=y
> +CONFIG_ARMADA_THERMAL=y
> +CONFIG_ARMADA_XP_CLK=y
> +CONFIG_ARM_APPENDED_DTB=y
> +# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
> +CONFIG_ARM_ATAG_DTB_COMPAT=y
> +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
> +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
> +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
> +CONFIG_ARM_CPU_SUSPEND=y
> +CONFIG_ARM_CRYPTO=y
> +CONFIG_ARM_ERRATA_720789=y
> +CONFIG_ARM_ERRATA_764369=y
> +CONFIG_ARM_GIC=y
> +CONFIG_ARM_GLOBAL_TIMER=y
> +CONFIG_ARM_HAS_SG_CHAIN=y
> +CONFIG_ARM_HEAVY_MB=y
> +CONFIG_ARM_L1_CACHE_SHIFT=6
> +CONFIG_ARM_L1_CACHE_SHIFT_6=y
> +# CONFIG_ARM_LPAE is not set
> +CONFIG_ARM_MVEBU_V7_CPUIDLE=y
> +CONFIG_ARM_PATCH_IDIV=y
> +CONFIG_ARM_PATCH_PHYS_VIRT=y
> +CONFIG_ARM_THUMB=y
> +# CONFIG_ARM_THUMBEE is not set
> +CONFIG_ARM_UNWIND=y
> +CONFIG_ARM_VIRT_EXT=y
> +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
> +CONFIG_ATA=y
> +CONFIG_ATAGS=y
> +CONFIG_AUTO_ZRELADDR=y
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_BLK_DEV_SD=y
> +CONFIG_BLK_MQ_PCI=y
> +CONFIG_BLK_SCSI_REQUEST=y
> +CONFIG_BOUNCE=y
> +# CONFIG_CACHE_FEROCEON_L2 is not set
> +CONFIG_CACHE_L2X0=y
> +CONFIG_CLKDEV_LOOKUP=y
> +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
> +CONFIG_CLKSRC_MMIO=y
> +CONFIG_CLONE_BACKWARDS=y
> +CONFIG_COMMON_CLK=y
> +CONFIG_CPUFREQ_DT=y
> +CONFIG_CPUFREQ_DT_PLATDEV=y
> +CONFIG_CPU_32v6K=y
> +CONFIG_CPU_32v7=y
> +CONFIG_CPU_ABRT_EV7=y
> +# CONFIG_CPU_BIG_ENDIAN is not set
> +# CONFIG_CPU_BPREDICT_DISABLE is not set
> +CONFIG_CPU_CACHE_V7=y
> +CONFIG_CPU_CACHE_VIPT=y
> +CONFIG_CPU_COPY_V6=y
> +CONFIG_CPU_CP15=y
> +CONFIG_CPU_CP15_MMU=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
> +CONFIG_CPU_FREQ_GOV_ATTR_SET=y
> +CONFIG_CPU_FREQ_GOV_COMMON=y
> +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
> +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
> +CONFIG_CPU_FREQ_STAT=y
> +CONFIG_CPU_HAS_ASID=y
> +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
> +# CONFIG_CPU_ICACHE_DISABLE is not set
> +CONFIG_CPU_IDLE=y
> +CONFIG_CPU_IDLE_GOV_LADDER=y
> +CONFIG_CPU_PABRT_V7=y
> +CONFIG_CPU_PJ4B=y
> +CONFIG_CPU_PM=y
> +CONFIG_CPU_RMAP=y
> +CONFIG_CPU_SPECTRE=y
> +CONFIG_CPU_THERMAL=y
> +CONFIG_CPU_THUMB_CAPABLE=y
> +CONFIG_CPU_TLB_V7=y
> +CONFIG_CPU_V7=y
> +CONFIG_CRC16=y
> +CONFIG_CRYPTO_ACOMP2=y
> +CONFIG_CRYPTO_AEAD=y
> +CONFIG_CRYPTO_AEAD2=y
> +CONFIG_CRYPTO_AES_ARM=y
> +CONFIG_CRYPTO_AES_ARM_BS=y
> +# CONFIG_CRYPTO_AES_ARM_CE is not set
> +# CONFIG_CRYPTO_CHACHA20_NEON is not set
> +CONFIG_CRYPTO_CRC32=y
> +CONFIG_CRYPTO_CRC32C=y
> +# CONFIG_CRYPTO_CRC32_ARM_CE is not set
> +CONFIG_CRYPTO_CRYPTD=y
> +CONFIG_CRYPTO_DEFLATE=y
> +CONFIG_CRYPTO_DES=y
> +CONFIG_CRYPTO_DEV_MARVELL_CESA=y
> +# CONFIG_CRYPTO_GHASH_ARM_CE is not set
> +CONFIG_CRYPTO_HASH=y
> +CONFIG_CRYPTO_HASH2=y
> +CONFIG_CRYPTO_HW=y
> +CONFIG_CRYPTO_LZO=y
> +CONFIG_CRYPTO_MANAGER=y
> +CONFIG_CRYPTO_MANAGER2=y
> +CONFIG_CRYPTO_NULL2=y
> +CONFIG_CRYPTO_RNG2=y
> +CONFIG_CRYPTO_SHA1=y
> +CONFIG_CRYPTO_SHA1_ARM=y
> +# CONFIG_CRYPTO_SHA1_ARM_CE is not set
> +CONFIG_CRYPTO_SHA1_ARM_NEON=y
> +CONFIG_CRYPTO_SHA256_ARM=y
> +# CONFIG_CRYPTO_SHA2_ARM_CE is not set
> +CONFIG_CRYPTO_SHA512_ARM=y
> +CONFIG_CRYPTO_SIMD=y
> +CONFIG_CRYPTO_WORKQUEUE=y
> +CONFIG_DCACHE_WORD_ACCESS=y
> +CONFIG_DEBUG_ALIGN_RODATA=y
> +CONFIG_DEBUG_INFO=y
> +CONFIG_DEBUG_LL=y
> +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
> +CONFIG_DEBUG_MVEBU_UART0=y
> +# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
> +# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
> +CONFIG_DEBUG_UART_8250=y
> +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
> +CONFIG_DEBUG_UART_8250_SHIFT=2
> +# CONFIG_DEBUG_UART_8250_WORD is not set
> +CONFIG_DEBUG_UART_PHYS=0xd0012000
> +CONFIG_DEBUG_UART_VIRT=0xfec12000
> +CONFIG_DEBUG_UNCOMPRESS=y
> +CONFIG_DEBUG_USER=y
> +CONFIG_DMADEVICES=y
> +CONFIG_DMA_ENGINE=y
> +CONFIG_DMA_ENGINE_RAID=y
> +CONFIG_DMA_OF=y
> +CONFIG_DTC=y
> +CONFIG_EARLY_PRINTK=y
> +CONFIG_EDAC_ATOMIC_SCRUB=y
> +CONFIG_EDAC_SUPPORT=y
> +CONFIG_EXT4_FS=y
> +CONFIG_EXTCON=y
> +# CONFIG_F2FS_CHECK_FS is not set
> +CONFIG_F2FS_FS=y
> +# CONFIG_F2FS_FS_SECURITY is not set
> +CONFIG_F2FS_FS_XATTR=y
> +CONFIG_F2FS_STAT_FS=y
> +CONFIG_FIXED_PHY=y
> +CONFIG_FIX_EARLYCON_MEM=y
> +CONFIG_FS_IOMAP=y
> +CONFIG_FS_MBCACHE=y
> +CONFIG_GENERIC_ALLOCATOR=y
> +CONFIG_GENERIC_ARCH_TOPOLOGY=y
> +CONFIG_GENERIC_BUG=y
> +CONFIG_GENERIC_CLOCKEVENTS=y
> +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
> +CONFIG_GENERIC_CPU_AUTOPROBE=y
> +CONFIG_GENERIC_EARLY_IOREMAP=y
> +CONFIG_GENERIC_IDLE_POLL_SETUP=y
> +CONFIG_GENERIC_IRQ_CHIP=y
> +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
> +CONFIG_GENERIC_IRQ_MIGRATION=y
> +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
> +CONFIG_GENERIC_IRQ_SHOW=y
> +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
> +CONFIG_GENERIC_MSI_IRQ=y
> +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
> +CONFIG_GENERIC_PCI_IOMAP=y
> +CONFIG_GENERIC_PHY=y
> +CONFIG_GENERIC_SCHED_CLOCK=y
> +CONFIG_GENERIC_SMP_IDLE_THREAD=y
> +CONFIG_GENERIC_STRNCPY_FROM_USER=y
> +CONFIG_GENERIC_STRNLEN_USER=y
> +CONFIG_GLOB=y
> +CONFIG_GPIOLIB=y
> +CONFIG_GPIOLIB_IRQCHIP=y
> +CONFIG_GPIO_GENERIC=y
> +CONFIG_GPIO_GENERIC_PLATFORM=y
> +CONFIG_GPIO_MVEBU=y
> +CONFIG_GPIO_PCA953X=y
> +CONFIG_GPIO_PCA953X_IRQ=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_HANDLE_DOMAIN_IRQ=y
> +CONFIG_HARDEN_BRANCH_PREDICTOR=y
> +CONFIG_HARDIRQS_SW_RESEND=y
> +CONFIG_HAS_DMA=y
> +CONFIG_HAS_IOMEM=y
> +CONFIG_HAS_IOPORT_MAP=y
> +CONFIG_HAVE_ARCH_AUDITSYSCALL=y
> +CONFIG_HAVE_ARCH_BITREVERSE=y
> +CONFIG_HAVE_ARCH_JUMP_LABEL=y
> +CONFIG_HAVE_ARCH_KGDB=y
> +CONFIG_HAVE_ARCH_PFN_VALID=y
> +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
> +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
> +CONFIG_HAVE_ARCH_TRACEHOOK=y
> +CONFIG_HAVE_ARM_SCU=y
> +CONFIG_HAVE_ARM_SMCCC=y
> +CONFIG_HAVE_ARM_TWD=y
> +CONFIG_HAVE_CLK=y
> +CONFIG_HAVE_CLK_PREPARE=y
> +CONFIG_HAVE_CONTEXT_TRACKING=y
> +CONFIG_HAVE_C_RECORDMCOUNT=y
> +CONFIG_HAVE_DEBUG_KMEMLEAK=y
> +CONFIG_HAVE_DMA_CONTIGUOUS=y
> +CONFIG_HAVE_DYNAMIC_FTRACE=y
> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
> +CONFIG_HAVE_EBPF_JIT=y
> +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
> +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
> +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
> +CONFIG_HAVE_FUNCTION_TRACER=y
> +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> +CONFIG_HAVE_IDE=y
> +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
> +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
> +CONFIG_HAVE_MEMBLOCK=y
> +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
> +CONFIG_HAVE_NET_DSA=y
> +CONFIG_HAVE_OPROFILE=y
> +CONFIG_HAVE_OPTPROBES=y
> +CONFIG_HAVE_PERF_EVENTS=y
> +CONFIG_HAVE_PERF_REGS=y
> +CONFIG_HAVE_PERF_USER_STACK_DUMP=y
> +CONFIG_HAVE_PROC_CPU=y
> +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
> +CONFIG_HAVE_RSEQ=y
> +CONFIG_HAVE_SMP=y
> +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
> +CONFIG_HAVE_UID16=y
> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
> +CONFIG_HIGHMEM=y
> +# CONFIG_HIGHPTE is not set
> +CONFIG_HOTPLUG_CPU=y
> +CONFIG_HWBM=y
> +CONFIG_HWMON=y
> +CONFIG_HW_RANDOM=y
> +CONFIG_HZ_FIXED=0
> +CONFIG_HZ_PERIODIC=y
> +CONFIG_I2C=y
> +CONFIG_I2C_BOARDINFO=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_MV64XXX=y
> +# CONFIG_I2C_PXA is not set
> +CONFIG_INITRAMFS_SOURCE=""
> +CONFIG_IRQCHIP=y
> +CONFIG_IRQ_DOMAIN=y
> +CONFIG_IRQ_DOMAIN_HIERARCHY=y
> +CONFIG_IRQ_FORCED_THREADING=y
> +CONFIG_IRQ_WORK=y
> +# CONFIG_IWMMXT is not set
> +CONFIG_JBD2=y
> +CONFIG_LEDS_GPIO=y
> +CONFIG_LEDS_PCA963X=y
> +CONFIG_LEDS_TLC591XX=y
> +CONFIG_LEDS_TRIGGER_DISK=y
> +CONFIG_LIBFDT=y
> +CONFIG_LOCK_DEBUGGING_SUPPORT=y
> +CONFIG_LOCK_SPIN_ON_OWNER=y
> +CONFIG_LZO_COMPRESS=y
> +CONFIG_LZO_DECOMPRESS=y
> +CONFIG_MACH_ARMADA_370=y
> +# CONFIG_MACH_ARMADA_375 is not set
> +CONFIG_MACH_ARMADA_38X=y
> +# CONFIG_MACH_ARMADA_39X is not set
> +CONFIG_MACH_ARMADA_XP=y
> +# CONFIG_MACH_DOVE is not set
> +CONFIG_MACH_MVEBU_ANY=y
> +CONFIG_MACH_MVEBU_V7=y
> +CONFIG_MAGIC_SYSRQ=y
> +CONFIG_MANGLE_BOOTARGS=y
> +CONFIG_MARVELL_PHY=y
> +CONFIG_MDIO_BUS=y
> +CONFIG_MDIO_DEVICE=y
> +CONFIG_MDIO_I2C=y
> +CONFIG_MEMFD_CREATE=y
> +CONFIG_MEMORY=y
> +CONFIG_MIGHT_HAVE_CACHE_L2X0=y
> +CONFIG_MIGHT_HAVE_PCI=y
> +CONFIG_MIGRATION=y
> +CONFIG_MMC=y
> +CONFIG_MMC_BLOCK=y
> +CONFIG_MMC_MVSDIO=y
> +CONFIG_MMC_SDHCI=y
> +# CONFIG_MMC_SDHCI_PCI is not set
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_PXAV3=y
> +# CONFIG_MMC_TIFM_SD is not set
> +CONFIG_MODULES_USE_ELF_REL=y
> +# CONFIG_MSCC_OCELOT_SWITCH is not set
> +CONFIG_MTD_CFI_STAA=y
> +CONFIG_MTD_M25P80=y
> +CONFIG_MTD_NAND=y
> +CONFIG_MTD_NAND_ECC=y
> +CONFIG_MTD_NAND_MARVELL=y
> +CONFIG_MTD_SPI_NOR=y
> +CONFIG_MTD_SPLIT_FIRMWARE=y
> +CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_BEB_LIMIT=20
> +CONFIG_MTD_UBI_BLOCK=y
> +# CONFIG_MTD_UBI_FASTMAP is not set
> +# CONFIG_MTD_UBI_GLUEBI is not set
> +CONFIG_MTD_UBI_WL_THRESHOLD=4096
> +CONFIG_MUTEX_SPIN_ON_OWNER=y
> +CONFIG_MVEBU_CLK_COMMON=y
> +CONFIG_MVEBU_CLK_COREDIV=y
> +CONFIG_MVEBU_CLK_CPU=y
> +CONFIG_MVEBU_DEVBUS=y
> +CONFIG_MVEBU_MBUS=y
> +CONFIG_MVMDIO=y
> +CONFIG_MVNETA=y
> +CONFIG_MVNETA_BM=y
> +CONFIG_MVNETA_BM_ENABLE=y
> +CONFIG_MVPP2=y
> +CONFIG_MVSW61XX_PHY=y
> +CONFIG_MV_XOR=y
> +CONFIG_NEED_DMA_MAP_STATE=y
> +CONFIG_NEON=y
> +CONFIG_NET_DSA=y
> +CONFIG_NET_DSA_LEGACY=y
> +CONFIG_NET_DSA_MV88E6XXX=y
> +CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
> +# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
> +# CONFIG_NET_DSA_REALTEK_SMI is not set
> +CONFIG_NET_DSA_TAG_DSA=y
> +CONFIG_NET_DSA_TAG_EDSA=y
> +# CONFIG_NET_DSA_VITESSE_VSC73XX is not set
> +CONFIG_NET_FLOW_LIMIT=y
> +CONFIG_NET_SWITCHDEV=y
> +CONFIG_NLS=y
> +CONFIG_NOP_USB_XCEIV=y
> +CONFIG_NO_BOOTMEM=y
> +CONFIG_NR_CPUS=4
> +CONFIG_NVMEM=y
> +CONFIG_OF=y
> +CONFIG_OF_ADDRESS=y
> +CONFIG_OF_EARLY_FLATTREE=y
> +CONFIG_OF_FLATTREE=y
> +CONFIG_OF_GPIO=y
> +CONFIG_OF_IRQ=y
> +CONFIG_OF_KOBJ=y
> +CONFIG_OF_MDIO=y
> +CONFIG_OF_NET=y
> +CONFIG_OF_RESERVED_MEM=y
> +CONFIG_OLD_SIGACTION=y
> +CONFIG_OLD_SIGSUSPEND3=y
> +CONFIG_ORION_WATCHDOG=y
> +CONFIG_OUTER_CACHE=y
> +CONFIG_OUTER_CACHE_SYNC=y
> +CONFIG_PADATA=y
> +CONFIG_PAGE_OFFSET=0xC0000000
> +CONFIG_PCI=y
> +CONFIG_PCI_DOMAINS=y
> +CONFIG_PCI_DOMAINS_GENERIC=y
> +CONFIG_PCI_MSI=y
> +CONFIG_PCI_MSI_IRQ_DOMAIN=y
> +CONFIG_PCI_MVEBU=y
> +# CONFIG_PCI_V3_SEMI is not set
> +CONFIG_PERF_USE_VMALLOC=y
> +CONFIG_PGTABLE_LEVELS=2
> +CONFIG_PHYLIB=y
> +CONFIG_PHYLINK=y
> +# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_ARMADA_370=y
> +CONFIG_PINCTRL_ARMADA_38X=y
> +CONFIG_PINCTRL_ARMADA_XP=y
> +CONFIG_PINCTRL_MVEBU=y
> +# CONFIG_PINCTRL_SINGLE is not set
> +CONFIG_PJ4B_ERRATA_4742=y
> +# CONFIG_PL310_ERRATA_588369 is not set
> +# CONFIG_PL310_ERRATA_727915 is not set
> +CONFIG_PL310_ERRATA_753970=y
> +# CONFIG_PL310_ERRATA_769419 is not set
> +CONFIG_PLAT_ORION=y
> +CONFIG_PM_OPP=y
> +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=11
> +CONFIG_PWM=y
> +CONFIG_PWM_SYSFS=y
> +CONFIG_RATIONAL=y
> +CONFIG_RCU_NEED_SEGCBLIST=y
> +CONFIG_RCU_STALL_COMMON=y
> +CONFIG_REFCOUNT_FULL=y
> +CONFIG_REGMAP=y
> +CONFIG_REGMAP_I2C=y
> +CONFIG_REGMAP_MMIO=y
> +CONFIG_REGMAP_SPI=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_RFS_ACCEL=y
> +CONFIG_RPS=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_ARMADA38X=y
> +CONFIG_RTC_DRV_MV=y
> +CONFIG_RTC_I2C_AND_SPI=y
> +CONFIG_RTC_MC146818_LIB=y
> +CONFIG_RWSEM_SPIN_ON_OWNER=y
> +CONFIG_RWSEM_XCHGADD_ALGORITHM=y
> +CONFIG_SATA_AHCI_PLATFORM=y
> +CONFIG_SATA_MV=y
> +CONFIG_SATA_PMP=y
> +CONFIG_SCSI=y
> +CONFIG_SENSORS_PWM_FAN=y
> +CONFIG_SENSORS_TMP421=y
> +CONFIG_SERIAL_8250_DW=y
> +CONFIG_SERIAL_8250_FSL=y
> +CONFIG_SERIAL_MVEBU_CONSOLE=y
> +CONFIG_SERIAL_MVEBU_UART=y
> +CONFIG_SFP=y
> +CONFIG_SGL_ALLOC=y
> +CONFIG_SG_POOL=y
> +CONFIG_SMP=y
> +CONFIG_SMP_ON_UP=y
> +CONFIG_SOC_BUS=y
> +CONFIG_SPARSE_IRQ=y
> +CONFIG_SPI=y
> +# CONFIG_SPI_ARMADA_3700 is not set
> +CONFIG_SPI_MASTER=y
> +CONFIG_SPI_MEM=y
> +CONFIG_SPI_ORION=y
> +CONFIG_SRAM=y
> +CONFIG_SRAM_EXEC=y
> +CONFIG_SRCU=y
> +CONFIG_SWCONFIG=y
> +CONFIG_SWPHY=y
> +CONFIG_SWP_EMULATE=y
> +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> +CONFIG_THERMAL=y
> +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
> +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
> +CONFIG_THERMAL_GOV_STEP_WISE=y
> +CONFIG_THERMAL_HWMON=y
> +CONFIG_THERMAL_OF=y
> +# CONFIG_THUMB2_KERNEL is not set
> +CONFIG_TICK_CPU_ACCOUNTING=y
> +CONFIG_TIMER_OF=y
> +CONFIG_TIMER_PROBE=y
> +CONFIG_TREE_RCU=y
> +CONFIG_TREE_SRCU=y
> +CONFIG_UBIFS_FS=y
> +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
> +CONFIG_UBIFS_FS_LZO=y
> +CONFIG_UBIFS_FS_ZLIB=y
> +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
> +CONFIG_USB=y
> +CONFIG_USB_COMMON=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_HCD_ORION=y
> +CONFIG_USB_EHCI_HCD_PLATFORM=y
> +CONFIG_USB_LEDS_TRIGGER_USBPORT=y
> +CONFIG_USB_PHY=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_SUPPORT=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_MVEBU=y
> +CONFIG_USB_XHCI_PLATFORM=y
> +CONFIG_USE_OF=y
> +CONFIG_VFP=y
> +CONFIG_VFPv3=y
> +CONFIG_WATCHDOG_CORE=y
> +CONFIG_XPS=y
> +CONFIG_XZ_DEC_ARM=y
> +CONFIG_XZ_DEC_BCJ=y
> +CONFIG_ZBOOT_ROM_BSS=0x0
> +CONFIG_ZBOOT_ROM_TEXT=0x0
> +CONFIG_ZLIB_DEFLATE=y
> +CONFIG_ZLIB_INFLATE=y
> diff --git a/target/linux/mvebu/cortexa53/config-default b/target/linux/mvebu/cortexa53/config-4.14
> similarity index 100%
> rename from target/linux/mvebu/cortexa53/config-default
> rename to target/linux/mvebu/cortexa53/config-4.14
> diff --git a/target/linux/mvebu/cortexa53/config-4.19 b/target/linux/mvebu/cortexa53/config-4.19
> new file mode 100644
> index 0000000000..67d6d4209d
> --- /dev/null
> +++ b/target/linux/mvebu/cortexa53/config-4.19
> @@ -0,0 +1,114 @@
> +CONFIG_64BIT=y
> +# CONFIG_ACPI is not set
> +CONFIG_ARCH_DMA_ADDR_T_64BIT=y
> +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
> +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
> +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
> +CONFIG_ARCH_HAS_KCOV=y
> +CONFIG_ARCH_MMAP_RND_BITS=18
> +CONFIG_ARCH_MMAP_RND_BITS_MAX=24
> +CONFIG_ARCH_MMAP_RND_BITS_MIN=18
> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
> +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
> +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
> +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
> +CONFIG_ARCH_PROC_KCORE_TEXT=y
> +CONFIG_ARCH_SELECT_MEMORY_MODEL=y
> +CONFIG_ARCH_SPARSEMEM_DEFAULT=y
> +CONFIG_ARCH_SPARSEMEM_ENABLE=y
> +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
> +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
> +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
> +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
> +CONFIG_ARCH_WANT_FRAME_POINTERS=y
> +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
> +CONFIG_ARM64=y
> +# CONFIG_ARM64_16K_PAGES is not set
> +CONFIG_ARM64_4K_PAGES=y
> +# CONFIG_ARM64_64K_PAGES is not set
> +CONFIG_ARM64_CONT_SHIFT=4
> +# CONFIG_ARM64_CRYPTO is not set
> +# CONFIG_ARM64_HW_AFDBM is not set
> +# CONFIG_ARM64_LSE_ATOMICS is not set
> +CONFIG_ARM64_PAGE_SHIFT=12
> +# CONFIG_ARM64_PAN is not set
> +# CONFIG_ARM64_PMEM is not set
> +# CONFIG_ARM64_PTDUMP_CORE is not set
> +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
> +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
> +CONFIG_ARM64_SSBD=y
> +CONFIG_ARM64_SVE=y
> +# CONFIG_ARM64_UAO is not set
> +CONFIG_ARM64_VA_BITS=39
> +CONFIG_ARM64_VA_BITS_39=y
> +# CONFIG_ARM64_VA_BITS_48 is not set
> +# CONFIG_ARM64_VHE is not set
> +CONFIG_ARMADA_37XX_CLK=y
> +CONFIG_ARMADA_AP806_SYSCON=y
> +CONFIG_ARMADA_CP110_SYSCON=y
> +CONFIG_ARM_AMBA=y
> +CONFIG_ARM_ARCH_TIMER=y
> +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
> +CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
> +CONFIG_ARM_GIC_V2M=y
> +CONFIG_ARM_GIC_V3=y
> +CONFIG_ARM_GIC_V3_ITS=y
> +# CONFIG_ARM_PL172_MPMC is not set
> +CONFIG_ARM_PSCI_FW=y
> +# CONFIG_ARM_SP805_WATCHDOG is not set
> +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
> +# CONFIG_DEBUG_ALIGN_RODATA is not set
> +CONFIG_FRAME_POINTER=y
> +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
> +CONFIG_GENERIC_CSUM=y
> +CONFIG_GENERIC_IRQ_MIGRATION=y
> +CONFIG_GENERIC_PINCONF=y
> +CONFIG_GENERIC_TIME_VSYSCALL=y
> +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
> +CONFIG_HAVE_ARCH_HUGE_VMAP=y
> +CONFIG_HAVE_ARCH_KASAN=y
> +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
> +CONFIG_HAVE_ARCH_VMAP_STACK=y
> +CONFIG_HAVE_CMPXCHG_DOUBLE=y
> +CONFIG_HAVE_CMPXCHG_LOCAL=y
> +CONFIG_HAVE_DEBUG_BUGVERBOSE=y
> +CONFIG_HAVE_GENERIC_GUP=y
> +CONFIG_HAVE_MEMORY_PRESENT=y
> +CONFIG_HAVE_PATA_PLATFORM=y
> +CONFIG_HAVE_RCU_TABLE_FREE=y
> +CONFIG_HOLES_IN_ZONE=y
> +# CONFIG_HUGETLBFS is not set
> +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
> +CONFIG_MFD_SYSCON=y
> +CONFIG_MMC_SDHCI_XENON=y
> +CONFIG_MODULES_USE_ELF_RELA=y
> +CONFIG_MVEBU_GICP=y
> +CONFIG_MVEBU_ICU=y
> +CONFIG_MVEBU_ODMI=y
> +CONFIG_MVEBU_PIC=y
> +CONFIG_NEED_SG_DMA_LENGTH=y
> +# CONFIG_NUMA is not set
> +CONFIG_PARTITION_PERCPU=y
> +CONFIG_PCI_AARDVARK=y
> +CONFIG_PCI_BUS_ADDR_T_64BIT=y
> +CONFIG_PGTABLE_LEVELS=3
> +CONFIG_PHYS_ADDR_T_64BIT=y
> +CONFIG_PINCTRL_ARMADA_37XX=y
> +CONFIG_PINCTRL_ARMADA_AP806=y
> +CONFIG_PINCTRL_ARMADA_CP110=y
> +CONFIG_POWER_RESET=y
> +CONFIG_POWER_SUPPLY=y
> +# CONFIG_RANDOMIZE_BASE is not set
> +CONFIG_REGULATOR_GPIO=y
> +# CONFIG_SERIAL_AMBA_PL011 is not set
> +CONFIG_SPARSEMEM=y
> +CONFIG_SPARSEMEM_EXTREME=y
> +CONFIG_SPARSEMEM_MANUAL=y
> +CONFIG_SPARSEMEM_VMEMMAP=y
> +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
> +CONFIG_SPI_ARMADA_3700=y
> +CONFIG_SYSCTL_EXCEPTION_TRACE=y
> +CONFIG_SYS_SUPPORTS_HUGETLBFS=y
> +CONFIG_THREAD_INFO_IN_TASK=y
> +CONFIG_UNMAP_KERNEL_AT_EL0=y
> +CONFIG_VMAP_STACK=y
> diff --git a/target/linux/mvebu/cortexa72/config-default b/target/linux/mvebu/cortexa72/config-4.14
> similarity index 100%
> rename from target/linux/mvebu/cortexa72/config-default
> rename to target/linux/mvebu/cortexa72/config-4.14
> diff --git a/target/linux/mvebu/cortexa72/config-4.19 b/target/linux/mvebu/cortexa72/config-4.19
> new file mode 100644
> index 0000000000..9143e4e6d4
> --- /dev/null
> +++ b/target/linux/mvebu/cortexa72/config-4.19
> @@ -0,0 +1,122 @@
> +CONFIG_64BIT=y
> +# CONFIG_ACPI is not set
> +CONFIG_ARCH_DMA_ADDR_T_64BIT=y
> +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
> +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
> +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
> +CONFIG_ARCH_HAS_KCOV=y
> +CONFIG_ARCH_MMAP_RND_BITS=18
> +CONFIG_ARCH_MMAP_RND_BITS_MAX=24
> +CONFIG_ARCH_MMAP_RND_BITS_MIN=18
> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
> +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
> +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
> +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
> +CONFIG_ARCH_PROC_KCORE_TEXT=y
> +CONFIG_ARCH_SELECT_MEMORY_MODEL=y
> +CONFIG_ARCH_SPARSEMEM_DEFAULT=y
> +CONFIG_ARCH_SPARSEMEM_ENABLE=y
> +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
> +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
> +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
> +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
> +CONFIG_ARCH_WANT_FRAME_POINTERS=y
> +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
> +CONFIG_ARM64=y
> +# CONFIG_ARM64_16K_PAGES is not set
> +CONFIG_ARM64_4K_PAGES=y
> +# CONFIG_ARM64_64K_PAGES is not set
> +CONFIG_ARM64_CONT_SHIFT=4
> +# CONFIG_ARM64_CRYPTO is not set
> +# CONFIG_ARM64_HW_AFDBM is not set
> +# CONFIG_ARM64_LSE_ATOMICS is not set
> +CONFIG_ARM64_PAGE_SHIFT=12
> +# CONFIG_ARM64_PAN is not set
> +# CONFIG_ARM64_PMEM is not set
> +# CONFIG_ARM64_PTDUMP_CORE is not set
> +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
> +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
> +CONFIG_ARM64_SSBD=y
> +CONFIG_ARM64_SVE=y
> +# CONFIG_ARM64_UAO is not set
> +CONFIG_ARM64_VA_BITS=39
> +CONFIG_ARM64_VA_BITS_39=y
> +# CONFIG_ARM64_VA_BITS_48 is not set
> +# CONFIG_ARM64_VHE is not set
> +CONFIG_ARMADA_37XX_CLK=y
> +CONFIG_ARMADA_AP806_SYSCON=y
> +CONFIG_ARMADA_CP110_SYSCON=y
> +CONFIG_ARM_AMBA=y
> +CONFIG_ARM_ARCH_TIMER=y
> +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
> +CONFIG_ARM_GIC_V2M=y
> +CONFIG_ARM_GIC_V3=y
> +CONFIG_ARM_GIC_V3_ITS=y
> +# CONFIG_ARM_PL172_MPMC is not set
> +CONFIG_ARM_PSCI_FW=y
> +# CONFIG_ARM_SP805_WATCHDOG is not set
> +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
> +# CONFIG_DEBUG_ALIGN_RODATA is not set
> +CONFIG_FRAME_POINTER=y
> +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
> +CONFIG_GENERIC_CSUM=y
> +CONFIG_GENERIC_IRQ_MIGRATION=y
> +CONFIG_GENERIC_PINCONF=y
> +CONFIG_GENERIC_TIME_VSYSCALL=y
> +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
> +CONFIG_HAVE_ARCH_HUGE_VMAP=y
> +CONFIG_HAVE_ARCH_KASAN=y
> +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
> +CONFIG_HAVE_ARCH_VMAP_STACK=y
> +CONFIG_HAVE_CMPXCHG_DOUBLE=y
> +CONFIG_HAVE_CMPXCHG_LOCAL=y
> +CONFIG_HAVE_DEBUG_BUGVERBOSE=y
> +CONFIG_HAVE_GENERIC_GUP=y
> +CONFIG_HAVE_MEMORY_PRESENT=y
> +CONFIG_HAVE_PATA_PLATFORM=y
> +CONFIG_HAVE_RCU_TABLE_FREE=y
> +CONFIG_HOLES_IN_ZONE=y
> +# CONFIG_HUGETLBFS is not set
> +CONFIG_HW_RANDOM_OMAP=y
> +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
> +CONFIG_MARVELL_10G_PHY=y
> +CONFIG_MFD_SYSCON=y
> +CONFIG_MMC_SDHCI_XENON=y
> +CONFIG_MODULES_USE_ELF_RELA=y
> +CONFIG_MVEBU_GICP=y
> +CONFIG_MVEBU_ICU=y
> +CONFIG_MVEBU_ODMI=y
> +CONFIG_MVEBU_PIC=y
> +CONFIG_MV_XOR_V2=y
> +CONFIG_NEED_SG_DMA_LENGTH=y
> +# CONFIG_NUMA is not set
> +CONFIG_PARTITION_PERCPU=y
> +CONFIG_PCIEAER=y
> +CONFIG_PCIEPORTBUS=y
> +CONFIG_PCIE_ARMADA_8K=y
> +CONFIG_PCIE_DW=y
> +CONFIG_PCIE_DW_HOST=y
> +# CONFIG_PCI_AARDVARK is not set
> +CONFIG_PCI_BUS_ADDR_T_64BIT=y
> +CONFIG_PGTABLE_LEVELS=3
> +CONFIG_PHYS_ADDR_T_64BIT=y
> +CONFIG_PHY_MVEBU_CP110_COMPHY=y
> +CONFIG_PINCTRL_ARMADA_37XX=y
> +CONFIG_PINCTRL_ARMADA_AP806=y
> +CONFIG_PINCTRL_ARMADA_CP110=y
> +CONFIG_POWER_RESET=y
> +CONFIG_POWER_SUPPLY=y
> +# CONFIG_RANDOMIZE_BASE is not set
> +CONFIG_RAS=y
> +CONFIG_REGULATOR_GPIO=y
> +# CONFIG_SERIAL_AMBA_PL011 is not set
> +CONFIG_SPARSEMEM=y
> +CONFIG_SPARSEMEM_EXTREME=y
> +CONFIG_SPARSEMEM_MANUAL=y
> +CONFIG_SPARSEMEM_VMEMMAP=y
> +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
> +CONFIG_SYSCTL_EXCEPTION_TRACE=y
> +CONFIG_SYS_SUPPORTS_HUGETLBFS=y
> +CONFIG_THREAD_INFO_IN_TASK=y
> +CONFIG_UNMAP_KERNEL_AT_EL0=y
> +CONFIG_VMAP_STACK=y
> diff --git a/target/linux/mvebu/files-4.19/arch/arm/boot/dts/armada-385-linksys-venom.dts b/target/linux/mvebu/files-4.19/arch/arm/boot/dts/armada-385-linksys-venom.dts
> new file mode 100644
> index 0000000000..c152c14c6b
> --- /dev/null
> +++ b/target/linux/mvebu/files-4.19/arch/arm/boot/dts/armada-385-linksys-venom.dts
> @@ -0,0 +1,213 @@
> +/*
> + * Device Tree file for the Linksys WRT32X (Venom)
> + *
> + * Copyright (C) 2017 Imre Kaloz <kaloz at openwrt.org>
> + *
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without
> + * any warranty of any kind, whether express or implied.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "armada-385-linksys.dtsi"
> +
> +/ {
> + model = "Linksys WRT32X";
> + compatible = "linksys,venom", "linksys,armada385", "marvell,armada385",
> + "marvell,armada380";
> +
> + chosen {
> + bootargs = "console=ttyS0,115200";
> + stdout-path = "serial0:115200n8";
> + append-rootblock = "root=/dev/mtdblock";
> + };
> +};
> +
> +&expander0 {
> + wan_amber at 0 {
> + label = "venom:amber:wan";
> + reg = <0x0>;
> + };
> +
> + wan_blue at 1 {
> + label = "venom:blue:wan";
> + reg = <0x1>;
> + };
> +
> + usb2 at 5 {
> + label = "venom:blue:usb2";
> + reg = <0x5>;
> + };
> +
> + usb3_1 at 6 {
> + label = "venom:blue:usb3_1";
> + reg = <0x6>;
> + };
> +
> + usb3_2 at 7 {
> + label = "venom:blue:usb3_2";
> + reg = <0x7>;
> + };
> +
> + wps_blue at 8 {
> + label = "venom:blue:wps";
> + reg = <0x8>;
> + };
> +
> + wps_amber at 9 {
> + label = "venom:amber:wps";
> + reg = <0x9>;
> + };
> +};
> +
> +&gpio_leds {
> + power {
> + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
> + label = "venom:blue:power";
> + };
> +
> + sata {
> + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
> + label = "venom:blue:sata";
> + };
> +
> + wlan_2g {
> + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> + label = "venom:blue:wlan_2g";
> + };
> +
> + wlan_5g {
> + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
> + label = "venom:blue:wlan_5g";
> + };
> +};
> +
> +&gpio_leds_pins {
> + marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
> +};
> +
> +&nand {
> + /* Spansion S34ML02G2 256MiB, OEM Layout */
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "u-boot";
> + reg = <0x0000000 0x200000>; /* 2MB */
> + read-only;
> + };
> +
> + partition at 200000 {
> + label = "u_env";
> + reg = <0x200000 0x20000>; /* 128KB */
> + };
> +
> + partition at 220000 {
> + label = "s_env";
> + reg = <0x220000 0x40000>; /* 256KB */
> + };
> +
> + partition at 180000 {
> + label = "unused_area";
> + reg = <0x260000 0x5c0000>; /* 5.75MB */
> + };
> +
> + partition at 7e0000 {
> + label = "devinfo";
> + reg = <0x7e0000 0x40000>; /* 256KB */
> + read-only;
> + };
> +
> + /* kernel1 overlaps with rootfs1 by design */
> + partition at 900000 {
> + label = "kernel1";
> + reg = <0x900000 0x7b00000>; /* 123MB */
> + };
> +
> + partition at c00000 {
> + label = "rootfs1";
> + reg = <0xc00000 0x7800000>; /* 120MB */
> + };
> +
> + /* kernel2 overlaps with rootfs2 by design */
> + partition at 8400000 {
> + label = "kernel2";
> + reg = <0x8400000 0x7b00000>; /* 123MB */
> + };
> +
> + partition at 8700000 {
> + label = "rootfs2";
> + reg = <0x8700000 0x7800000>; /* 120MB */
> + };
> +
> + /* last MB is for the BBT, not writable */
> + partition at ff00000 {
> + label = "BBT";
> + reg = <0xff00000 0x100000>;
> + };
> + };
> +};
> +
> +
> +&pcie1 {
> + mwlwifi {
> + marvell,chainmask = <4 4>;
> + };
> +};
> +
> +&pcie2 {
> + mwlwifi {
> + marvell,chainmask = <4 4>;
> + };
> +};
> +
> +&sdhci {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdhci_pins>;
> + no-1-8-v;
> + non-removable;
> + wp-inverted;
> + bus-width = <8>;
> + status = "okay";
> +};
> +
> +&usb3_1_vbus {
> + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&usb3_1_vbus_pins {
> + marvell,pins = "mpp44";
> +};
> diff --git a/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts
> new file mode 100644
> index 0000000000..ef90a1bd38
> --- /dev/null
> +++ b/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
> + * Copyright (C) 2018 Marvell
> + *
> + * Romain Perier <romain.perier at free-electrons.com>
> + * Konstantin Porotchkin <kostap at marvell.com>
> + *
> + */
> +
> +#include "armada-3720-espressobin.dts"
> +
> +/ {
> + model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
> + compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
> + "marvell,armada3720", "marvell,armada3710";
> +};
> +
> +&sdhci0 {
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mmccard: mmccard at 0 {
> + compatible = "mmc-card";
> + reg = <0>;
> + };
> +};
> diff --git a/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts
> new file mode 100644
> index 0000000000..2b565ca8d8
> --- /dev/null
> +++ b/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC
> + * Copyright (C) 2018 Marvell
> + *
> + * Romain Perier <romain.perier at free-electrons.com>
> + * Konstantin Porotchkin <kostap at marvell.com>
> + *
> + */
> +
> +#include "armada-3720-espressobin.dts"
> +
> +/ {
> + model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)";
> + compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
> + "globalscale,espressobin", "marvell,armada3720",
> + "marvell,armada3710";
> +};
> +
> +&ports {
> + port at 1 {
> + reg = <1>;
> + label = "lan1";
> + phy-handle = <&switch0phy0>;
> + };
> +
> + port at 3 {
> + reg = <3>;
> + label = "wan";
> + phy-handle = <&switch0phy2>;
> + };
> +};
> +
> +&sdhci0 {
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mmccard: mmccard at 0 {
> + compatible = "mmc-card";
> + reg = <0>;
> + };
> +};
> diff --git a/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts
> new file mode 100644
> index 0000000000..8a408c3c48
> --- /dev/null
> +++ b/target/linux/mvebu/files-4.19/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7
> + * Copyright (C) 2018 Marvell
> + *
> + * Romain Perier <romain.perier at free-electrons.com>
> + * Konstantin Porotchkin <kostap at marvell.com>
> + *
> + */
> +
> +#include "armada-3720-espressobin.dts"
> +
> +/ {
> + model = "Globalscale Marvell ESPRESSOBin Board V7";
> + compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
> + "marvell,armada3720", "marvell,armada3710";
> +};
> +
> +&ports {
> + port at 1 {
> + reg = <1>;
> + label = "lan1";
> + phy-handle = <&switch0phy0>;
> + };
> +
> + port at 3 {
> + reg = <3>;
> + label = "wan";
> + phy-handle = <&switch0phy2>;
> + };
> +};
> diff --git a/target/linux/mvebu/patches-4.19/002-add_powertables.patch b/target/linux/mvebu/patches-4.19/002-add_powertables.patch
> new file mode 100644
> index 0000000000..c2fb748d5d
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/002-add_powertables.patch
> @@ -0,0 +1,770 @@
> +--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
> ++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
> +@@ -212,11 +212,19 @@
> + &pcie1 {
> + /* Marvell 88W8864, 5GHz-only */
> + status = "okay";
> ++
> ++ mwlwifi {
> ++ marvell,2ghz = <0>;
> ++ };
> + };
> +
> + &pcie2 {
> + /* Marvell 88W8864, 2GHz-only */
> + status = "okay";
> ++
> ++ mwlwifi {
> ++ marvell,5ghz = <0>;
> ++ };
> + };
> +
> + &pinctrl {
> +--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
> ++++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
> +@@ -142,3 +142,205 @@
> + };
> + };
> + };
> ++
> ++&pcie1 {
> ++ mwlwifi {
> ++ marvell,chainmask = <2 2>;
> ++ marvell,powertable {
> ++ AU =
> ++ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
> ++ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
> ++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
> ++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
> ++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
> ++ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
> ++ CA =
> ++ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
> ++ CN =
> ++ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
> ++ ETSI =
> ++ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
> ++ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
> ++ FCC =
> ++ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
> ++ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
> ++ };
> ++ };
> ++};
> ++
> ++&pcie2 {
> ++ mwlwifi {
> ++ marvell,chainmask = <2 2>;
> ++ marvell,powertable {
> ++ AU =
> ++ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
> ++ CA =
> ++ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
> ++ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
> ++ CN =
> ++ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
> ++ ETSI =
> ++ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
> ++ FCC =
> ++ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
> ++ };
> ++ };
> ++};
> +--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
> ++++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
> +@@ -142,3 +142,205 @@
> + };
> + };
> + };
> ++
> ++&pcie1 {
> ++ mwlwifi {
> ++ marvell,chainmask = <4 4>;
> ++ marvell,powertable {
> ++ AU =
> ++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
> ++ CA =
> ++ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
> ++ CN =
> ++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
> ++ ETSI =
> ++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
> ++ FCC =
> ++ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
> ++ };
> ++ };
> ++};
> ++
> ++&pcie2 {
> ++ mwlwifi {
> ++ marvell,chainmask = <4 4>;
> ++ marvell,powertable {
> ++ AU =
> ++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
> ++ CA =
> ++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
> ++ CN =
> ++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
> ++ ETSI =
> ++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
> ++ FCC =
> ++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
> ++ };
> ++ };
> ++};
> +--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
> ++++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
> +@@ -142,3 +142,205 @@
> + };
> + };
> + };
> ++
> ++&pcie1 {
> ++ mwlwifi {
> ++ marvell,chainmask = <4 4>;
> ++ marvell,powertable {
> ++ AU =
> ++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
> ++ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
> ++ CA =
> ++ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
> ++ CN =
> ++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
> ++ ETSI =
> ++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
> ++ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
> ++ FCC =
> ++ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
> ++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
> ++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
> ++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
> ++ };
> ++ };
> ++};
> ++
> ++&pcie2 {
> ++ mwlwifi {
> ++ marvell,chainmask = <4 4>;
> ++ marvell,powertable {
> ++ AU =
> ++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
> ++ CA =
> ++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
> ++ CN =
> ++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
> ++ ETSI =
> ++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
> ++ FCC =
> ++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
> ++ };
> ++ };
> ++};
> +--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
> ++++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
> +@@ -157,6 +157,18 @@
> + };
> + };
> +
> ++&pcie1 {
> ++ mwlwifi {
> ++ marvell,chainmask = <4 4>;
> ++ };
> ++};
> ++
> ++&pcie2 {
> ++ mwlwifi {
> ++ marvell,chainmask = <4 4>;
> ++ };
> ++};
> ++
> + &sdhci {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdhci_pins>;
> +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> +@@ -272,12 +272,100 @@
> + pcie at 2,0 {
> + /* Port 0, Lane 1 */
> + status = "okay";
> ++
> ++ mwlwifi {
> ++ marvell,5ghz = <0>;
> ++ marvell,chainmask = <4 4>;
> ++ marvell,powertable {
> ++ FCC =
> ++ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
> ++
> ++ ETSI =
> ++ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
> ++ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
> ++ };
> ++ };
> + };
> +
> + /* Second mini-PCIe port */
> + pcie at 3,0 {
> + /* Port 0, Lane 3 */
> + status = "okay";
> ++
> ++ mwlwifi {
> ++ marvell,2ghz = <0>;
> ++ marvell,chainmask = <4 4>;
> ++ marvell,powertable {
> ++ FCC =
> ++ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
> ++ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
> ++ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
> ++ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
> ++ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
> ++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
> ++ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
> ++
> ++ ETSI =
> ++ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
> ++ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
> ++ };
> ++ };
> + };
> + };
> +
> diff --git a/target/linux/mvebu/patches-4.19/003-add_switch_nodes.patch b/target/linux/mvebu/patches-4.19/003-add_switch_nodes.patch
> new file mode 100644
> index 0000000000..b208638916
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/003-add_switch_nodes.patch
> @@ -0,0 +1,40 @@
> +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> +@@ -257,6 +257,16 @@
> + };
> + };
> + };
> ++
> ++ mvsw61xx {
> ++ compatible = "marvell,88e6172";
> ++ status = "okay";
> ++ reg = <0x10>;
> ++
> ++ mii-bus = <&mdio>;
> ++ cpu-port-0 = <5>;
> ++ cpu-port-1 = <6>;
> ++ };
> + };
> +
> + &pciec {
> +--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
> ++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
> +@@ -82,6 +82,18 @@
> + linux,default-trigger = "disk-activity";
> + };
> + };
> ++
> ++ mvsw61xx {
> ++ #address-cells = <1>;
> ++ #size-cells = <0>;
> ++ compatible = "marvell,88e6176";
> ++ status = "okay";
> ++ reg = <0x10>;
> ++
> ++ mii-bus = <&mdio>;
> ++ cpu-port-0 = <5>;
> ++ cpu-port-1 = <6>;
> ++ };
> + };
> +
> + &ahci0 {
> diff --git a/target/linux/mvebu/patches-4.19/004-add_sata_disk_activity_trigger.patch b/target/linux/mvebu/patches-4.19/004-add_sata_disk_activity_trigger.patch
> new file mode 100644
> index 0000000000..2cb8f25490
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/004-add_sata_disk_activity_trigger.patch
> @@ -0,0 +1,39 @@
> +From 172230195068703b78ad5733a09492f5d6814c09 Mon Sep 17 00:00:00 2001
> +From: Ansuel Smith <ansuelsmth at gmail.com>
> +Date: Tue, 28 Feb 2017 14:15:50 +0100
> +Subject: [PATCH] ARM: dts: armada: Add default trigger for sata led
> +
> +In others board we have the sata led set to function
> +with the sata led trigger by default.
> +This patch makes the same for these board that have sata
> +led but get disabled by not associating it to any trigger.
> +
> +Signed-off-by: Ansuel Smith <ansuelsmth at gmail.com>
> +Acked-by: Jason Cooper <jason at lakedaemon.net>
> +Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
> +---
> + arch/arm/boot/dts/armada-385-linksys-caiman.dts | 1 +
> + arch/arm/boot/dts/armada-385-linksys-cobra.dts | 1 +
> + arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 1 +
> + 3 files changed, 3 insertions(+)
> +
> +--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
> ++++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
> +@@ -68,6 +68,7 @@
> +
> + sata {
> + label = "caiman:white:sata";
> ++ linux,default-trigger = "disk-activity";
> + };
> + };
> +
> +--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
> ++++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
> +@@ -68,6 +68,7 @@
> +
> + sata {
> + label = "cobra:white:sata";
> ++ linux,default-trigger = "disk-activity";
> + };
> + };
> +
> diff --git a/target/linux/mvebu/patches-4.19/005-linksys_hardcode_nand_ecc_settings.patch b/target/linux/mvebu/patches-4.19/005-linksys_hardcode_nand_ecc_settings.patch
> new file mode 100644
> index 0000000000..dfe13bae7b
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/005-linksys_hardcode_nand_ecc_settings.patch
> @@ -0,0 +1,17 @@
> +Newer Linksys boards might come with a Winbond W29N02GV which can be
> +configured in different ways. Make sure we configure it the same way
> +as the older chips so everything keeps working.
> +
> +Signed-off-by: Imre Kaloz <kaloz at openwrt.org>
> +
> +--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
> ++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
> +@@ -160,6 +160,8 @@
> + reg = <0>;
> + label = "pxa3xx_nand-0";
> + nand-rb = <0>;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> + marvell,nand-keep-config;
> + nand-on-flash-bbt;
> + };
> diff --git a/target/linux/mvebu/patches-4.19/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-4.19/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
> new file mode 100644
> index 0000000000..6a84b1397b
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
> @@ -0,0 +1,201 @@
> +From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
> +From: Adrian Panella <ianchi74 at outlook.com>
> +Date: Thu, 9 Mar 2017 09:37:17 +0100
> +Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
> +
> +The command-line arguments provided by the boot loader will be
> +appended to a new device tree property: bootloader-args.
> +If there is a property "append-rootblock" in DT under /chosen
> +and a root= option in bootloaders command line it will be parsed
> +and added to DT bootargs with the form: <append-rootblock>XX.
> +Only command line ATAG will be processed, the rest of the ATAGs
> +sent by bootloader will be ignored.
> +This is usefull in dual boot systems, to get the current root partition
> +without afecting the rest of the system.
> +
> +Signed-off-by: Adrian Panella <ianchi74 at outlook.com>
> +
> +This patch has been modified to be mvebu specific. The original patch
> +did not pass the bootloader cmdline on if no append-rootblock stanza
> +was found, resulting in blank cmdline and failure to boot.
> +
> +Signed-off-by: Michael Gray <michael.gray at lantisproject.com>
> +---
> + arch/arm/Kconfig | 11 +++++
> + arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
> + init/main.c | 16 ++++++++
> + 3 files changed, 98 insertions(+), 1 deletion(-)
> +
> +--- a/arch/arm/Kconfig
> ++++ b/arch/arm/Kconfig
> +@@ -1925,6 +1925,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
> + The command-line arguments provided by the boot loader will be
> + appended to the the device tree bootargs property.
> +
> ++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
> ++ bool "Append rootblock parsing bootloader's kernel arguments"
> ++ help
> ++ The command-line arguments provided by the boot loader will be
> ++ appended to a new device tree property: bootloader-args.
> ++ If there is a property "append-rootblock" in DT under /chosen
> ++ and a root= option in bootloaders command line it will be parsed
> ++ and added to DT bootargs with the form: <append-rootblock>XX.
> ++ Only command line ATAG will be processed, the rest of the ATAGs
> ++ sent by bootloader will be ignored.
> ++
> + endchoice
> +
> + config CMDLINE
> +--- a/arch/arm/boot/compressed/atags_to_fdt.c
> ++++ b/arch/arm/boot/compressed/atags_to_fdt.c
> +@@ -4,6 +4,8 @@
> +
> + #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
> + #define do_extend_cmdline 1
> ++#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
> ++#define do_extend_cmdline 1
> + #else
> + #define do_extend_cmdline 0
> + #endif
> +@@ -67,6 +69,65 @@ static uint32_t get_cell_size(const void
> + return cell_size;
> + }
> +
> ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
> ++
> ++static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
> ++{
> ++ char *ptr, *end;
> ++ char *root="root=";
> ++ int i, l;
> ++ const char *rootblock;
> ++
> ++ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
> ++ ptr = str - 1;
> ++
> ++ do {
> ++ //first find an 'r' at the begining or after a space
> ++ do {
> ++ ptr++;
> ++ ptr = strchr(ptr, 'r');
> ++ if(!ptr) return dest;
> ++
> ++ } while (ptr != str && *(ptr-1) != ' ');
> ++
> ++ //then check for the rest
> ++ for(i = 1; i <= 4; i++)
> ++ if(*(ptr+i) != *(root+i)) break;
> ++
> ++ } while (i != 5);
> ++
> ++ end = strchr(ptr, ' ');
> ++ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
> ++
> ++ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
> ++ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
> ++ ptr = end + 1;
> ++
> ++ /* if append-rootblock property is set use it to append to command line */
> ++ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
> ++ if(rootblock != NULL) {
> ++ if(*dest != ' ') {
> ++ *dest = ' ';
> ++ dest++;
> ++ len++;
> ++ }
> ++ if (len + l + i <= COMMAND_LINE_SIZE) {
> ++ memcpy(dest, rootblock, l);
> ++ dest += l - 1;
> ++ memcpy(dest, ptr, i);
> ++ dest += i;
> ++ }
> ++ } else {
> ++ len = strlen(str);
> ++ if (len + 1 < COMMAND_LINE_SIZE) {
> ++ memcpy(dest, str, len);
> ++ dest += len;
> ++ }
> ++ }
> ++ return dest;
> ++}
> ++#endif
> ++
> + static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
> + {
> + char cmdline[COMMAND_LINE_SIZE];
> +@@ -86,12 +147,21 @@ static void merge_fdt_bootargs(void *fdt
> +
> + /* and append the ATAG_CMDLINE */
> + if (fdt_cmdline) {
> ++
> ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
> ++ //save original bootloader args
> ++ //and append ubi.mtd with root partition number to current cmdline
> ++ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
> ++ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
> ++
> ++#else
> + len = strlen(fdt_cmdline);
> + if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
> + *ptr++ = ' ';
> + memcpy(ptr, fdt_cmdline, len);
> + ptr += len;
> + }
> ++#endif
> + }
> + *ptr = '\0';
> +
> +@@ -148,7 +218,9 @@ int atags_to_fdt(void *atag_list, void *
> + else
> + setprop_string(fdt, "/chosen", "bootargs",
> + atag->u.cmdline.cmdline);
> +- } else if (atag->hdr.tag == ATAG_MEM) {
> ++ }
> ++#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
> ++ else if (atag->hdr.tag == ATAG_MEM) {
> + if (memcount >= sizeof(mem_reg_property)/4)
> + continue;
> + if (!atag->u.mem.size)
> +@@ -187,6 +259,10 @@ int atags_to_fdt(void *atag_list, void *
> + setprop(fdt, "/memory", "reg", mem_reg_property,
> + 4 * memcount * memsize);
> + }
> ++#else
> ++
> ++ }
> ++#endif
> +
> + return fdt_pack(fdt);
> + }
> +--- a/init/main.c
> ++++ b/init/main.c
> +@@ -102,6 +102,10 @@
> + #define CREATE_TRACE_POINTS
> + #include <trace/events/initcall.h>
> +
> ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
> ++#include <linux/of.h>
> ++#endif
> ++
> + static int kernel_init(void *);
> +
> + extern void init_IRQ(void);
> +@@ -592,6 +596,18 @@ asmlinkage __visible void __init start_k
> + page_alloc_init();
> +
> + pr_notice("Kernel command line: %s\n", boot_command_line);
> ++
> ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
> ++ //Show bootloader's original command line for reference
> ++ if(of_chosen) {
> ++ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
> ++ if(prop)
> ++ pr_notice("Bootloader command line (ignored): %s\n", prop);
> ++ else
> ++ pr_notice("Bootloader command line not present\n");
> ++ }
> ++#endif
> ++
> + /* parameters may set static keys */
> + jump_label_init();
> + parse_early_param();
> diff --git a/target/linux/mvebu/patches-4.19/100-find_active_root.patch b/target/linux/mvebu/patches-4.19/100-find_active_root.patch
> new file mode 100644
> index 0000000000..f52a5108b8
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/100-find_active_root.patch
> @@ -0,0 +1,60 @@
> +The WRT1900AC among other Linksys routers uses a dual-firmware layout.
> +Dynamically rename the active partition to "ubi".
> +
> +Signed-off-by: Imre Kaloz <kaloz at openwrt.org>
> +
> +--- a/drivers/mtd/ofpart.c
> ++++ b/drivers/mtd/ofpart.c
> +@@ -25,6 +25,8 @@ static bool node_has_compatible(struct d
> + return of_get_property(pp, "compatible", NULL);
> + }
> +
> ++static int mangled_rootblock;
> ++
> + static int parse_fixed_partitions(struct mtd_info *master,
> + const struct mtd_partition **pparts,
> + struct mtd_part_parser_data *data)
> +@@ -33,6 +35,7 @@ static int parse_fixed_partitions(struct
> + struct device_node *mtd_node;
> + struct device_node *ofpart_node;
> + const char *partname;
> ++ const char *owrtpart = "ubi";
> + struct device_node *pp;
> + int nr_parts, i, ret = 0;
> + bool dedicated = true;
> +@@ -110,9 +113,13 @@ static int parse_fixed_partitions(struct
> + parts[i].size = of_read_number(reg + a_cells, s_cells);
> + parts[i].of_node = pp;
> +
> +- partname = of_get_property(pp, "label", &len);
> +- if (!partname)
> +- partname = of_get_property(pp, "name", &len);
> ++ if (mangled_rootblock && (i == mangled_rootblock)) {
> ++ partname = owrtpart;
> ++ } else {
> ++ partname = of_get_property(pp, "label", &len);
> ++ if (!partname)
> ++ partname = of_get_property(pp, "name", &len);
> ++ }
> + parts[i].name = partname;
> +
> + if (of_get_property(pp, "read-only", &len))
> +@@ -219,6 +226,18 @@ static int __init ofpart_parser_init(voi
> + return 0;
> + }
> +
> ++static int __init active_root(char *str)
> ++{
> ++ get_option(&str, &mangled_rootblock);
> ++
> ++ if (!mangled_rootblock)
> ++ return 1;
> ++
> ++ return 1;
> ++}
> ++
> ++__setup("mangled_rootblock=", active_root);
> ++
> + static void __exit ofpart_parser_exit(void)
> + {
> + deregister_mtd_parser(&ofpart_parser);
> diff --git a/target/linux/mvebu/patches-4.19/102-revert_i2c_delay.patch b/target/linux/mvebu/patches-4.19/102-revert_i2c_delay.patch
> new file mode 100644
> index 0000000000..930c0f9494
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/102-revert_i2c_delay.patch
> @@ -0,0 +1,15 @@
> +--- a/arch/arm/boot/dts/armada-xp.dtsi
> ++++ b/arch/arm/boot/dts/armada-xp.dtsi
> +@@ -237,12 +237,10 @@
> + };
> +
> + &i2c0 {
> +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> + reg = <0x11000 0x100>;
> + };
> +
> + &i2c1 {
> +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> + reg = <0x11100 0x100>;
> + };
> +
> diff --git a/target/linux/mvebu/patches-4.19/205-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-4.19/205-armada-385-rd-mtd-partitions.patch
> new file mode 100644
> index 0000000000..31bd53b1f3
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/205-armada-385-rd-mtd-partitions.patch
> @@ -0,0 +1,19 @@
> +--- a/arch/arm/boot/dts/armada-388-rd.dts
> ++++ b/arch/arm/boot/dts/armada-388-rd.dts
> +@@ -103,6 +103,16 @@
> + compatible = "st,m25p128", "jedec,spi-nor";
> + reg = <0>; /* Chip select 0 */
> + spi-max-frequency = <108000000>;
> ++
> ++ partition at 0 {
> ++ label = "uboot";
> ++ reg = <0 0x400000>;
> ++ };
> ++
> ++ partition at 1 {
> ++ label = "firmware";
> ++ reg = <0x400000 0xc00000>;
> ++ };
> + };
> + };
> +
> diff --git a/target/linux/mvebu/patches-4.19/206-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-4.19/206-ARM-mvebu-385-ap-Add-partitions.patch
> new file mode 100644
> index 0000000000..2057e31c7e
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/206-ARM-mvebu-385-ap-Add-partitions.patch
> @@ -0,0 +1,35 @@
> +From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
> +From: Maxime Ripard <maxime.ripard at free-electrons.com>
> +Date: Tue, 13 Jan 2015 11:14:09 +0100
> +Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
> +
> +Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> +---
> + arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
> + 1 file changed, 15 insertions(+)
> +
> +--- a/arch/arm/boot/dts/armada-385-db-ap.dts
> ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts
> +@@ -218,19 +218,19 @@
> + #size-cells = <1>;
> +
> + partition at 0 {
> +- label = "U-Boot";
> ++ label = "u-boot";
> + reg = <0x00000000 0x00800000>;
> + read-only;
> + };
> +
> + partition at 800000 {
> +- label = "uImage";
> ++ label = "kernel";
> + reg = <0x00800000 0x00400000>;
> + read-only;
> + };
> +
> + partition at c00000 {
> +- label = "Root";
> ++ label = "ubi";
> + reg = <0x00c00000 0x3f400000>;
> + };
> + };
> diff --git a/target/linux/mvebu/patches-4.19/210-clearfog_switch_node.patch b/target/linux/mvebu/patches-4.19/210-clearfog_switch_node.patch
> new file mode 100644
> index 0000000000..f9677a82f2
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/210-clearfog_switch_node.patch
> @@ -0,0 +1,21 @@
> +--- a/arch/arm/boot/dts/armada-388-clearfog.dts
> ++++ b/arch/arm/boot/dts/armada-388-clearfog.dts
> +@@ -88,6 +88,18 @@
> + };
> + };
> +
> ++ mvsw61xx {
> ++ #address-cells = <1>;
> ++ #size-cells = <0>;
> ++ compatible = "marvell,88e6176";
> ++ status = "okay";
> ++ reg = <0x4>;
> ++ is-indirect;
> ++
> ++ mii-bus = <&mdio>;
> ++ cpu-port-0 = <5>;
> ++ };
> ++
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-0 = <&rear_button_pins>;
> diff --git a/target/linux/mvebu/patches-4.19/220-disable-untested-dsa-boards.patch b/target/linux/mvebu/patches-4.19/220-disable-untested-dsa-boards.patch
> new file mode 100644
> index 0000000000..9cc7a113f6
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/220-disable-untested-dsa-boards.patch
> @@ -0,0 +1,30 @@
> +--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
> ++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
> +@@ -171,6 +171,7 @@
> + status = "okay";
> +
> + switch at 0 {
> ++ status = "disabled";
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +--- a/arch/arm/boot/dts/armada-388-clearfog.dts
> ++++ b/arch/arm/boot/dts/armada-388-clearfog.dts
> +@@ -161,6 +161,7 @@
> + status = "okay";
> +
> + switch at 4 {
> ++ status = "disabled";
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> +@@ -413,6 +413,7 @@
> + status = "okay";
> +
> + switch at 0 {
> ++ status = "disabled";
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> diff --git a/target/linux/mvebu/patches-4.19/230-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-4.19/230-armada-xp-linksys-mamba-broken-idle.patch
> new file mode 100644
> index 0000000000..935c8fe093
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/230-armada-xp-linksys-mamba-broken-idle.patch
> @@ -0,0 +1,10 @@
> +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> +@@ -543,3 +543,7 @@
> + };
> + };
> + };
> ++
> ++&coherencyfab {
> ++ broken-idle;
> ++};
> diff --git a/target/linux/mvebu/patches-4.19/300-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-4.19/300-mvneta-tx-queue-workaround.patch
> new file mode 100644
> index 0000000000..c27b5d9478
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/300-mvneta-tx-queue-workaround.patch
> @@ -0,0 +1,35 @@
> +The hardware queue scheduling is apparently configured with fixed
> +priorities, which creates a nasty fairness issue where traffic from one
> +CPU can starve traffic from all other CPUs.
> +
> +Work around this issue by forcing all tx packets to go through one CPU,
> +until this issue is fixed properly.
> +
> +Signed-off-by: Felix Fietkau <nbd at nbd.name>
> +---
> +--- a/drivers/net/ethernet/marvell/mvneta.c
> ++++ b/drivers/net/ethernet/marvell/mvneta.c
> +@@ -4257,6 +4257,15 @@ static int mvneta_ethtool_set_eee(struct
> + return phylink_ethtool_set_eee(pp->phylink, eee);
> + }
> +
> ++static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
> ++ struct net_device *sb_dev,
> ++ select_queue_fallback_t fallback)
> ++{
> ++ /* XXX: hardware queue scheduling is broken,
> ++ * use only one queue until it is fixed */
> ++ return 0;
> ++}
> ++
> + static const struct net_device_ops mvneta_netdev_ops = {
> + .ndo_open = mvneta_open,
> + .ndo_stop = mvneta_stop,
> +@@ -4267,6 +4276,7 @@ static const struct net_device_ops mvnet
> + .ndo_fix_features = mvneta_fix_features,
> + .ndo_get_stats64 = mvneta_get_stats64,
> + .ndo_do_ioctl = mvneta_ioctl,
> ++ .ndo_select_queue = mvneta_select_queue,
> + };
> +
> + static const struct ethtool_ops mvneta_eth_tool_ops = {
> diff --git a/target/linux/mvebu/patches-4.19/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-4.19/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
> new file mode 100644
> index 0000000000..29f36be460
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
> @@ -0,0 +1,40 @@
> +From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at arm.linux.org.uk>
> +Date: Sat, 3 Oct 2015 09:13:05 +0100
> +Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
> +
> +The cpuidle ->enter method expects the return value to be the sleep
> +state we entered. Returning negative numbers or other codes is not
> +permissible since coupled CPU idle was merged.
> +
> +At least some of the mvebu_v7_cpu_suspend() implementations return the
> +value from cpu_suspend(), which returns zero if the CPU vectors back
> +into the kernel via cpu_resume() (the success case), or the non-zero
> +return value of the suspend actor, or one (failure cases).
> +
> +We do not want to be returning the failure case value back to CPU idle
> +as that indicates that we successfully entered one of the deeper idle
> +states. Always return zero instead, indicating that we slept for the
> +shortest amount of time.
> +
> +Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> +---
> + drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
> + 1 file changed, 5 insertions(+), 1 deletion(-)
> +
> +--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
> ++++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
> +@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
> + ret = mvebu_v7_cpu_suspend(deepidle);
> + cpu_pm_exit();
> +
> ++ /*
> ++ * If we failed to enter the desired state, indicate that we
> ++ * slept lightly.
> ++ */
> + if (ret)
> +- return ret;
> ++ return 0;
> +
> + return index;
> + }
> diff --git a/target/linux/mvebu/patches-4.19/401-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-4.19/401-pci-mvebu-time-out-reset-on-link-up.patch
> new file mode 100644
> index 0000000000..2bbb647153
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/401-pci-mvebu-time-out-reset-on-link-up.patch
> @@ -0,0 +1,60 @@
> +From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Sat, 9 Jul 2016 10:58:16 +0100
> +Subject: pci: mvebu: time out reset on link up
> +
> +If the port reports that the link is up while we are resetting, there's
> +little point in waiting for the full duration.
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
> + 1 file changed, 14 insertions(+), 6 deletions(-)
> +
> +--- a/drivers/pci/controller/pci-mvebu.c
> ++++ b/drivers/pci/controller/pci-mvebu.c
> +@@ -1112,6 +1112,7 @@ static int mvebu_pcie_powerup(struct mve
> +
> + if (port->reset_gpio) {
> + u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
> ++ unsigned int i;
> +
> + of_property_read_u32(port->dn, "reset-delay-us",
> + &reset_udelay);
> +@@ -1119,7 +1120,13 @@ static int mvebu_pcie_powerup(struct mve
> + udelay(100);
> +
> + gpiod_set_value_cansleep(port->reset_gpio, 0);
> +- msleep(reset_udelay / 1000);
> ++ for (i = 0; i < reset_udelay; i += 1000) {
> ++ if (mvebu_pcie_link_up(port))
> ++ break;
> ++ msleep(1);
> ++ }
> ++
> ++ printk("%s: reset completed in %dus\n", port->name, i);
> + }
> +
> + return 0;
> +@@ -1283,15 +1290,16 @@ static int mvebu_pcie_probe(struct platf
> + if (!child)
> + continue;
> +
> +- ret = mvebu_pcie_powerup(port);
> +- if (ret < 0)
> +- continue;
> +-
> + port->base = mvebu_pcie_map_registers(pdev, child, port);
> + if (IS_ERR(port->base)) {
> + dev_err(dev, "%s: cannot map registers\n", port->name);
> + port->base = NULL;
> +- mvebu_pcie_powerdown(port);
> ++ continue;
> ++ }
> ++
> ++ ret = mvebu_pcie_powerup(port);
> ++ if (ret < 0) {
> ++ port->base = NULL;
> + continue;
> + }
> +
> diff --git a/target/linux/mvebu/patches-4.19/402-net-phylink-only-call-mac_config-during-resolve-when.patch b/target/linux/mvebu/patches-4.19/402-net-phylink-only-call-mac_config-during-resolve-when.patch
> new file mode 100644
> index 0000000000..0dc2605077
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/402-net-phylink-only-call-mac_config-during-resolve-when.patch
> @@ -0,0 +1,44 @@
> +From 6f3ea4e5b1f0867ec217f6101fcb89783ed905d7 Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Sat, 9 Feb 2019 18:23:26 +0000
> +Subject: [PATCH] net: phylink: only call mac_config() during resolve
> + when link is up
> +
> +There's little point calling mac_config() when the link is down.
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + drivers/net/phy/phylink.c | 11 +++++++++--
> + 1 file changed, 9 insertions(+), 2 deletions(-)
> +
> +--- a/drivers/net/phy/phylink.c
> ++++ b/drivers/net/phy/phylink.c
> +@@ -333,6 +333,13 @@ static void phylink_mac_config(struct ph
> + pl->ops->mac_config(pl->netdev, pl->link_an_mode, state);
> + }
> +
> ++static void phylink_mac_config_up(struct phylink *pl,
> ++ const struct phylink_link_state *state)
> ++{
> ++ if (state->link)
> ++ phylink_mac_config(pl, state);
> ++}
> ++
> + static void phylink_mac_an_restart(struct phylink *pl)
> + {
> + if (pl->link_config.an_enabled &&
> +@@ -436,12 +443,12 @@ static void phylink_resolve(struct work_
> + case MLO_AN_PHY:
> + link_state = pl->phy_state;
> + phylink_resolve_flow(pl, &link_state);
> +- phylink_mac_config(pl, &link_state);
> ++ phylink_mac_config_up(pl, &link_state);
> + break;
> +
> + case MLO_AN_FIXED:
> + phylink_get_fixed_state(pl, &link_state);
> +- phylink_mac_config(pl, &link_state);
> ++ phylink_mac_config_up(pl, &link_state);
> + break;
> +
> + case MLO_AN_INBAND:
> diff --git a/target/linux/mvebu/patches-4.19/403-net-phylink-ensure-inband-AN-works-correctly.patch b/target/linux/mvebu/patches-4.19/403-net-phylink-ensure-inband-AN-works-correctly.patch
> new file mode 100644
> index 0000000000..63f2113100
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/403-net-phylink-ensure-inband-AN-works-correctly.patch
> @@ -0,0 +1,59 @@
> +From 72f973f292b3eaaf451ebcd3253900d41f4ef24a Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Fri, 25 Jan 2019 17:42:51 +0000
> +Subject: [PATCH] net: phylink: ensure inband AN works correctly
> +
> +Do not update the link interface mode while the link is down to avoid
> +spurious link interface changes.
> +
> +Always call mac_config if we have a PHY to propagate the pause mode
> +settings to the MAC.
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + drivers/net/phy/phylink.c | 37 +++++++++++++++----------------------
> + 1 file changed, 15 insertions(+), 22 deletions(-)
> +
> +--- a/drivers/net/phy/phylink.c
> ++++ b/drivers/net/phy/phylink.c
> +@@ -453,28 +453,21 @@ static void phylink_resolve(struct work_
> +
> + case MLO_AN_INBAND:
> + phylink_get_mac_state(pl, &link_state);
> +- if (pl->phydev) {
> +- bool changed = false;
> +
> +- link_state.link = link_state.link &&
> +- pl->phy_state.link;
> ++ /* If we have a phy, the "up" state is the union of
> ++ * both the PHY and the MAC */
> ++ if (pl->phydev)
> ++ link_state.link &= pl->phy_state.link;
> +
> +- if (pl->phy_state.interface !=
> +- link_state.interface) {
> +- link_state.interface = pl->phy_state.interface;
> +- changed = true;
> +- }
> ++ /* Only update if the PHY link is up */
> ++ if (pl->phydev && pl->phy_state.link) {
> ++ link_state.interface = pl->phy_state.interface;
> +
> +- /* Propagate the flow control from the PHY
> +- * to the MAC. Also propagate the interface
> +- * if changed.
> +- */
> +- if (pl->phy_state.link || changed) {
> +- link_state.pause |= pl->phy_state.pause;
> +- phylink_resolve_flow(pl, &link_state);
> +-
> +- phylink_mac_config(pl, &link_state);
> +- }
> ++ /* If we have a PHY, we need to update with
> ++ * the pause mode bits. */
> ++ link_state.pause |= pl->phy_state.pause;
> ++ phylink_resolve_flow(pl, &link_state);
> ++ phylink_mac_config(pl, &link_state);
> + }
> + break;
> + }
> diff --git a/target/linux/mvebu/patches-4.19/404-sfp-provide-netdev-sfp_bus-and-use-for-start-stop.patch b/target/linux/mvebu/patches-4.19/404-sfp-provide-netdev-sfp_bus-and-use-for-start-stop.patch
> new file mode 100644
> index 0000000000..bd8f64dcbe
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/404-sfp-provide-netdev-sfp_bus-and-use-for-start-stop.patch
> @@ -0,0 +1,39 @@
> +From 0068a89747e7c1d9a0bbb7282a34382a4274638a Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Fri, 14 Apr 2017 16:41:55 +0100
> +Subject: [PATCH] sfp: provide netdev sfp_bus and use for start/stop
> +
> +Add a netdev sfp_bus pointer for propagating the phylink start/stop
> +actions to the SFP cage: the SFP cage may not be directly connected to
> +phylink, but may be the other side of a fixed PHY, and SFP needs to
> +know when the netdev is brought up or taken down.
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + drivers/net/phy/phylink.c | 8 ++++----
> + 1 file changed, 4 insertions(+), 4 deletions(-)
> +
> +--- a/drivers/net/phy/phylink.c
> ++++ b/drivers/net/phy/phylink.c
> +@@ -943,8 +943,8 @@ void phylink_start(struct phylink *pl)
> +
> + if (pl->link_an_mode == MLO_AN_FIXED && !IS_ERR(pl->link_gpio))
> + mod_timer(&pl->link_poll, jiffies + HZ);
> +- if (pl->sfp_bus)
> +- sfp_upstream_start(pl->sfp_bus);
> ++ if (pl->netdev->sfp_bus)
> ++ sfp_upstream_start(pl->netdev->sfp_bus);
> + if (pl->phydev)
> + phy_start(pl->phydev);
> + }
> +@@ -965,8 +965,8 @@ void phylink_stop(struct phylink *pl)
> +
> + if (pl->phydev)
> + phy_stop(pl->phydev);
> +- if (pl->sfp_bus)
> +- sfp_upstream_stop(pl->sfp_bus);
> ++ if (pl->netdev->sfp_bus)
> ++ sfp_upstream_stop(pl->netdev->sfp_bus);
> + if (pl->link_an_mode == MLO_AN_FIXED && !IS_ERR(pl->link_gpio))
> + del_timer_sync(&pl->link_poll);
> +
> diff --git a/target/linux/mvebu/patches-4.19/405-net-phy-marvell10g-add-SFP-support.patch b/target/linux/mvebu/patches-4.19/405-net-phy-marvell10g-add-SFP-support.patch
> new file mode 100644
> index 0000000000..9624b6cd81
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/405-net-phy-marvell10g-add-SFP-support.patch
> @@ -0,0 +1,155 @@
> +From 5f3ac54810055fec0cc667bb04c16f783830abff Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Fri, 14 Apr 2017 14:21:25 +0100
> +Subject: [PATCH] net: phy: marvell10g: add SFP+ support
> +
> +Add support for SFP+ cages to the Marvell 10G PHY driver. This is
> +slightly complicated by the way phylib works in that we need to use
> +a multi-step process to attach the SFP bus, and we also need to track
> +the phylink state machine to know when the module's transmit disable
> +signal should change state.
> +
> +With appropriate DT changes, this allows the SFP+ canges on the
> +Macchiatobin platform to be functional.
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + drivers/net/phy/marvell10g.c | 80 ++++++++++++++++++++++++++++++++++++
> + 1 file changed, 80 insertions(+)
> +
> +--- a/drivers/net/phy/marvell10g.c
> ++++ b/drivers/net/phy/marvell10g.c
> +@@ -25,6 +25,8 @@
> + #include <linux/hwmon.h>
> + #include <linux/marvell_phy.h>
> + #include <linux/phy.h>
> ++#include <linux/property.h>
> ++#include <linux/sfp.h>
> +
> + enum {
> + MV_PMA_BOOT = 0xc050,
> +@@ -56,6 +58,11 @@ enum {
> + };
> +
> + struct mv3310_priv {
> ++ struct fwnode_handle *sfp_fwnode;
> ++ struct sfp_bus *sfp_bus;
> ++ enum phy_state state;
> ++ bool running;
> ++
> + struct device *hwmon_dev;
> + char *hwmon_name;
> + };
> +@@ -219,6 +226,27 @@ static int mv3310_hwmon_probe(struct phy
> + }
> + #endif
> +
> ++static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
> ++{
> ++ struct phy_device *phydev = upstream;
> ++ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
> ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
> ++ phy_interface_t iface;
> ++
> ++ sfp_parse_support(priv->sfp_bus, id, support);
> ++ iface = sfp_select_interface(priv->sfp_bus, id, support);
> ++
> ++ if (iface != PHY_INTERFACE_MODE_10GKR) {
> ++ dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
> ++ return -EINVAL;
> ++ }
> ++ return 0;
> ++}
> ++
> ++static const struct sfp_upstream_ops mv3310_sfp_ops = {
> ++ .module_insert = mv3310_sfp_insert,
> ++};
> ++
> + static int mv3310_probe(struct phy_device *phydev)
> + {
> + struct mv3310_priv *priv;
> +@@ -249,9 +277,30 @@ static int mv3310_probe(struct phy_devic
> + if (ret)
> + return ret;
> +
> ++ if (phydev->mdio.dev.fwnode) {
> ++ struct fwnode_reference_args ref;
> ++ int ret;
> ++
> ++ ret = fwnode_property_get_reference_args(phydev->mdio.dev.fwnode,
> ++ "sfp", NULL, 0, 0,
> ++ &ref);
> ++ if (ret == 0)
> ++ priv->sfp_fwnode = ref.fwnode;
> ++ }
> ++
> + return 0;
> + }
> +
> ++static void mv3310_remove(struct phy_device *phydev)
> ++{
> ++ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
> ++
> ++ if (priv->sfp_bus)
> ++ sfp_unregister_upstream(priv->sfp_bus);
> ++
> ++ fwnode_handle_put(priv->sfp_fwnode);
> ++}
> ++
> + static int mv3310_suspend(struct phy_device *phydev)
> + {
> + return 0;
> +@@ -262,8 +311,29 @@ static int mv3310_resume(struct phy_devi
> + return mv3310_hwmon_config(phydev, true);
> + }
> +
> ++static void mv3310_link_change_notify(struct phy_device *phydev)
> ++{
> ++ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
> ++ enum phy_state state = phydev->state;
> ++ bool running;
> ++
> ++ if (priv->sfp_bus && priv->state != state) {
> ++ priv->state = state;
> ++
> ++ running = state >= PHY_UP && state < PHY_HALTED;
> ++ if (priv->running != running) {
> ++ priv->running = running;
> ++ if (running)
> ++ sfp_upstream_start(priv->sfp_bus);
> ++ else
> ++ sfp_upstream_stop(priv->sfp_bus);
> ++ }
> ++ }
> ++}
> ++
> + static int mv3310_config_init(struct phy_device *phydev)
> + {
> ++ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
> + __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
> + u32 mask;
> + int val;
> +@@ -357,6 +427,14 @@ static int mv3310_config_init(struct phy
> + phydev->supported &= mask;
> + phydev->advertising &= phydev->supported;
> +
> ++ /* Would be nice to do this in the probe function, but unfortunately,
> ++ * phylib doesn't have phydev->attached_dev set there.
> ++ */
> ++ if (priv->sfp_fwnode && !priv->sfp_bus)
> ++ priv->sfp_bus = sfp_register_upstream(priv->sfp_fwnode,
> ++ phydev->attached_dev,
> ++ phydev, &mv3310_sfp_ops);
> ++
> + return 0;
> + }
> +
> +@@ -566,6 +644,8 @@ static struct phy_driver mv3310_drivers[
> + .config_aneg = mv3310_config_aneg,
> + .aneg_done = mv3310_aneg_done,
> + .read_status = mv3310_read_status,
> ++ .remove = mv3310_remove,
> ++ .link_change_notify = mv3310_link_change_notify,
> + },
> + };
> +
> diff --git a/target/linux/mvebu/patches-4.19/406-sfp-add-sfp-compatible.patch b/target/linux/mvebu/patches-4.19/406-sfp-add-sfp-compatible.patch
> new file mode 100644
> index 0000000000..f800e0a49c
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/406-sfp-add-sfp-compatible.patch
> @@ -0,0 +1,24 @@
> +From 7e8bf5227f87601d8d74948bcae8846d2bdd6995 Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Fri, 14 Apr 2017 20:17:13 +0100
> +Subject: [PATCH] sfp: add sfp+ compatible
> +
> +Add a compatible for SFP+ cages. SFP+ cages are backwards compatible,
> +but the ethernet device behind them may not support the slower speeds
> +of SFP modules.
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + drivers/net/phy/sfp.c | 1 +
> + 1 file changed, 1 insertion(+)
> +
> +--- a/drivers/net/phy/sfp.c
> ++++ b/drivers/net/phy/sfp.c
> +@@ -229,6 +229,7 @@ static const struct sff_data sfp_data =
> + static const struct of_device_id sfp_of_match[] = {
> + { .compatible = "sff,sff", .data = &sff_data, },
> + { .compatible = "sff,sfp", .data = &sfp_data, },
> ++ { .compatible = "sff,sfp+", .data = &sfp_data, },
> + { },
> + };
> + MODULE_DEVICE_TABLE(of, sfp_of_match);
> diff --git a/target/linux/mvebu/patches-4.19/407-sfp-display-SFP-module-information.patch b/target/linux/mvebu/patches-4.19/407-sfp-display-SFP-module-information.patch
> new file mode 100644
> index 0000000000..d1106d938c
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/407-sfp-display-SFP-module-information.patch
> @@ -0,0 +1,297 @@
> +From 4ce55fb01c473bf1ad2048f8b4db62dca392e6d2 Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at arm.linux.org.uk>
> +Date: Sun, 13 Sep 2015 01:06:31 +0100
> +Subject: [PATCH] sfp: display SFP module information
> +
> +Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> +---
> + drivers/net/phy/sfp.c | 261 +++++++++++++++++++++++++++++++++++++++++-
> + 1 file changed, 258 insertions(+), 3 deletions(-)
> +
> +--- a/drivers/net/phy/sfp.c
> ++++ b/drivers/net/phy/sfp.c
> +@@ -1115,6 +1115,184 @@ static void sfp_hwmon_remove(struct sfp
> + }
> + #endif
> +
> ++static const char *sfp_link_len(char *buf, size_t size, unsigned int length,
> ++ unsigned int multiplier)
> ++{
> ++ if (length == 0)
> ++ return "unsupported/unspecified";
> ++
> ++ if (length == 255) {
> ++ *buf++ = '>';
> ++ size -= 1;
> ++ length -= 1;
> ++ }
> ++
> ++ length *= multiplier;
> ++
> ++ if (length >= 1000)
> ++ snprintf(buf, size, "%u.%0*ukm",
> ++ length / 1000,
> ++ multiplier > 100 ? 1 :
> ++ multiplier > 10 ? 2 : 3,
> ++ length % 1000);
> ++ else
> ++ snprintf(buf, size, "%um", length);
> ++
> ++ return buf;
> ++}
> ++
> ++struct bitfield {
> ++ unsigned int mask;
> ++ unsigned int val;
> ++ const char *str;
> ++};
> ++
> ++static const struct bitfield sfp_options[] = {
> ++ {
> ++ .mask = SFP_OPTIONS_HIGH_POWER_LEVEL,
> ++ .val = SFP_OPTIONS_HIGH_POWER_LEVEL,
> ++ .str = "hpl",
> ++ }, {
> ++ .mask = SFP_OPTIONS_PAGING_A2,
> ++ .val = SFP_OPTIONS_PAGING_A2,
> ++ .str = "paginga2",
> ++ }, {
> ++ .mask = SFP_OPTIONS_RETIMER,
> ++ .val = SFP_OPTIONS_RETIMER,
> ++ .str = "retimer",
> ++ }, {
> ++ .mask = SFP_OPTIONS_COOLED_XCVR,
> ++ .val = SFP_OPTIONS_COOLED_XCVR,
> ++ .str = "cooled",
> ++ }, {
> ++ .mask = SFP_OPTIONS_POWER_DECL,
> ++ .val = SFP_OPTIONS_POWER_DECL,
> ++ .str = "powerdecl",
> ++ }, {
> ++ .mask = SFP_OPTIONS_RX_LINEAR_OUT,
> ++ .val = SFP_OPTIONS_RX_LINEAR_OUT,
> ++ .str = "rxlinear",
> ++ }, {
> ++ .mask = SFP_OPTIONS_RX_DECISION_THRESH,
> ++ .val = SFP_OPTIONS_RX_DECISION_THRESH,
> ++ .str = "rxthresh",
> ++ }, {
> ++ .mask = SFP_OPTIONS_TUNABLE_TX,
> ++ .val = SFP_OPTIONS_TUNABLE_TX,
> ++ .str = "tunabletx",
> ++ }, {
> ++ .mask = SFP_OPTIONS_RATE_SELECT,
> ++ .val = SFP_OPTIONS_RATE_SELECT,
> ++ .str = "ratesel",
> ++ }, {
> ++ .mask = SFP_OPTIONS_TX_DISABLE,
> ++ .val = SFP_OPTIONS_TX_DISABLE,
> ++ .str = "txdisable",
> ++ }, {
> ++ .mask = SFP_OPTIONS_TX_FAULT,
> ++ .val = SFP_OPTIONS_TX_FAULT,
> ++ .str = "txfault",
> ++ }, {
> ++ .mask = SFP_OPTIONS_LOS_INVERTED,
> ++ .val = SFP_OPTIONS_LOS_INVERTED,
> ++ .str = "los-",
> ++ }, {
> ++ .mask = SFP_OPTIONS_LOS_NORMAL,
> ++ .val = SFP_OPTIONS_LOS_NORMAL,
> ++ .str = "los+",
> ++ }, { }
> ++};
> ++
> ++static const struct bitfield diagmon[] = {
> ++ {
> ++ .mask = SFP_DIAGMON_DDM,
> ++ .val = SFP_DIAGMON_DDM,
> ++ .str = "ddm",
> ++ }, {
> ++ .mask = SFP_DIAGMON_INT_CAL,
> ++ .val = SFP_DIAGMON_INT_CAL,
> ++ .str = "intcal",
> ++ }, {
> ++ .mask = SFP_DIAGMON_EXT_CAL,
> ++ .val = SFP_DIAGMON_EXT_CAL,
> ++ .str = "extcal",
> ++ }, {
> ++ .mask = SFP_DIAGMON_RXPWR_AVG,
> ++ .val = SFP_DIAGMON_RXPWR_AVG,
> ++ .str = "rxpwravg",
> ++ }, { }
> ++};
> ++
> ++static const char *sfp_bitfield(char *out, size_t outsz, const struct bitfield *bits, unsigned int val)
> ++{
> ++ char *p = out;
> ++ int n;
> ++
> ++ *p = '\0';
> ++ while (bits->mask) {
> ++ if ((val & bits->mask) == bits->val) {
> ++ n = snprintf(p, outsz, "%s%s",
> ++ out != p ? ", " : "",
> ++ bits->str);
> ++ if (n == outsz)
> ++ break;
> ++ p += n;
> ++ outsz -= n;
> ++ }
> ++ bits++;
> ++ }
> ++
> ++ return out;
> ++}
> ++
> ++static const char *sfp_connector(unsigned int connector)
> ++{
> ++ switch (connector) {
> ++ case SFP_CONNECTOR_UNSPEC:
> ++ return "unknown/unspecified";
> ++ case SFP_CONNECTOR_SC:
> ++ return "SC";
> ++ case SFP_CONNECTOR_FIBERJACK:
> ++ return "Fiberjack";
> ++ case SFP_CONNECTOR_LC:
> ++ return "LC";
> ++ case SFP_CONNECTOR_MT_RJ:
> ++ return "MT-RJ";
> ++ case SFP_CONNECTOR_MU:
> ++ return "MU";
> ++ case SFP_CONNECTOR_SG:
> ++ return "SG";
> ++ case SFP_CONNECTOR_OPTICAL_PIGTAIL:
> ++ return "Optical pigtail";
> ++ case SFP_CONNECTOR_HSSDC_II:
> ++ return "HSSDC II";
> ++ case SFP_CONNECTOR_COPPER_PIGTAIL:
> ++ return "Copper pigtail";
> ++ default:
> ++ return "unknown";
> ++ }
> ++}
> ++
> ++static const char *sfp_encoding(unsigned int encoding)
> ++{
> ++ switch (encoding) {
> ++ case SFP_ENCODING_UNSPEC:
> ++ return "unspecified";
> ++ case SFP_ENCODING_8472_64B66B:
> ++ return "64b66b";
> ++ case SFP_ENCODING_8B10B:
> ++ return "8b10b";
> ++ case SFP_ENCODING_4B5B:
> ++ return "4b5b";
> ++ case SFP_ENCODING_NRZ:
> ++ return "NRZ";
> ++ case SFP_ENCODING_8472_MANCHESTER:
> ++ return "MANCHESTER";
> ++ default:
> ++ return "unknown";
> ++ }
> ++}
> ++
> + /* Helpers */
> + static void sfp_module_tx_disable(struct sfp *sfp)
> + {
> +@@ -1359,6 +1537,8 @@ static int sfp_sm_mod_probe(struct sfp *
> + {
> + /* SFP module inserted - read I2C data */
> + struct sfp_eeprom_id id;
> ++ char date[9];
> ++ char options[80];
> + bool cotsworks;
> + u8 check;
> + int ret;
> +@@ -1415,12 +1595,87 @@ static int sfp_sm_mod_probe(struct sfp *
> +
> + sfp->id = id;
> +
> +- dev_info(sfp->dev, "module %.*s %.*s rev %.*s sn %.*s dc %.*s\n",
> ++ date[0] = sfp->id.ext.datecode[4];
> ++ date[1] = sfp->id.ext.datecode[5];
> ++ date[2] = '-';
> ++ date[3] = sfp->id.ext.datecode[2];
> ++ date[4] = sfp->id.ext.datecode[3];
> ++ date[5] = '-';
> ++ date[6] = sfp->id.ext.datecode[0];
> ++ date[7] = sfp->id.ext.datecode[1];
> ++ date[8] = '\0';
> ++
> ++ dev_info(sfp->dev, "module %.*s %.*s rev %.*s sn %.*s dc %s\n",
> + (int)sizeof(id.base.vendor_name), id.base.vendor_name,
> + (int)sizeof(id.base.vendor_pn), id.base.vendor_pn,
> + (int)sizeof(id.base.vendor_rev), id.base.vendor_rev,
> +- (int)sizeof(id.ext.vendor_sn), id.ext.vendor_sn,
> +- (int)sizeof(id.ext.datecode), id.ext.datecode);
> ++ (int)sizeof(id.ext.vendor_sn), id.ext.vendor_sn, date);
> ++ dev_info(sfp->dev, " %s connector, encoding %s, nominal bitrate %u.%uGbps +%u%% -%u%%\n",
> ++ sfp_connector(sfp->id.base.connector),
> ++ sfp_encoding(sfp->id.base.encoding),
> ++ sfp->id.base.br_nominal / 10,
> ++ sfp->id.base.br_nominal % 10,
> ++ sfp->id.ext.br_max, sfp->id.ext.br_min);
> ++ dev_info(sfp->dev, " 1000BaseSX%c 1000BaseLX%c 1000BaseCX%c 1000BaseT%c 100BaseLX%c 100BaseFX%c BaseBX10%c BasePX%c\n",
> ++ sfp->id.base.e1000_base_sx ? '+' : '-',
> ++ sfp->id.base.e1000_base_lx ? '+' : '-',
> ++ sfp->id.base.e1000_base_cx ? '+' : '-',
> ++ sfp->id.base.e1000_base_t ? '+' : '-',
> ++ sfp->id.base.e100_base_lx ? '+' : '-',
> ++ sfp->id.base.e100_base_fx ? '+' : '-',
> ++ sfp->id.base.e_base_bx10 ? '+' : '-',
> ++ sfp->id.base.e_base_px ? '+' : '-');
> ++ dev_info(sfp->dev, " 10GBaseSR%c 10GBaseLR%c 10GBaseLRM%c 10GBaseER%c\n",
> ++ sfp->id.base.e10g_base_sr ? '+' : '-',
> ++ sfp->id.base.e10g_base_lr ? '+' : '-',
> ++ sfp->id.base.e10g_base_lrm ? '+' : '-',
> ++ sfp->id.base.e10g_base_er ? '+' : '-');
> ++
> ++ if (!sfp->id.base.sfp_ct_passive && !sfp->id.base.sfp_ct_active &&
> ++ !sfp->id.base.e1000_base_t) {
> ++ char len_9um[16], len_om[16];
> ++
> ++ dev_info(sfp->dev, " Wavelength %unm, fiber lengths:\n",
> ++ be16_to_cpup(&sfp->id.base.optical_wavelength));
> ++
> ++ if (sfp->id.base.link_len[0] == 255)
> ++ strcpy(len_9um, ">254km");
> ++ else if (sfp->id.base.link_len[1] && sfp->id.base.link_len[1] != 255)
> ++ sprintf(len_9um, "%um",
> ++ sfp->id.base.link_len[1] * 100);
> ++ else if (sfp->id.base.link_len[0])
> ++ sprintf(len_9um, "%ukm", sfp->id.base.link_len[0]);
> ++ else if (sfp->id.base.link_len[1] == 255)
> ++ strcpy(len_9um, ">25.4km");
> ++ else
> ++ strcpy(len_9um, "unsupported");
> ++
> ++ dev_info(sfp->dev, " 9µm SM : %s\n", len_9um);
> ++ dev_info(sfp->dev, " 62.5µm MM OM1: %s\n",
> ++ sfp_link_len(len_om, sizeof(len_om),
> ++ sfp->id.base.link_len[3], 10));
> ++ dev_info(sfp->dev, " 50µm MM OM2: %s\n",
> ++ sfp_link_len(len_om, sizeof(len_om),
> ++ sfp->id.base.link_len[2], 10));
> ++ dev_info(sfp->dev, " 50µm MM OM3: %s\n",
> ++ sfp_link_len(len_om, sizeof(len_om),
> ++ sfp->id.base.link_len[5], 10));
> ++ dev_info(sfp->dev, " 50µm MM OM4: %s\n",
> ++ sfp_link_len(len_om, sizeof(len_om),
> ++ sfp->id.base.link_len[4], 10));
> ++ } else {
> ++ char len[16];
> ++ dev_info(sfp->dev, " Copper length: %s\n",
> ++ sfp_link_len(len, sizeof(len),
> ++ sfp->id.base.link_len[4], 1));
> ++ }
> ++
> ++ dev_info(sfp->dev, " Options: %s\n",
> ++ sfp_bitfield(options, sizeof(options), sfp_options,
> ++ be16_to_cpu(sfp->id.ext.options)));
> ++ dev_info(sfp->dev, " Diagnostics: %s\n",
> ++ sfp_bitfield(options, sizeof(options), diagmon,
> ++ sfp->id.ext.diagmon));
> +
> + /* Check whether we support this module */
> + if (!sfp->type->module_supported(&sfp->id)) {
> diff --git a/target/linux/mvebu/patches-4.19/408-sfp-more-cotsworks-fixes.patch b/target/linux/mvebu/patches-4.19/408-sfp-more-cotsworks-fixes.patch
> new file mode 100644
> index 0000000000..c3887eadad
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/408-sfp-more-cotsworks-fixes.patch
> @@ -0,0 +1,44 @@
> +From e26af2726067ff260b77485df6af8375b82bfb1d Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Sat, 23 Dec 2017 12:22:58 +0000
> +Subject: [PATCH] sfp: more cotsworks fixes
> +
> +Cotsworks also gets the date code wrong.
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + drivers/net/phy/sfp.c | 15 ++++++++-------
> + 1 file changed, 8 insertions(+), 7 deletions(-)
> +
> +--- a/drivers/net/phy/sfp.c
> ++++ b/drivers/net/phy/sfp.c
> +@@ -1554,9 +1554,9 @@ static int sfp_sm_mod_probe(struct sfp *
> + return -EAGAIN;
> + }
> +
> +- /* Cotsworks do not seem to update the checksums when they
> +- * do the final programming with the final module part number,
> +- * serial number and date code.
> ++ /* Cotsworks do not seem to update the checksums when they update the
> ++ * module part number, serial number and date code. They also format
> ++ * the date code incorrectly.
> + */
> + cotsworks = !memcmp(id.base.vendor_name, "COTSWORKS ", 16);
> +
> +@@ -1595,11 +1595,12 @@ static int sfp_sm_mod_probe(struct sfp *
> +
> + sfp->id = id;
> +
> +- date[0] = sfp->id.ext.datecode[4];
> +- date[1] = sfp->id.ext.datecode[5];
> ++ /* Cotsworks also gets the date code wrong. */
> ++ date[0] = sfp->id.ext.datecode[4 - 2 * cotsworks];
> ++ date[1] = sfp->id.ext.datecode[5 - 2 * cotsworks];
> + date[2] = '-';
> +- date[3] = sfp->id.ext.datecode[2];
> +- date[4] = sfp->id.ext.datecode[3];
> ++ date[3] = sfp->id.ext.datecode[2 + 2 * cotsworks];
> ++ date[4] = sfp->id.ext.datecode[3 + 2 * cotsworks];
> + date[5] = '-';
> + date[6] = sfp->id.ext.datecode[0];
> + date[7] = sfp->id.ext.datecode[1];
> diff --git a/target/linux/mvebu/patches-4.19/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-4.19/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
> new file mode 100644
> index 0000000000..dd2bef7f63
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
> @@ -0,0 +1,87 @@
> +From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at armlinux.org.uk>
> +Date: Tue, 29 Nov 2016 10:15:45 +0000
> +Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
> +
> +Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
> +---
> + arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
> + .../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
> + 2 files changed, 63 insertions(+)
> + create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
> +
> +--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
> ++++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
> +@@ -7,6 +7,7 @@
> +
> + /dts-v1/;
> + #include "armada-388-clearfog.dtsi"
> ++#include "armada-38x-solidrun-microsom-emmc.dtsi"
> +
> + / {
> + model = "SolidRun Clearfog Base A1";
> +--- /dev/null
> ++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
> +@@ -0,0 +1,62 @@
> ++/*
> ++ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
> ++ *
> ++ * Copyright (C) 2015 Russell King
> ++ *
> ++ * This board is in development; the contents of this file work with
> ++ * the A1 rev 2.0 of the board, which does not represent final
> ++ * production board. Things will change, don't expect this file to
> ++ * remain compatible info the future.
> ++ *
> ++ * This file is dual-licensed: you can use it either under the terms
> ++ * of the GPL or the X11 license, at your option. Note that this dual
> ++ * licensing only applies to this file, and not this project as a
> ++ * whole.
> ++ *
> ++ * a) This file is free software; you can redistribute it and/or
> ++ * modify it under the terms of the GNU General Public License
> ++ * version 2 as published by the Free Software Foundation.
> ++ *
> ++ * This file is distributed in the hope that it will be useful
> ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> ++ * GNU General Public License for more details.
> ++ *
> ++ * Or, alternatively
> ++ *
> ++ * b) Permission is hereby granted, free of charge, to any person
> ++ * obtaining a copy of this software and associated documentation
> ++ * files (the "Software"), to deal in the Software without
> ++ * restriction, including without limitation the rights to use
> ++ * copy, modify, merge, publish, distribute, sublicense, and/or
> ++ * sell copies of the Software, and to permit persons to whom the
> ++ * Software is furnished to do so, subject to the following
> ++ * conditions:
> ++ *
> ++ * The above copyright notice and this permission notice shall be
> ++ * included in all copies or substantial portions of the Software.
> ++ *
> ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> ++ * OTHER DEALINGS IN THE SOFTWARE.
> ++ */
> ++/ {
> ++ soc {
> ++ internal-regs {
> ++ sdhci at d8000 {
> ++ bus-width = <4>;
> ++ no-1-8-v;
> ++ non-removable;
> ++ pinctrl-0 = <µsom_sdhci_pins>;
> ++ pinctrl-names = "default";
> ++ status = "okay";
> ++ wp-inverted;
> ++ };
> ++ };
> ++ };
> ++};
> diff --git a/target/linux/mvebu/patches-4.19/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch b/target/linux/mvebu/patches-4.19/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
> new file mode 100644
> index 0000000000..d64bd8084e
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
> @@ -0,0 +1,124 @@
> +From 09a0122c74ec076e08512f1b00b7ccb8a450282f Mon Sep 17 00:00:00 2001
> +From: Russell King <rmk+kernel at arm.linux.org.uk>
> +Date: Tue, 29 Nov 2016 10:15:43 +0000
> +Subject: ARM: dts: armada388-clearfog: document MPP usage
> +
> +Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> +---
> + arch/arm/boot/dts/armada-388-clearfog-base.dts | 51 ++++++++++++++++++++++++++
> + arch/arm/boot/dts/armada-388-clearfog.dts | 50 +++++++++++++++++++++++++
> + 2 files changed, 101 insertions(+)
> +
> +--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
> ++++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
> +@@ -67,3 +67,54 @@
> + marvell,function = "gpio";
> + };
> + };
> ++
> ++/*
> ++MPP
> ++18: pu gpio pca9655 int
> ++19: gpio phy reset
> ++20: pu gpio sd0 detect
> ++21: sd0:cmd
> ++22: pd gpio mikro int
> ++23:
> ++
> ++24: ua1:rxd mikro rx
> ++25: ua1:txd mikro tx
> ++26: pu i2c1:sck
> ++27: pu i2c1:sda
> ++28: sd0:clk
> ++29: pd gpio mikro rst
> ++30:
> ++31:
> ++
> ++32:
> ++33:
> ++34:
> ++35:
> ++36:
> ++37: sd0:d3
> ++38: sd0:d0
> ++39: sd0:d1
> ++
> ++40: sd0:d2
> ++41:
> ++42:
> ++43: spi1:cs2 mikro cs
> ++44: gpio rear button sw3
> ++45: ref:clk_out0 phy#0 clock
> ++46: ref:clk_out1 phy#1 clock
> ++47:
> ++
> ++48: gpio J18 spare gpio
> ++49: gpio U10 I2C_IRQ(GNSS)
> ++50: gpio board id?
> ++51:
> ++52:
> ++53:
> ++54: gpio mikro pwm
> ++55:
> ++
> ++56: pu spi1:mosi mikro mosi
> ++57: pd spi1:sck mikro sck
> ++58: spi1:miso mikro miso
> ++59:
> ++*/
> +--- a/arch/arm/boot/dts/armada-388-clearfog.dts
> ++++ b/arch/arm/boot/dts/armada-388-clearfog.dts
> +@@ -249,3 +249,53 @@
> + */
> + pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
> + };
> ++/*
> +++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
> ++MPP18: gpio ? (pca9655 int?)
> ++MPP19: gpio ? (clkreq?)
> ++MPP20: gpio ? (sd0 detect)
> ++MPP21: sd0:cmd x sd0
> ++MPP22: gpio x mikro int
> ++MPP23: gpio x switch irq
> +++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
> ++MPP24: ua1:rxd x mikro rx
> ++MPP25: ua1:txd x mikro tx
> ++MPP26: i2c1:sck x mikro sck
> ++MPP27: i2c1:sda x mikro sda
> ++MPP28: sd0:clk x sd0
> ++MPP29: gpio x mikro rst
> ++MPP30: ge1:txd2 ? (config)
> ++MPP31: ge1:txd3 ? (config)
> +++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
> ++MPP32: ge1:txctl ? (unused)
> ++MPP33: gpio ? (pic_com0)
> ++MPP34: gpio x rear button (pic_com1)
> ++MPP35: gpio ? (pic_com2)
> ++MPP36: gpio ? (unused)
> ++MPP37: sd0:d3 x sd0
> ++MPP38: sd0:d0 x sd0
> ++MPP39: sd0:d1 x sd0
> +++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
> ++MPP40: sd0:d2 x sd0
> ++MPP41: gpio x switch reset
> ++MPP42: gpio ? sw1-1
> ++MPP43: spi1:cs2 x mikro cs
> ++MPP44: sata3:prsnt ? (unused)
> ++MPP45: ref:clk_out0 ?
> ++MPP46: ref:clk_out1 x switch clk
> ++MPP47: 4 ? (unused)
> +++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
> ++MPP48: tdm:pclk
> ++MPP49: tdm:fsync
> ++MPP50: tdm:drx
> ++MPP51: tdm:dtx
> ++MPP52: tdm:int
> ++MPP53: tdm:rst
> ++MPP54: gpio ? (pwm)
> ++MPP55: spi1:cs1 x slic
> +++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
> ++MPP56: spi1:mosi x mikro mosi
> ++MPP57: spi1:sck x mikro sck
> ++MPP58: spi1:miso x mikro miso
> ++MPP59: spi1:cs0 x w25q32
> ++*/
> diff --git a/target/linux/mvebu/patches-4.19/450-reprobe_sfp_phy.patch b/target/linux/mvebu/patches-4.19/450-reprobe_sfp_phy.patch
> new file mode 100644
> index 0000000000..2c03b6a760
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/450-reprobe_sfp_phy.patch
> @@ -0,0 +1,94 @@
> +From 28baa5e2635285b178326b301f534ed95c65dd01 Mon Sep 17 00:00:00 2001
> +From: Jonas Gorski <jonas.gorski at gmail.com>
> +Date: Thu, 29 Sep 2016 11:44:39 +0200
> +Subject: [PATCH] sfp: retry phy probe if unsuccessful
> +
> +Some phys seem to take longer than 50 ms to come out of reset, so retry
> +until we find a phy.
> +
> +Signed-off-by: Jonas Gorski <jonas.gorski at gmail.com>
> +---
> + drivers/net/phy/sfp.c | 38 +++++++++++++++++++++++++-------------
> + 1 file changed, 25 insertions(+), 13 deletions(-)
> +
> +--- a/drivers/net/phy/sfp.c
> ++++ b/drivers/net/phy/sfp.c
> +@@ -1357,7 +1357,7 @@ static void sfp_sm_phy_detach(struct sfp
> + sfp->mod_phy = NULL;
> + }
> +
> +-static void sfp_sm_probe_phy(struct sfp *sfp)
> ++static int sfp_sm_probe_phy(struct sfp *sfp)
> + {
> + struct phy_device *phy;
> + int err;
> +@@ -1367,11 +1367,11 @@ static void sfp_sm_probe_phy(struct sfp
> + phy = mdiobus_scan(sfp->i2c_mii, SFP_PHY_ADDR);
> + if (phy == ERR_PTR(-ENODEV)) {
> + dev_info(sfp->dev, "no PHY detected\n");
> +- return;
> ++ return -EAGAIN;
> + }
> + if (IS_ERR(phy)) {
> + dev_err(sfp->dev, "mdiobus scan returned %ld\n", PTR_ERR(phy));
> +- return;
> ++ return PTR_ERR(phy);
> + }
> +
> + err = sfp_add_phy(sfp->sfp_bus, phy);
> +@@ -1379,11 +1379,13 @@ static void sfp_sm_probe_phy(struct sfp
> + phy_device_remove(phy);
> + phy_device_free(phy);
> + dev_err(sfp->dev, "sfp_add_phy failed: %d\n", err);
> +- return;
> ++ return err;
> + }
> +
> + sfp->mod_phy = phy;
> + phy_start(phy);
> ++
> ++ return 0;
> + }
> +
> + static void sfp_sm_link_up(struct sfp *sfp)
> +@@ -1447,14 +1449,9 @@ static void sfp_sm_fault(struct sfp *sfp
> +
> + static void sfp_sm_mod_init(struct sfp *sfp)
> + {
> +- sfp_module_tx_enable(sfp);
> ++ int ret = 0;
> +
> +- /* Wait t_init before indicating that the link is up, provided the
> +- * current state indicates no TX_FAULT. If TX_FAULT clears before
> +- * this time, that's fine too.
> +- */
> +- sfp_sm_next(sfp, SFP_S_INIT, T_INIT_JIFFIES);
> +- sfp->sm_retries = 5;
> ++ sfp_module_tx_enable(sfp);
> +
> + /* Setting the serdes link mode is guesswork: there's no
> + * field in the EEPROM which indicates what mode should
> +@@ -1468,7 +1465,22 @@ static void sfp_sm_mod_init(struct sfp *
> + if (sfp->id.base.e1000_base_t ||
> + sfp->id.base.e100_base_lx ||
> + sfp->id.base.e100_base_fx)
> +- sfp_sm_probe_phy(sfp);
> ++ ret = sfp_sm_probe_phy(sfp);
> ++
> ++ if (!ret) {
> ++ /* Wait t_init before indicating that the link is up, provided
> ++ * the current state indicates no TX_FAULT. If TX_FAULT clears
> ++ * this time, that's fine too.
> ++ */
> ++ sfp_sm_next(sfp, SFP_S_INIT, T_INIT_JIFFIES);
> ++ sfp->sm_retries = 5;
> ++ return;
> ++ }
> ++
> ++ if (ret == -EAGAIN)
> ++ sfp_sm_set_timer(sfp, T_PROBE_RETRY);
> ++ else
> ++ sfp_sm_next(sfp, SFP_S_TX_DISABLE, 0);
> + }
> +
> + static int sfp_sm_mod_hpower(struct sfp *sfp)
> diff --git a/target/linux/mvebu/patches-4.19/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch b/target/linux/mvebu/patches-4.19/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
> new file mode 100644
> index 0000000000..880b0d9241
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
> @@ -0,0 +1,40 @@
> +From eefe328439642101774f0f5c4ea0dc6ba1cfb687 Mon Sep 17 00:00:00 2001
> +From: Ding Tao <miyatsu at qq.com>
> +Date: Fri, 26 Oct 2018 11:50:27 +0000
> +Subject: [PATCH] arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl
> + definition
> +
> +Add emmc/sdio pinctrl definition for marvell armada37xx SoCs.
> +
> +Signed-off-by: Ding Tao <miyatsu at qq.com>
> +Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
> +---
> + arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 ++++++++++
> + 1 file changed, 10 insertions(+)
> +
> +--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> ++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +@@ -221,6 +221,11 @@
> + groups = "uart2";
> + function = "uart";
> + };
> ++
> ++ mmc_pins: mmc-pins {
> ++ groups = "emmc_nb";
> ++ function = "emmc";
> ++ };
> + };
> +
> + nb_pm: syscon at 14000 {
> +@@ -253,6 +258,11 @@
> + function = "mii";
> + };
> +
> ++ sdio_pins: sdio-pins {
> ++ groups = "sdio_sb";
> ++ function = "sdio";
> ++ };
> ++
> + };
> +
> + eth0: ethernet at 30000 {
> diff --git a/target/linux/mvebu/patches-4.19/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch b/target/linux/mvebu/patches-4.19/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
> new file mode 100644
> index 0000000000..77af3d1219
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
> @@ -0,0 +1,49 @@
> +From 43ebc7c1b3ed8198b9acf3019eca16e722f7331c Mon Sep 17 00:00:00 2001
> +From: Ding Tao <miyatsu at qq.com>
> +Date: Fri, 26 Oct 2018 11:50:28 +0000
> +Subject: [PATCH] arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
> +
> +The ESPRESSObin board has a emmc interface available on U11: declare it
> +and let the bootloader enable it if the emmc is present.
> +
> +[gregory.clement at bootlin.com: disable the emmc by default]
> +Signed-off-by: Ding Tao <miyatsu at qq.com>
> +Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
> +---
> + .../dts/marvell/armada-3720-espressobin.dts | 22 +++++++++++++++++++
> + 1 file changed, 22 insertions(+)
> +
> +--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> ++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> +@@ -60,9 +60,31 @@
> + cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
> + marvell,pad-type = "sd";
> + vqmmc-supply = <&vcc_sd_reg1>;
> ++
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&sdio_pins>;
> + status = "okay";
> + };
> +
> ++/* U11 */
> ++&sdhci0 {
> ++ non-removable;
> ++ bus-width = <8>;
> ++ mmc-ddr-1_8v;
> ++ mmc-hs400-1_8v;
> ++ marvell,xenon-emmc;
> ++ marvell,xenon-tun-count = <9>;
> ++ marvell,pad-type = "fixed-1-8v";
> ++
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&mmc_pins>;
> ++/*
> ++ * This eMMC is not populated on all boards, so disable it by
> ++ * default and let the bootloader enable it, if it is present
> ++ */
> ++ status = "disabled";
> ++};
> ++
> + &spi0 {
> + status = "okay";
> +
> diff --git a/target/linux/mvebu/patches-4.19/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch b/target/linux/mvebu/patches-4.19/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
> new file mode 100644
> index 0000000000..e989f59d5c
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
> @@ -0,0 +1,20 @@
> +From be893f672e340b56ca60f2f6c32fdd713a5852f5 Mon Sep 17 00:00:00 2001
> +From: Kevin Mihelich <kevin at archlinuxarm.org>
> +Date: Tue, 4 Jul 2017 19:25:28 -0600
> +Subject: arm64: dts: marvell: armada37xx: Add eth0 alias
> +
> +Signed-off-by: Kevin Mihelich <kevin at archlinuxarm.org>
> +---
> + arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
> + 1 file changed, 1 insertion(+)
> +
> +--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> ++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +@@ -18,6 +18,7 @@
> + #size-cells = <2>;
> +
> + aliases {
> ++ ethernet0 = ð0;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + };
> diff --git a/target/linux/mvebu/patches-4.19/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch b/target/linux/mvebu/patches-4.19/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
> new file mode 100644
> index 0000000000..0f39b2a3c2
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
> @@ -0,0 +1,58 @@
> +From 3217cdfe8a3eae76fafbebbe407be5985a7fd4c2 Mon Sep 17 00:00:00 2001
> +From: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +Date: Mon, 31 Dec 2018 14:18:50 +0100
> +Subject: [PATCH] arm64: dts: armada-3720-espressobin: correct spi node
> +
> +The manufacturer of this board, ships it with various SPI NOR chips and
> +increments U-Boot bootloader version along the time. There is no way to
> +tell which is placed on the board since no revision bump takes place.
> +This creates two issues.
> +
> +The first, cosmetic. Since the SPI chip may differ, there's message on
> +boot stating that kernel expected w25q32dw and found different one. To
> +correct this, remove optional device-specific compatible string. Being
> +here lets replace bogus "spi-flash" string with proper one.
> +
> +The second is linked to partitions layout, it changed after commit [1]
> +in Marvells downstream U-Boot fork, shifting environment location to the
> +end of boot device. Since the new boards can have U-Boot with this
> +change it can lead to improper results writing or reading from these
> +partitions. We can't tell if users will update bootloader to recent
> +version, so let's drop current layout.
> +
> +1. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/81e7251252aefe1a6b829ed05f3586320cb45372
> +
> +Signed-off-by: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +---
> + .../dts/marvell/armada-3720-espressobin.dts | 18 +-----------------
> + 1 file changed, 1 insertion(+), 17 deletions(-)
> +
> +--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> ++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> +@@ -90,25 +90,9 @@
> +
> + flash at 0 {
> + reg = <0>;
> +- compatible = "winbond,w25q32dw", "jedec,spi-flash";
> ++ compatible = "jedec,spi-nor";
> + spi-max-frequency = <104000000>;
> + m25p,fast-read;
> +-
> +- partitions {
> +- compatible = "fixed-partitions";
> +- #address-cells = <1>;
> +- #size-cells = <1>;
> +-
> +- partition at 0 {
> +- label = "uboot";
> +- reg = <0 0x180000>;
> +- };
> +-
> +- partition at 180000 {
> +- label = "ubootenv";
> +- reg = <0x180000 0x10000>;
> +- };
> +- };
> + };
> + };
> +
> diff --git a/target/linux/mvebu/patches-4.19/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch b/target/linux/mvebu/patches-4.19/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
> new file mode 100644
> index 0000000000..cea0d1db44
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
> @@ -0,0 +1,26 @@
> +From 6ea9a1ee9367fb35acff1c08a0dc4213ff4687a0 Mon Sep 17 00:00:00 2001
> +From: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +Date: Tue, 9 Apr 2019 15:53:42 +0200
> +Subject: [PATCH] arm64: dts: marvell: armada-3720-espressobin: add ports
> + phandle
> +
> +Instead of referencing the whole mdio node, add ports phandle to adjust
> +port labels in dts for different hardware iterations of ESPRESSObin
> +boards.
> +
> +Signed-off-by: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +---
> + arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 +-
> + 1 file changed, 1 insertion(+), 1 deletion(-)
> +
> +--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> ++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> +@@ -132,7 +132,7 @@
> +
> + dsa,member = <0 0>;
> +
> +- ports {
> ++ ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> diff --git a/target/linux/mvebu/patches-4.19/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch b/target/linux/mvebu/patches-4.19/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
> new file mode 100644
> index 0000000000..3fd561db3a
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
> @@ -0,0 +1,44 @@
> +From 5e79c0c381eb085a2aa2da175eedea1950f07520 Mon Sep 17 00:00:00 2001
> +From: Tomasz Maciej Nowak <tomek_n at o2.pl>
> +Date: Tue, 30 Apr 2019 15:37:34 +0200
> +Subject: [PATCH] Revert "PCI: aardvark: Convert to use pci_host_probe()"
> +
> +This reverts commit c8e144f8ab00e6c4a070a932ef9c57db09aa41cf.
> +---
> + drivers/pci/controller/pci-aardvark.c | 12 +++++++++++-
> + 1 file changed, 11 insertions(+), 1 deletion(-)
> +
> +--- a/drivers/pci/controller/pci-aardvark.c
> ++++ b/drivers/pci/controller/pci-aardvark.c
> +@@ -843,6 +843,7 @@ static int advk_pcie_probe(struct platfo
> + struct device *dev = &pdev->dev;
> + struct advk_pcie *pcie;
> + struct resource *res;
> ++ struct pci_bus *bus, *child;
> + struct pci_host_bridge *bridge;
> + int ret, irq;
> +
> +@@ -896,13 +897,22 @@ static int advk_pcie_probe(struct platfo
> + bridge->map_irq = of_irq_parse_and_map_pci;
> + bridge->swizzle_irq = pci_common_swizzle;
> +
> +- ret = pci_host_probe(bridge);
> ++ ret = pci_scan_root_bus_bridge(bridge);
> + if (ret < 0) {
> + advk_pcie_remove_msi_irq_domain(pcie);
> + advk_pcie_remove_irq_domain(pcie);
> + return ret;
> + }
> +
> ++ bus = bridge->bus;
> ++
> ++ pci_bus_size_bridges(bus);
> ++ pci_bus_assign_resources(bus);
> ++
> ++ list_for_each_entry(child, &bus->children, node)
> ++ pcie_bus_configure_settings(child);
> ++
> ++ pci_bus_add_devices(bus);
> + return 0;
> + }
> +
> diff --git a/target/linux/mvebu/patches-4.19/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch b/target/linux/mvebu/patches-4.19/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
> new file mode 100644
> index 0000000000..204d6e2aec
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
> @@ -0,0 +1,138 @@
> +From patchwork Thu Sep 28 12:58:34 2017
> +Content-Type: text/plain; charset="utf-8"
> +MIME-Version: 1.0
> +Content-Transfer-Encoding: 7bit
> +Subject: [v2,
> + 3/7] PCI: aardvark: set host and device to the same MAX payload size
> +X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +X-Patchwork-Id: 819587
> +Message-Id: <20170928125838.11887-4-thomas.petazzoni at free-electrons.com>
> +To: Bjorn Helgaas <bhelgaas at google.com>, linux-pci at vger.kernel.org
> +Cc: Jason Cooper <jason at lakedaemon.net>, Andrew Lunn <andrew at lunn.ch>,
> + Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>, Gregory Clement
> + <gregory.clement at free-electrons.com>,
> + Nadav Haklai <nadavh at marvell.com>, Hanna Hawa <hannah at marvell.com>,
> + Yehuda Yitschak <yehuday at marvell.com>,
> + linux-arm-kernel at lists.infradead.org, Antoine Tenart
> + <antoine.tenart at free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
> + <miquel.raynal at free-electrons.com>, Victor Gu <xigu at marvell.com>,
> + Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +Date: Thu, 28 Sep 2017 14:58:34 +0200
> +From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +List-Id: <linux-pci.vger.kernel.org>
> +
> +From: Victor Gu <xigu at marvell.com>
> +
> +Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
> +subsystem will not align the MAX payload size between the host and the
> +device. This patch ensures that the host and device have the same MAX
> +payload size, fixing a number of problems with various PCIe devices.
> +
> +This is part of fixing bug
> +https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
> +reported as the user to be important to get a Intel 7260 mini-PCIe
> +WiFi card working.
> +
> +Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
> +Signed-off-by: Victor Gu <xigu at marvell.com>
> +Reviewed-by: Evan Wang <xswang at marvell.com>
> +Reviewed-by: Nadav Haklai <nadavh at marvell.com>
> +[Thomas: tweak commit log.]
> +Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +---
> + drivers/pci/controller/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
> + 1 file changed, 59 insertions(+), 1 deletion(-)
> +
> +--- a/drivers/pci/controller/pci-aardvark.c
> ++++ b/drivers/pci/controller/pci-aardvark.c
> +@@ -29,9 +29,11 @@
> + #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
> + #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
> + #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
> ++#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
> + #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
> + #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
> + #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
> ++#define PCIE_CORE_MPS_UNIT_BYTE 128
> + #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
> + #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
> + #define PCIE_CORE_LINK_TRAINING BIT(5)
> +@@ -253,7 +255,8 @@ static void advk_pcie_setup_hw(struct ad
> +
> + /* Set PCIe Device Control and Status 1 PF0 register */
> + reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
> +- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
> ++ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
> ++ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
> + PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
> + (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
> + PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
> +@@ -838,6 +841,58 @@ out_release_res:
> + return err;
> + }
> +
> ++static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
> ++{
> ++ u8 *smpss = data;
> ++
> ++ if (!dev)
> ++ return 0;
> ++
> ++ if (!pci_is_pcie(dev))
> ++ return 0;
> ++
> ++ if (*smpss > dev->pcie_mpss)
> ++ *smpss = dev->pcie_mpss;
> ++
> ++ return 0;
> ++}
> ++
> ++static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
> ++{
> ++ int mps;
> ++
> ++ if (!dev)
> ++ return 0;
> ++
> ++ if (!pci_is_pcie(dev))
> ++ return 0;
> ++
> ++ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
> ++ pcie_set_mps(dev, mps);
> ++
> ++ return 0;
> ++}
> ++
> ++static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
> ++{
> ++ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
> ++ u32 reg;
> ++
> ++ /* Find the minimal supported MAX payload size */
> ++ advk_pcie_find_smpss(bus->self, &smpss);
> ++ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
> ++
> ++ /* Configure RC MAX payload size */
> ++ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
> ++ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
> ++ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
> ++ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
> ++
> ++ /* Configure device MAX payload size */
> ++ advk_pcie_bus_configure_mps(bus->self, &smpss);
> ++ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
> ++}
> ++
> + static int advk_pcie_probe(struct platform_device *pdev)
> + {
> + struct device *dev = &pdev->dev;
> +@@ -912,6 +967,9 @@ static int advk_pcie_probe(struct platfo
> + list_for_each_entry(child, &bus->children, node)
> + pcie_bus_configure_settings(child);
> +
> ++ /* Configure the MAX pay load size */
> ++ advk_pcie_configure_mps(bus, pcie);
> ++
> + pci_bus_add_devices(bus);
> + return 0;
> + }
> diff --git a/target/linux/mvebu/patches-4.19/526-PCI-aardvark-disable-LOS-state-by-default.patch b/target/linux/mvebu/patches-4.19/526-PCI-aardvark-disable-LOS-state-by-default.patch
> new file mode 100644
> index 0000000000..b6fcec81f8
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/526-PCI-aardvark-disable-LOS-state-by-default.patch
> @@ -0,0 +1,55 @@
> +From patchwork Thu Sep 28 12:58:36 2017
> +Content-Type: text/plain; charset="utf-8"
> +MIME-Version: 1.0
> +Content-Transfer-Encoding: 7bit
> +Subject: [v2,5/7] PCI: aardvark: disable LOS state by default
> +X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +X-Patchwork-Id: 819590
> +Message-Id: <20170928125838.11887-6-thomas.petazzoni at free-electrons.com>
> +To: Bjorn Helgaas <bhelgaas at google.com>, linux-pci at vger.kernel.org
> +Cc: Jason Cooper <jason at lakedaemon.net>, Andrew Lunn <andrew at lunn.ch>,
> + Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>, Gregory Clement
> + <gregory.clement at free-electrons.com>,
> + Nadav Haklai <nadavh at marvell.com>, Hanna Hawa <hannah at marvell.com>,
> + Yehuda Yitschak <yehuday at marvell.com>,
> + linux-arm-kernel at lists.infradead.org, Antoine Tenart
> + <antoine.tenart at free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
> + <miquel.raynal at free-electrons.com>, Victor Gu <xigu at marvell.com>,
> + Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +Date: Thu, 28 Sep 2017 14:58:36 +0200
> +From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +List-Id: <linux-pci.vger.kernel.org>
> +
> +From: Victor Gu <xigu at marvell.com>
> +
> +Some PCIe devices do not support LOS, and will cause timeouts if the
> +root complex forces the LOS state. This patch disables the LOS state
> +by default.
> +
> +This is part of fixing bug
> +https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
> +reported as the user to be important to get a Intel 7260 mini-PCIe
> +WiFi card working.
> +
> +Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
> +Signed-off-by: Victor Gu <xigu at marvell.com>
> +Reviewed-by: Evan Wang <xswang at marvell.com>
> +Reviewed-by: Nadav Haklai <nadavh at marvell.com>
> +[Thomas: tweak commit log.]
> +Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> +---
> + drivers/pci/controller/pci-aardvark.c | 3 +--
> + 1 file changed, 1 insertion(+), 2 deletions(-)
> +
> +--- a/drivers/pci/controller/pci-aardvark.c
> ++++ b/drivers/pci/controller/pci-aardvark.c
> +@@ -324,8 +324,7 @@ static void advk_pcie_setup_hw(struct ad
> +
> + advk_pcie_wait_for_link(pcie);
> +
> +- reg = PCIE_CORE_LINK_L0S_ENTRY |
> +- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
> ++ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
> + advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
> +
> + reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
> diff --git a/target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch b/target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch
> new file mode 100644
> index 0000000000..0ac3476147
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch
> @@ -0,0 +1,43 @@
> +From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
> +From: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +Date: Thu, 14 Jun 2018 14:24:40 +0200
> +Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
> +
> +Use DT of_pci_get_max_link_speed() facility to allow specifying link
> +capability. If none or unspecified value is given it falls back to gen2,
> +which is default for Armada 3700 SoC.
> +
> +Signed-off-by: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +---
> + drivers/pci/controller/pci-aardvark.c | 11 +++++++++--
> + 1 file changed, 9 insertions(+), 2 deletions(-)
> +
> +--- a/drivers/pci/controller/pci-aardvark.c
> ++++ b/drivers/pci/controller/pci-aardvark.c
> +@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc
> +
> + static void advk_pcie_setup_hw(struct advk_pcie *pcie)
> + {
> ++ struct device *dev = &pcie->pdev->dev;
> ++ struct device_node *node = dev->of_node;
> + u32 reg;
> +
> + /* Set to Direct mode */
> +@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad
> + PCIE_CORE_CTRL2_TD_ENABLE;
> + advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
> +
> +- /* Set GEN2 */
> ++ /* Set GEN */
> + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
> + reg &= ~PCIE_GEN_SEL_MSK;
> +- reg |= SPEED_GEN_2;
> ++ if (of_pci_get_max_link_speed(node) == 1)
> ++ reg |= SPEED_GEN_1;
> ++ else if (of_pci_get_max_link_speed(node) == 3)
> ++ reg |= SPEED_GEN_3;
> ++ else
> ++ reg |= SPEED_GEN_2;
> + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
> +
> + /* Set lane X1 */
> diff --git a/target/linux/mvebu/patches-4.19/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch b/target/linux/mvebu/patches-4.19/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
> new file mode 100644
> index 0000000000..88080d64ca
> --- /dev/null
> +++ b/target/linux/mvebu/patches-4.19/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
> @@ -0,0 +1,73 @@
> +From 33f8fdcedb01680427328d710594facef7a0092c Mon Sep 17 00:00:00 2001
> +From: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +Date: Thu, 14 Jun 2018 14:40:26 +0200
> +Subject: [PATCH 2/2] arm64: dts: armada-3720-espressobin: set max link to gen1
> +
> +Since the beginning there's been an issue with initializing the Atheros
> +based MiniPCIe wireless cards. Here's an example of kerenel log:
> +
> + OF: PCI: host bridge /soc/pcie at d0070000 ranges:
> + OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
> + OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
> + advk-pcie d0070000.pcie: link up
> + advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
> + pci_bus 0000:00: root bus resource [bus 00-ff]
> + pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
> + pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
> + pci 0000:00:00.0: BAR 0: assigned [mem0xe8000000-0xe801ffff 64bit]
> + pci 0000:00:00.0: BAR 6: assigned [mem0xe8020000-0xe802ffff pref]
> + [...]
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x44
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
> + ath9k 0000:00:00.0: enabling device (0000 -> 0002)
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0xc
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x40
> + ath9k 0000:00:00.0: request_irq failed
> + advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
> + ath9k: probe of 0000:00:00.0 failed with error -22
> +
> +The same happens for ath5k cards, while ath10k card didn't appear at
> +all (not detected):
> +
> + OF: PCI: host bridge /soc/pcie at d0070000 ranges:
> + OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
> + OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
> + advk-pcie d0070000.pcie: link never came up
> + advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
> + pci_bus 0000:00: root bus resource [bus 00-ff]
> + pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
> + pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
> + advk-pcie d0070000.pcie: config read/write timed out
> +
> +Following the issue on esppressobin.net forum [1] the workaround seems
> +to be limiting the speed of PCIe bridge to 1st generation. This fixed
> +the initialisation of all tested Atheros wireless cards.
> +The patch in the forum thread swaped registers which would limit speed
> +for all Armada 3700 based boards. The approach in this patch, in
> +conjunction with "PCI: aardvark: allow to specify link capability" patch
> +is less invasive, it only touches the affected board.
> +
> +For the record, the iwlwifi and mt76 cards were not affected by this
> +issue.
> +
> +1. http://espressobin.net/forums/topic/which-pcie-wlan-cards-are-supported
> +
> +Signed-off-by: Tomasz Maciej Nowak <tmn505 at gmail.com>
> +---
> + arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++
> + 1 file changed, 2 insertions(+)
> +
> +--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> ++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> +@@ -46,6 +46,8 @@
> + /* J9 */
> + &pcie0 {
> + status = "okay";
> ++
> ++ max-link-speed = <1>;
> + };
> +
> + /* J6 */
Compile / Test: mamba, rango (P1, relevant bit) kicked around and
generally abused.
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