[OpenWrt-Devel] [PATCH] ar71xx: fix ar724x clock calculation

[Weijie Gao]

Signed-off-by: Weijie Gao <hackpascal at gmail.com>

According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.

The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.

This patch is compatible with the current calculation procedure with default
DIV and REF_DIV values.

Test on both AR7240, AR7241 and AR7242.
---
 ...MIPS-ath79-ar724x-clock-calculation-fixes.patch | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch

diff --git a/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch
new file mode 100644
index 0000000..16d4621
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch
@@ -0,0 +1,22 @@
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -25,7 +25,7 @@
+ #include "common.h"
+ 
+ #define AR71XX_BASE_FREQ	40000000
+-#define AR724X_BASE_FREQ	5000000
++#define AR724X_BASE_FREQ	40000000
+ #define AR913X_BASE_FREQ	5000000
+ 
+ struct clk {
+@@ -99,8 +99,8 @@
+ 	div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
+ 	freq = div * ref_rate;
+ 
+-	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
+-	freq *= div;
++	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
++	freq /= div;
+ 
+ 	cpu_rate = freq;
+ 
-- 
2.1.4
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