[OpenWrt-Devel] [PATCH 2/3] ar71xx: add support for the Giga Device spi nand chips

[miaoqing at qti.qualcomm.com]

From: Miaoqing Pan <miaoqing at codeaurora.org>

Signed-off-by: Miaoqing Pan <miaoqing at codeaurora.org>
---
 ...PS-ath79-add-giga-device-spi-nand-support.patch | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 target/linux/ar71xx/patches-3.18/916-MIPS-ath79-add-giga-device-spi-nand-support.patch

diff --git a/target/linux/ar71xx/patches-3.18/916-MIPS-ath79-add-giga-device-spi-nand-support.patch b/target/linux/ar71xx/patches-3.18/916-MIPS-ath79-add-giga-device-spi-nand-support.patch
new file mode 100644
index 0000000..ff366cc
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.18/916-MIPS-ath79-add-giga-device-spi-nand-support.patch
@@ -0,0 +1,40 @@
+--- a/drivers/mtd/nand/nand_ids.c
++++ b/drivers/mtd/nand/nand_ids.c
+@@ -51,6 +51,19 @@ struct nand_flash_dev nand_flash_ids[] = {
+ 		  SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
+ 		  4 },
+ 
++	{"GD5F1GQ4U 1G 3.3V 8-bit",
++		{ .id = {0xc8, 0xb1} },
++		  SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(4, SZ_512) },
++	{"GD5F2GQ4U 2G 3.3V 8-bit",
++		{ .id = {0xc8, 0xb2} },
++		  SZ_2K, SZ_256, SZ_128K, 0, 2, 128, NAND_ECC_INFO(4, SZ_512) },
++	{"GD5F1GQ4R 1G 1.8V 8-bit",
++		{ .id = {0xc8, 0xa1} },
++		  SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(4, SZ_512) },
++	{"GD5F2GQ4R 2G 1.8V 8-bit",
++		{ .id = {0xc8, 0xa2} },
++		  SZ_2K, SZ_256, SZ_128K, 0, 2, 128, NAND_ECC_INFO(4, SZ_512) },
++
+ 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
+ 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
+ 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
+@@ -178,6 +191,7 @@ struct nand_manufacturers nand_manuf_ids[] = {
+ 	{NAND_MFR_EON, "Eon"},
+ 	{NAND_MFR_SANDISK, "SanDisk"},
+ 	{NAND_MFR_INTEL, "Intel"},
++	{NAND_MFR_GIGADEVICE, "Giga Device"},
+ 	{0x0, "Unknown"}
+ };
+ 
+--- a/include/linux/mtd/nand.h
++++ b/include/linux/mtd/nand.h
+@@ -720,6 +720,7 @@ struct nand_chip {
+ #define NAND_MFR_MICRON		0x2c
+ #define NAND_MFR_AMD		0x01
+ #define NAND_MFR_MACRONIX	0xc2
++#define NAND_MFR_GIGADEVICE	0xc8
+ #define NAND_MFR_EON		0x92
+ #define NAND_MFR_SANDISK	0x45
+ #define NAND_MFR_INTEL		0x89
-- 
1.9.1
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