[OpenWrt-Devel] Merged: ramips: Increase GB-PC2 SPI frequency to 80MHz

Rosen Penev rosenp at gmail.com
Mon Mar 25 17:11:32 EDT 2019

On Mon, Mar 25, 2019 at 1:43 PM Christian Lamparter <chunkeey at gmail.com> wrote:
> On Monday, March 25, 2019 2:16:04 PM CET Petr Štetiar wrote:
> > Thanks! Merged into my staging tree at https://git.openwrt.org/openwrt/staging/ynezz.git
> https://patchwork.ozlabs.org/patch/1034614/#2088615
> So, I think in order for this to "work as expected" the sysclock
> in the mt7621.dtsi should be at 220 MHz (as in the upstream
> drivers/staging/mt7621-dts/mt7621.dtsi) instead of 50 MHz.
According to GCH, that commit is wrong:

As far as the clock goes, it's using a PLL now:
> That said, I don't think this will break anything since the mt7621-spi driver
> from 0043-spi-add-mt7621-support.patch, just limits it at the fake "25 Mhz"
> (which should be ~110 MHz). So, this will just look odd and makes no sense
> at the first glance.
Ah, none of my testing was done with the stock driver, only the upstream one.

There are also other devices with an 80MHz clock in the ramips dts directory.

80MHz looked like it was a peak so that's what I used.
> Cheers,
> Christian

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