[OpenWrt-Devel] [PATCH 1/2] ath79: fix qca955x pcie0 memory size
gch981213 at gmail.com
Fri Feb 1 10:01:46 EST 2019
On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé <f4bug at amsat.org> wrote:
> Now that you pointed this line, I am not sure it is correct...
> It maps I/O (0x01000000) region of 1B (0 0x000001) from PCI 0x00000000
> (0 0x00000000) at 0x0000000 (0x0000000) into cpu space.
> But the DDR is already mapped at 0x0000000 in cpu address space...
> Am I missing something?
The atheros PCIE controller doesn't have an IO space at all. (at least
the documentation doesn't mention it.)
I'm not sure if it's possible to write a PCIE driver without IO space.
I guess the existing code just uses 1 byte of system memory as a
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