[OpenWrt-Devel] [PATCH 1/2] ath79: fix qca955x pcie0 memory size
f4bug at amsat.org
Fri Feb 1 08:53:37 EST 2019
On 1/29/19 5:12 AM, Santiago Piccinini wrote:
> Datasheet states that both PCI ranges are of 0x2000000 size:
> 0x1000_0000-0x11FF_FFF and 0x1200_0000-0x13FF_0000.
> Signed-off-by: Santiago Piccinini <spiccinini at altermundi.net>
Each PCIe root complex region is 32MB wide indeed.
> target/linux/ath79/dts/qca9557.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi
> index bfc2545b27..541aa6916e 100644
> --- a/target/linux/ath79/dts/qca9557.dtsi
> +++ b/target/linux/ath79/dts/qca9557.dtsi
> @@ -186,7 +186,7 @@
> reg = <0x180c0000 0x1000>, /* CRP */
> <0x180f0000 0x100>, /* CTRL */
> <0x14000000 0x1000>; /* CFG */
> reg-names = "crp_base", "ctrl_base", "cfg_base";
> - ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
> + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x02000000 /* pci memory */
"Map 32-bit non-prefetchable (0x02000000) region of 32MB (0 0x04000000)
from PCI 0x10000000 (0 0x10000000) at 0x10000000 (0x10000000) into cpu
OK, your change is correct, thus:
Reviewed-by: Philippe Mathieu-Daudé <f4bug at amsat.org>
> 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
Now that you pointed this line, I am not sure it is correct...
It maps I/O (0x01000000) region of 1B (0 0x000001) from PCI 0x00000000
(0 0x00000000) at 0x0000000 (0x0000000) into cpu space.
But the DDR is already mapped at 0x0000000 in cpu address space...
Am I missing something?
I'm cc'ing Johann who initially wrote that.
> interrupt-parent = <&intc2>;
> interrupts = <1>;
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