[OpenWrt-Devel] Lantiq xrx200 - switch rtl8367rb controlled via builtin mdio (not gpio sck/sda!) in EasyBox 904xDSL

Jonas Gorski jogo at openwrt.org
Thu Jun 18 17:15:42 EDT 2015


On Sun, Jun 14, 2015 at 11:10 PM, Arnold Schulz <arnysch at gmx.net> wrote:
> Hi everyone,
> for fun I have put efforts to solve some mysteries of the EasyBox 904xDSL.
> (here thank you Sylwester and Martin B. for feedback).
> Currently code in driver/net/phy/rtl8366_smi.c is used to control rtl836x
> chips via bitbanging two gpio lines. This does not work for the 904 xDSL.
> Disassembling code from the rtl8367rb.ko (oem firmware) shows that the
> rtl8367rb is controlled via mdio registers at 0xBE10B120~128.
> I'm pretty sure I identified all gpio usage in rt8367rb.ko. There is
> one switch hw reset line (io41). Pin io42 and io43 are setup once
> (AltSel1/0:=1/0; no open drain; Dir:=output for io43) and then left alone,
> I guess to be driven by internal mdio logic responding to 0xBE10B120~128.
> Access to the switch' registers looks somehow cumbersome, e.g.
> u32  RTL83XX_SMI_READ(u32 addr)
> {
>         ifx_vr9_mdio_write(0, 0x1D, 0xFFFF);
>         ifx_vr9_mdio_write(0, 0x1F, 0xE);
>         ifx_vr9_mdio_write(0, 0x1D, 0xFFFF);
>         ifx_vr9_mdio_write(0, 0x17, addr & 0xFFFF)
>         ifx_vr9_mdio_write(0, 0x1D, 0xFFFF);
>         ifx_vr9_mdio_write(0, 0x15, 1);
>         ifx_vr9_mdio_write(0, 0x1D, 0xFFFF);
>         return  ifx_vr9_mdio_read(0, 0x19);
> }
> So many more bits are banged over the bus as the code in rtl8366_smi.c
> does. Me wondering: there must be a chip between, which relays control
> info to the rtl8367rb?

There is no special chip, the RTL8367 provides several means of
accessing the chip registers; using MDIO registers is one of them. It
also understands SPI (likely using different pins though).

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