[PATCH 6/6] mediatek: add Adtran SDG 854-6/854-v6
Tomasz Maciej Nowak
tmn505 at terefe.re
Wed Jun 10 15:40:11 PDT 2026
From: Tomasz Maciej Nowak <tmn505 at gmail.com>
Called Service Delivery Gateway, it's a dual band WiFi 6 router.
Specification
SoC: MediaTek MT7622A
RAM: 1 GiB DDR3L
Storage: 4 GiB eMMC
WiFi: 2.4 GHz MediaTek MT7915AN 4T4R oversized Mini PCIe card
5 GHz MediaTek MT7915AN 4T4R oversized Mini PCIe card
Ethernet: 4x 10/100/1000 Mbps MT7531AE
only one of the following can be active:
1x 10/100/1000/2500 Mbps MaxLinear GPY211C wired to 5th port
of MT7531AE
- or -
1x 10/100/1000/2500 Mbps SFP cage wired to 5th port of
MT7531AE
USB: 1x 3.0
LEDs: 6x GPIO controlled
1x RGBW controlled by MCU
Buttons: 2x GPIO controlled
UART: 4-pin Dupont connector on bottom of the device, 2.54 mm pitch,
3.3V logic, marked JP1 on PCB
baud: 115200, parity: none, flow control: none
______
| Tx Rx
| . .
SFP | . .
slot |3.3V GND
area |
|
______|
Unsupported features
Bluetooth
FXS POTS (v6 variant)
Installation
1. Prepare TFTP server with OpenWrt initramfs image and rename that
image to "fit-multi.itb".
2. Connect to one of LAN ports.
3. Connect to UART port.
4. Power on the device and type "st" to enter U-Boot command line. The
window to do that might be very short (below 1s), so type it as soon
as "U-Boot ..." string appears.
5. Alter U-Boot environment with following commands (don't omit quotes):
setenv OpenWrt 'mmc init; mmc read ${loadaddr} 0x1600 0xafff; source ${loadaddr}:bootscript'
setenv bootcmd 'run OpenWrt'
saveenv
6. Download the OpenWrt initramfs image with "tftpboot" command.
The default "serverip" is 192.168.1.10 and "ipaddr" 192.168.1.1.
Adjust them if needed.
7. Boot the initramfs image by issuing "bootm $loadaddr".
8. After OpenWrt finishes booting, download OpenWrt sysupgrade image and
use "sysupgrade" command to write it to eMMC.
9. After sysupgrade finishes writing the device will reboot to OpenWrt.
When the front LED is solid white the device is ready for
configuration.
Notes
Decision on what type of port is active, Base-T or SFP, is made in
U-Boot phase, which means device needs full boot cycle to choose which
port it will use. By default Base-T port is active, plug SFP stick and
reboot the device to make SFP port active. Unfortunately some SFP
sticks, particularly GPON, can take long time to show presence, which
can be missed by detection phase. Issuing "fw_setenv sfp force" will
force the SFP cage being active after reboot. To revert to automatic
detection, issue "fw_setenv sfp" and reboot.
Some SFP sticks might not fit in the slot because of plastic case
elements. This case element can be removed, after disassembling the
case, or one can use pliers to cut out the necessary space in that case
element.
WAN LED is on when WAN Base-T port link is up, no traffic indication.
Fiber LED is on when SFP cage is active, no traffic indication.
Known issues
See "Unsupported features"
Erratic behaviour of front RGBW LED, often doesn't light up.
Signed-off-by: Tomasz Maciej Nowak <tmn505 at gmail.com>
---
.../uboot-envtools/files/mediatek_mt7622 | 3 +
.../dts/mt7622-adtran-sdg-854-6-extphy.dts | 22 +
.../dts/mt7622-adtran-sdg-854-6-sfp.dts | 30 +
.../mediatek/dts/mt7622-adtran-sdg-854.dtsi | 547 ++++++++++++++++++
.../image/bootscript-adtran_sdg-854-6.txt | 21 +
target/linux/mediatek/image/mt7622.mk | 14 +
.../mt7622/base-files/lib/upgrade/platform.sh | 29 +-
target/linux/mediatek/mt7622/config-6.18 | 1 +
...-phy-mxl-gpy-soft-reset-during-probe.patch | 64 ++
9 files changed, 718 insertions(+), 13 deletions(-)
create mode 100644 target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-extphy.dts
create mode 100644 target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-sfp.dts
create mode 100644 target/linux/mediatek/dts/mt7622-adtran-sdg-854.dtsi
create mode 100644 target/linux/mediatek/image/bootscript-adtran_sdg-854-6.txt
create mode 100644 target/linux/mediatek/patches-6.18/951-smartrg-net-phy-mxl-gpy-soft-reset-during-probe.patch
diff --git a/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622 b/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622
index 805261bcdad7..afb5f54c5e99 100644
--- a/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622
+++ b/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622
@@ -17,6 +17,9 @@ ubootenv_add_mmc_default() {
board=$(board_name)
case "$board" in
+adtran,sdg-854-6)
+ ubootenv_add_mmc "nvram" "" "0x0" "0x8000"
+ ;;
asiarf,ap7622-wh1)
ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x1000" "0x10000"
;;
diff --git a/target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-extphy.dts b/target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-extphy.dts
new file mode 100644
index 000000000000..e93a063df75a
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-extphy.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+
+/dts-v1/;
+
+#include "mt7622-adtran-sdg-854.dtsi"
+
+&led_wan {
+ linux,default-trigger = "mt7530-0:05:link";
+};
+
+&mux_sel {
+ output-high;
+};
+
+&phy5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ mxl,soft-reset;
+};
+
+&port5 {
+ phy-handle = <&phy5>;
+};
diff --git a/target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-sfp.dts b/target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-sfp.dts
new file mode 100644
index 000000000000..eedbd1f73cb7
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7622-adtran-sdg-854-6-sfp.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+
+/dts-v1/;
+
+#include "mt7622-adtran-sdg-854.dtsi"
+
+/ {
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&pio 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 77 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 87 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&led_sfp {
+ default-state = "on";
+};
+
+&mux_sel {
+ output-low;
+};
+
+&port5 {
+ sfp = <&sfp>;
+ managed = "in-band-status";
+};
diff --git a/target/linux/mediatek/dts/mt7622-adtran-sdg-854.dtsi b/target/linux/mediatek/dts/mt7622-adtran-sdg-854.dtsi
new file mode 100644
index 000000000000..8791e72baa32
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7622-adtran-sdg-854.dtsi
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+
+/ {
+ model = "Adtran Service Delivery Gateway 854-6/854-v6";
+ compatible = "adtran,sdg-854-6", "adtran,sdg-854-v6", "mediatek,mt7622";
+
+ aliases {
+ label-mac-device = &port5;
+ led-boot = &led_status_blue;
+ led-failsafe = &led_status_blue;
+ led-running = &led_status_white;
+ led-upgrade = &led_status_blue;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=PARTLABEL=res1";
+ };
+
+ cpus {
+ cpu at 0 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+
+ cpu at 1 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ button-reset {
+ label = "reset";
+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ button-wps {
+ label = "wps";
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-fxs {
+ color = <LED_COLOR_ID_GREEN>;
+ function = "telephone";
+ gpios = <&pio 100 GPIO_ACTIVE_LOW>;
+ };
+
+ led_sfp: led-sfp {
+ color = <LED_COLOR_ID_GREEN>;
+ function = "fiber";
+ gpios = <&pio 95 GPIO_ACTIVE_LOW>;
+ };
+
+ led_wan: led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&pio 98 GPIO_ACTIVE_LOW>;
+ };
+
+ led-wlan2g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ gpios = <&pio 96 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0radio";
+ };
+
+ led-wlan5g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ gpios = <&pio 97 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy1radio";
+ };
+
+ led-wps {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WPS;
+ gpios = <&pio 99 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory at 40000000 {
+ reg = <0x0 0x40000000 0x0 0x40000000>;
+ device_type = "memory";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /delete-node/ramoops at 42ff0000;
+
+ bootdata at 45000000 {
+ no-map;
+ reg = <0x0 0x45000000 0x0 0x00001000>;
+ };
+
+ ramoops_reserved: ramoops1 at 45001000 {
+ no-map;
+ compatible = "ramoops";
+ reg = <0x0 0x45001000 0x0 0x00140000>;
+ ftrace-size = <0x20000>;
+ record-size = <0x20000>;
+ console-size = <0x20000>;
+ pmsg-size = <0x80000>;
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ð {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_pins>;
+
+ gmac0: mac at 0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+ nvmem-cells = <&macaddr 0x1>;
+ nvmem-cell-names = "mac-address";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch at 1f {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swphy0: phy at 0 {
+ reg = <0>;
+ };
+
+ swphy1: phy at 1 {
+ reg = <1>;
+ };
+
+ swphy2: phy at 2 {
+ reg = <2>;
+ };
+
+ swphy3: phy at 3 {
+ reg = <3>;
+ };
+
+ phy5: ethernet-phy at 5 {
+ reg = <5>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan4";
+ phy-handle = <&swphy0>;
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan3";
+ phy-handle = <&swphy1>;
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&swphy2>;
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan1";
+ phy-handle = <&swphy3>;
+ };
+
+ port at 4 {
+ status = "disabled";
+ };
+
+ port5: port at 5 {
+ reg = <5>;
+ label = "wan";
+ nvmem-cells = <&macaddr 0x0>;
+ nvmem-cell-names = "mac-address";
+ phy-mode = "2500base-x";
+ };
+
+ port at 6 {
+ reg = <6>;
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ leds at 30 {
+ compatible = "srg,sysled";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led at 1 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ reg = <1>;
+ };
+
+ led at 2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ reg = <2>;
+ };
+
+ led_status_blue: led at 3 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ reg = <3>;
+ };
+
+ led_status_white: led at 4 {
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_STATUS;
+ reg = <4>;
+ };
+ };
+};
+
+&mmc0 {
+ status = "okay";
+
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&emmc_default_pins>;
+ pinctrl-1 = <&emmc_uhs_pins>;
+ bus-width = <8>;
+ max-frequency = <50000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+ non-removable;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ card at 0 {
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ partitions {
+ block-partition-nvram {
+ partnum = <3>;
+ partname = "nvram";
+
+ nvmem-layout {
+ compatible = "u-boot,env";
+ };
+ };
+
+ block-partition-rf {
+ partnum = <4>;
+ partname = "rf";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom0: eeprom at 0 {
+ reg = <0x0 0x5000>;
+ };
+
+ eeprom1: eeprom at 5000 {
+ reg = <0x5000 0x5000>;
+ };
+ };
+ };
+
+ block-partition-mfginfo {
+ partnum = <7>;
+ partname = "mfginfo";
+
+ nvmem-layout {
+ compatible = "adtran,mfginfo";
+
+ macaddr: mfg-mac {
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+ };
+ };
+ };
+};
+
+&pcie0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+};
+
+&slot0 {
+ mt7915 at 0,0 {
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom0>, <&macaddr 0x4>;
+ nvmem-cell-names = "eeprom", "mac-address";
+ ieee80211-freq-limit = <2400000 2500000>;
+ };
+};
+
+&pcie1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+};
+
+&slot1 {
+ mt7915 at 0,0 {
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom1>, <&macaddr 0xa>;
+ nvmem-cell-names = "eeprom", "mac-address";
+ ieee80211-freq-limit = <5170000 5835000>;
+ };
+};
+
+&pio {
+ mux_sel: auxin1-hog {
+ gpio-hog;
+ gpios = <88 GPIO_ACTIVE_LOW>;
+ line-name = "mux-sel";
+ };
+
+ auxin2-hog {
+ gpio-hog;
+ gpios = <89 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "mux-oe";
+ };
+
+ emmc_default_pins: emmc-default-pins {
+ mux {
+ function = "emmc", "emmc_rst";
+ groups = "emmc";
+ };
+
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ bias-pull-down;
+ };
+ };
+
+ emmc_uhs_pins: emmc-uhs-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-down;
+ };
+ };
+
+ eth_pins: eth-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio", "rgmii_via_gmac2";
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c0";
+ };
+ };
+
+ pcie0_pins: pcie0-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie0_pad_perst",
+ "pcie0_1_waken",
+ "pcie0_1_clkreq";
+ };
+ };
+
+ pcie1_pins: pcie1-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie1_pad_perst";
+ };
+ };
+
+ pmic_bus_pins: pmic-bus-pins {
+ mux {
+ function = "pmic";
+ groups = "pmic_bus";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ watchdog_pins: watchdog-pins {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+&pwrap {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_bus_pins>;
+};
+
+&ssusb {
+ status = "okay";
+
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+};
+
+&u3phy {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&watchdog {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
+};
diff --git a/target/linux/mediatek/image/bootscript-adtran_sdg-854-6.txt b/target/linux/mediatek/image/bootscript-adtran_sdg-854-6.txt
new file mode 100644
index 000000000000..ab4466b82b69
--- /dev/null
+++ b/target/linux/mediatek/image/bootscript-adtran_sdg-854-6.txt
@@ -0,0 +1,21 @@
+# SFP pull-ups
+mw.l 0x10211930 0x00300000 1
+# Toggle AUXINx pins to GPIO
+mw.l 0x10211cf0 0x000000ff 1
+
+# Detect if SFP cage is occupied by checking GPIO87_DIN
+setexpr.l gpio87_din 0x800000 \& *0x10211220
+
+echo
+if test ${gpio87_din} -eq 0; then
+ setenv fit_config mt7622-adtran-sdg-854-6-sfp
+ echo "SFP cage status: occupied"
+elif test -n ${sfp} && test ${sfp} = force; then
+ setenv fit_config mt7622-adtran-sdg-854-6-sfp
+ echo "SFP cage status: occupied (forced)"
+else
+ setenv fit_config config-1
+ echo "SFP cage status: empty"
+fi
+
+bootm ${loadaddr}#${fit_config}
diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk
index c63e1fcf64bd..108e7618896d 100644
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@@ -52,6 +52,20 @@ define Build/mt7622-gpt
rm $@.tmp
endef
+define Device/adtran_sdg-854-6
+ DEVICE_VENDOR := Adtran
+ DEVICE_MODEL := SDG-854-6
+ DEVICE_ALT0_VENDOR := Adtran
+ DEVICE_ALT0_MODEL := SDG-854-v6
+ DEVICE_DTS := mt7622-adtran-sdg-854-6-extphy mt7622-adtran-sdg-854-6-sfp
+ DEVICE_DTS_DIR := ../dts
+ DEVICE_PACKAGES += e2fsprogs f2fsck mkf2fs kmod-mt7915e kmod-mt7915-firmware kmod-sfp kmod-usb3
+ BOOT_SCRIPT := bootscript-$$(DEVICE_NAME).txt
+ KERNEL_SIZE := 19711k
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += adtran_sdg-854-6
+
define Device/asiarf_ap7622-wh1
DEVICE_VENDOR := AsiaRF
DEVICE_MODEL := AP7622-WH1
diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
index 8674339f0685..b048dffdc43d 100755
--- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
@@ -6,6 +6,12 @@ platform_do_upgrade() {
local file_type=$(identify $1)
case "$board" in
+ adtran,sdg-854-6|\
+ smartrg,sdg-841-t6)
+ CI_KERNPART="boot"
+ CI_ROOTPART="res1"
+ emmc_do_upgrade "$1"
+ ;;
bananapi,bpi-r64|\
linksys,e8450-ubi|\
ubnt,unifi-6-lr-v1-ubootmod|\
@@ -36,11 +42,6 @@ platform_do_upgrade() {
fi
default_do_upgrade "$1"
;;
- smartrg,sdg-841-t6)
- CI_KERNPART="boot"
- CI_ROOTPART="res1"
- emmc_do_upgrade "$1"
- ;;
*)
default_do_upgrade "$1"
;;
@@ -56,11 +57,7 @@ platform_check_image() {
[ "$#" -gt 1 ] && return 1
case "$board" in
- buffalo,wsr-2533dhp2|\
- buffalo,wsr-2533dhp3|\
- buffalo,wsr-3200ax4s)
- buffalo_check_image "$board" "$magic" "$1" || return 1
- ;;
+ adtran,sdg-854-6|\
dlink,eagle-pro-ai-m32-a1|\
dlink,eagle-pro-ai-r32-a1|\
elecom,wrc-g01|\
@@ -72,6 +69,11 @@ platform_check_image() {
nand_do_platform_check "$board" "$1"
return $?
;;
+ buffalo,wsr-2533dhp2|\
+ buffalo,wsr-2533dhp3|\
+ buffalo,wsr-3200ax4s)
+ buffalo_check_image "$board" "$magic" "$1" || return 1
+ ;;
*)
fit_check_image "$1"
return $?
@@ -83,13 +85,14 @@ platform_check_image() {
platform_copy_config() {
case "$(board_name)" in
+ adtran,sdg-854-6|\
+ smartrg,sdg-841-t6)
+ emmc_copy_config
+ ;;
bananapi,bpi-r64)
if [ "$CI_METHOD" = "emmc" ]; then
emmc_copy_config
fi
;;
- smartrg,sdg-841-t6)
- emmc_copy_config
- ;;
esac
}
diff --git a/target/linux/mediatek/mt7622/config-6.18 b/target/linux/mediatek/mt7622/config-6.18
index 136c192bc651..e5e18983a337 100644
--- a/target/linux/mediatek/mt7622/config-6.18
+++ b/target/linux/mediatek/mt7622/config-6.18
@@ -241,6 +241,7 @@ CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_LEDS_SMARTRG_LED=y
+CONFIG_LED_TRIGGER_PHY=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
diff --git a/target/linux/mediatek/patches-6.18/951-smartrg-net-phy-mxl-gpy-soft-reset-during-probe.patch b/target/linux/mediatek/patches-6.18/951-smartrg-net-phy-mxl-gpy-soft-reset-during-probe.patch
new file mode 100644
index 000000000000..599de3e58632
--- /dev/null
+++ b/target/linux/mediatek/patches-6.18/951-smartrg-net-phy-mxl-gpy-soft-reset-during-probe.patch
@@ -0,0 +1,64 @@
+From: Chad Monroe <chad at monroe.io>
+Date: Thu, 27 Apr 2023 16:55:04 -0700
+Subject: [PATCH] net: phy: mxl: soft reset during probe
+
+Some hardware platforms don't have a PHY reset line hooked
+up. Soft reset PHY during probe so it's in a known state.
+
+Signed-off-by: Chad Monroe <chad at monroe.io>
+---
+ drivers/net/phy/mxl-gpy.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/net/phy/mxl-gpy.c
++++ b/drivers/net/phy/mxl-gpy.c
+@@ -10,6 +10,7 @@
+ #include <linux/bitfield.h>
+ #include <linux/hwmon.h>
+ #include <linux/mutex.h>
++#include <linux/of.h>
+ #include <linux/phy.h>
+ #include <linux/polynomial.h>
+ #include <linux/property.h>
+@@ -329,6 +330,21 @@ out:
+ return ret;
+ }
+
++static int gpy_soft_reset(struct phy_device *phydev)
++{
++ int ret;
++
++ phydev_info(phydev, "gpy_soft_reset: start VSPEC1_SGMII_CTRL=%04x\n",
++ phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL));
++
++ ret = genphy_soft_reset(phydev);
++
++ phydev_info(phydev, "gpy_soft_reset: complete ret=%d VSPEC1_SGMII_CTRL=%04x\n",
++ ret, phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL));
++
++ return ret;
++}
++
+ static int gpy_config_init(struct phy_device *phydev)
+ {
+ /* Nothing to configure. Configuration Requirement Placeholder */
+@@ -349,12 +365,19 @@ static int gpy_probe(struct phy_device *
+ struct gpy_priv *priv;
+ int fw_version;
+ int ret;
++ struct device_node *node = phydev->mdio.dev.of_node;
+
+ if (!phydev->is_c45) {
+ ret = phy_get_c45_ids(phydev);
+ if (ret < 0)
+ return ret;
+ }
++
++ if (of_property_read_bool(node, "mxl,soft-reset")) {
++ ret = gpy_soft_reset(phydev);
++ if (ret < 0)
++ return ret;
++ }
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
--
2.54.0
More information about the openwrt-devel
mailing list