[PATCH] target: mediatek: Enable WED for MT7988 devices running 6.12.x kernels
Lorenzo Bianconi
lorenzo at kernel.org
Thu Jul 17 09:45:48 PDT 2025
Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
---
.../198-dts-mt7988a-enable-wed.patch | 167 ++++++++++++++++++
1 file changed, 167 insertions(+)
create mode 100644 target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch
diff --git a/target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch b/target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch
new file mode 100644
index 0000000000..a78aba3cee
--- /dev/null
+++ b/target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch
@@ -0,0 +1,167 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+@@ -145,6 +145,32 @@
+ reg = <0 0x43000000 0 0x50000>;
+ no-map;
+ };
++
++ wmcpu_emi: wmcpu-reserved at 47cc0000 {
++ reg = <0 0x47cc0000 0 0x00100000>;
++ no-map;
++ };
++
++ wo_emi0: wo-emi at 4f600000 {
++ reg = <0 0x4f600000 0 0x40000>;
++ no-map;
++ };
++
++ wo_emi1: wo-emi at 4f640000 {
++ reg = <0 0x4f640000 0 0x40000>;
++ no-map;
++ };
++
++ wo_emi2: wo-emi at 4f680000 {
++ reg = <0 0x4f680000 0 0x40000>;
++ no-map;
++ };
++
++ wo_data: wo-data at 4f700000 {
++ reg = <0 0x4f700000 0 0x800000>;
++ no-map;
++ shared = <1>;
++ };
+ };
+
+ soc {
+@@ -867,6 +893,50 @@
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ };
++
++ wed0: wed at 15010000 {
++ compatible = "mediatek,mt7988-wed",
++ "syscon";
++ reg = <0 0x15010000 0 0x2000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++ memory-region = <&wo_emi0>, <&wo_data>;
++ memory-region-names = "wo-emi", "wo-data";
++ mediatek,wo-ccif = <&wo_ccif0>;
++ mediatek,wo-ilm = <&wo_ilm0>;
++ mediatek,wo-dlm = <&wo_dlm0>;
++ mediatek,wo-cpuboot = <&wo_cpuboot0>;
++ };
++
++ wed1: wed at 15012000 {
++ compatible = "mediatek,mt7988-wed",
++ "syscon";
++ reg = <0 0x15012000 0 0x2000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
++ memory-region = <&wo_emi1>, <&wo_data>;
++ memory-region-names = "wo-emi", "wo-data";
++ mediatek,wo-ccif = <&wo_ccif1>;
++ mediatek,wo-ilm = <&wo_ilm1>;
++ mediatek,wo-dlm = <&wo_dlm1>;
++ mediatek,wo-cpuboot = <&wo_cpuboot1>;
++ };
++
++ wed2: wed at 15014000 {
++ compatible = "mediatek,mt7988-wed",
++ "syscon";
++ reg = <0 0x15014000 0 0x2000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
++ memory-region = <&wo_emi2>, <&wo_data>;
++ memory-region-names = "wo-emi", "wo-data";
++ mediatek,wo-ccif = <&wo_ccif2>;
++ mediatek,wo-ilm = <&wo_ilm2>;
++ mediatek,wo-dlm = <&wo_dlm2>;
++ mediatek,wo-cpuboot = <&wo_cpuboot2>;
+ };
+
+ switch: switch at 15020000 {
+@@ -1086,6 +1156,7 @@
+ <&apmixedsys CLK_APMIXED_SGMPLL>;
+ mediatek,ethsys = <ðsys>;
+ mediatek,infracfg = <&topmisc>;
++ mediatek,wed = <&wed0>, <&wed1>, <&wed2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+@@ -1147,6 +1218,72 @@
+ };
+ };
+
++ wo_ccif0: syscon at 151a5000 {
++ compatible = "mediatek,mt7988-wo-ccif", "syscon";
++ reg = <0 0x151a5000 0 0x1000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ wo_ccif1: syscon at 152a5000 {
++ compatible = "mediatek,mt7988-wo-ccif", "syscon";
++ reg = <0 0x152a5000 0 0x1000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ wo_ccif2: syscon at 153a5000 {
++ compatible = "mediatek,mt7988-wo-ccif", "syscon";
++ reg = <0 0x153a5000 0 0x1000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ wo_ilm0: syscon at 151e0000 {
++ compatible = "mediatek,mt7988-wo-ilm", "syscon";
++ reg = <0 0x151e0000 0 0x8000>;
++ };
++
++ wo_ilm1: syscon at 152e0000 {
++ compatible = "mediatek,mt7988-wo-ilm", "syscon";
++ reg = <0 0x152e0000 0 0x8000>;
++ };
++
++ wo_ilm2: syscon at 153e0000 {
++ compatible = "mediatek,mt7988-wo-ilm", "syscon";
++ reg = <0 0x153e0000 0 0x8000>;
++ };
++
++ wo_dlm0: syscon at 151e8000 {
++ compatible = "mediatek,mt7988-wo-dlm", "syscon";
++ reg = <0 0x151e8000 0 0x2000>;
++ };
++
++ wo_dlm1: syscon at 152e8000 {
++ compatible = "mediatek,mt7988-wo-dlm", "syscon";
++ reg = <0 0x152e8000 0 0x2000>;
++ };
++
++ wo_dlm2: syscon at 153e8000 {
++ compatible = "mediatek,mt7988-wo-dlm", "syscon";
++ reg = <0 0x153e8000 0 0x2000>;
++ };
++
++ wo_cpuboot0: syscon at 15194000 {
++ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
++ reg = <0 0x15194000 0 0x1000>;
++ };
++
++ wo_cpuboot1: syscon at 15294000 {
++ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
++ reg = <0 0x15294000 0 0x1000>;
++ };
++
++ wo_cpuboot2: syscon at 15394000 {
++ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
++ reg = <0 0x15394000 0 0x1000>;
++ };
++
+ crypto: crypto at 15600000 {
+ compatible = "inside-secure,safexcel-eip197b";
+ reg = <0 0x15600000 0 0x180000>;
--
2.50.1
More information about the openwrt-devel
mailing list