MIPS per-cpu "shadow interrupts" (?)

[Caleb James DeLisle]

Hello folks,


I'm working on what I hope will be my first contribution, support for EcoNet EN75xx MIPS 34K SoCs.

I ran into something I've never seen before and I wanted some advice on it. On this platform there 
is something I've taken to calling "shadow interrupts", they never fire but they provide a way to 
control one (v)CPU's view of a per-cpu interrupt. For example: Masking int 30 causes int 31 to stop 
firing on the 2nd CPU.

I'd be fine to write econet,shadow-interrupts = [ 1e 1f ] in the DTS file and call it a day, but I 
don't want to be treating this like alien tech if it actually isn't.

So my question: Is this a known thing? Does it have a name? Is there some term I can search for, or 
some existing PIC driver I can look at and copy from?


Thanks,

Caleb