[2/2] mediatek: add eip197 inside-secure driver support for MT7988 SoC series

[Chris.Chou at mediatek.com]

From: Chris Chou <chris.chou at mediatek.com>

Add configuration for axi burst size and rx burst size and enable eip197
clock gate.

Signed-off-by: Chris Chou <chris.chou at mediatek.com>
---
 ...pto-add-eip197-inside-secure-support.patch | 64 +++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 target/linux/mediatek/patches-6.6/402-crypto-add-eip197-inside-secure-support.patch

diff --git a/target/linux/mediatek/patches-6.6/402-crypto-add-eip197-inside-secure-support.patch b/target/linux/mediatek/patches-6.6/402-crypto-add-eip197-inside-secure-support.patch
new file mode 100644
index 0000000..ec0a9fe
--- /dev/null
+++ b/target/linux/mediatek/patches-6.6/402-crypto-add-eip197-inside-secure-support.patch
@@ -0,0 +1,64 @@
+--- a/drivers/crypto/inside-secure/safexcel.c
++++ b/drivers/crypto/inside-secure/safexcel.c
+@@ -414,13 +414,13 @@ static int eip197_load_firmwares(struct
+ 	const struct firmware *fw[FW_NB];
+ 	char fw_path[37], *dir = NULL;
+ 	int i, j, ret = 0, pe;
+-	int ipuesz, ifppsz, minifw = 0;
++	int ipuesz, ifppsz, minifw = 1;
+ 
+ 	if (priv->data->version == EIP197D_MRVL)
+ 		dir = "eip197d";
+ 	else if (priv->data->version == EIP197B_MRVL ||
+ 		 priv->data->version == EIP197_DEVBRD)
+-		dir = "eip197b";
++		dir = "eip197_minifw";
+ 	else if (priv->data->version == EIP197C_MXL)
+ 		dir = "eip197c";
+ 	else
+@@ -455,6 +455,9 @@ retry_fw:
+ 
+ 	ipuesz = eip197_write_firmware(priv, fw[FW_IPUE]);
+ 
++	for (j = 0; j < i; j++)
++		release_firmware(fw[j]);
++
+ 	if (eip197_start_firmware(priv, ipuesz, ifppsz, minifw)) {
+ 		dev_dbg(priv->dev, "Firmware loaded successfully\n");
+ 		return 0;
+@@ -605,6 +608,11 @@ static int safexcel_hw_init(struct safex
+ 	 */
+ 	if (priv->flags & SAFEXCEL_HW_EIP197) {
+ 		val = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
++		/* Clear axi_burst_size and rx_burst_size */
++		val &= 0xffffff00;
++		/* Set axi_burst_size = 3, rx_burst_size = 3 */
++		val |= EIP197_MST_CTRL_RD_CACHE(3);
++		val |= EIP197_MST_CTRL_WD_CACHE(3);
+ 		val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
+ 		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
+ 	}
+@@ -805,6 +813,12 @@ static int safexcel_hw_init(struct safex
+ 			return ret;
+ 	}
+ 
++	/* Allow clocks to be forced on for EIP197 */
++	if (priv->flags & SAFEXCEL_HW_EIP197) {
++		writel(0xffffffff, EIP197_HIA_GEN_CFG(priv) + EIP197_FORCE_CLOCK_ON);
++		writel(0xffffffff, EIP197_HIA_GEN_CFG(priv) + EIP197_FORCE_CLOCK_ON2);
++	}
++
+ 	return safexcel_hw_setup_cdesc_rings(priv) ?:
+ 	       safexcel_hw_setup_rdesc_rings(priv) ?:
+ 	       0;
+--- a/drivers/crypto/inside-secure/safexcel.h
++++ b/drivers/crypto/inside-secure/safexcel.h
+@@ -189,6 +189,8 @@
+ #define EIP197_PE_DEBUG(n)			(0x1ff4 + (0x2000 * (n)))
+ #define EIP197_PE_OPTIONS(n)			(0x1ff8 + (0x2000 * (n)))
+ #define EIP197_PE_VERSION(n)			(0x1ffc + (0x2000 * (n)))
++#define EIP197_FORCE_CLOCK_ON2			0xffd8
++#define EIP197_FORCE_CLOCK_ON			0xffe8
+ #define EIP197_MST_CTRL				0xfff4
+ #define EIP197_OPTIONS				0xfff8
+ #define EIP197_VERSION				0xfffc
-- 
2.45.2