[OpenWrt-Devel] SPI 104 MHz on ar7240/Spansion S25FL032P

[Piotr Dymacz]

Hi Adrian,

On 10.02.2020 12:25, Adrian Schmutzler wrote:
> Hi,
> 
> while reviewing the PR for the TL-WA830REv1 [1], I was wondered about the
> unusually high
> spi-max-frequency = <104000000>;
> 
> The author states it's running stable, the datasheet tells
> 
> Normal READ (Serial): 40-MHz clock rate
> FAST_READ (Serial): 104-MHz clock rate (maximum)
> DUAL I/O FAST_READ: 80-MHz clock rate or 20 MB/s effective data rate
> QUAD I/O FAST_READ: 80 MHz clock rate or 40 MB/s effective data rate
> 
> and according to the author, there are other boards with the same chip and this
> frequency, e.g.
> https://github.com/openwrt/openwrt/blob/master/target/linux/ath79/dts/ar9331_tpl
> ink_tl-mr3020-v1.dts#L123
> 
> So, can somebody lend me some expertise whether the value is okay?

The 'spi-max-frequency' property applies to the SPI slave node and the 
device it represents, thus if this flash IC can run with 104 MHz clock, 
then (according to the standard) it's correct (see also note: [0]).

But, a totally different story is:
- max. frequency of SPI clock for this platform
- real max. frequency on this particular PCB (it's serial, so length of 
traces, crosstalk and many other factors have to be considered)

Based only on formula from datasheet(s) [1], on ath79 WiSOCs SPI clock 
could go (in theory) up to ~100 MHz (with AHB bus clocked at 200 MHz).

I suppose if the spi_clk is set to the maximum possible value, it gets 
limited anyway by some 'internals' (hardware capabilities). For example, 
if you check 'SPI Timing' section in QCA9563 datasheet, you will see 
that min. SPI clock period is 40 ns which gives 25 MHz clock. On the 
other hand, in AR9331 min. period is 20 ns, so 50 MHz clock (based on my 
experience, running it with 35+ MHz always caused problems with data 
integrity on various boards).

Even more information on this subject gives QCA9531 v2 datasheet 
(minimum TDS for QCA9531 v2 is 11 ns):

"Actual SPI operating frequency is dependent on the CLK-to-SO flash 
delay and the CLK/MISO signals propagation delay in the board. The 
minimum SPI_CLK period is 2 * (TDS + (CK-to-SO flash delay) + (board 
propagation delay of CLK + board propagation delay of MISO signals)."

So, setting 104 MHz in DTS on that particular platform means the SPI 
flash will operate on max. hardware possible clock (which of course 
would never reach 104 MHz). Is this safe for that board? I don't know 
and I don't know how fast SPI clock can actually run on AR7240.

[0] 104 MHz applies for all single SPI mode instructions excluding 
'normal READ' (opcode 0x3) thus in this case, this value can be set only 
together with 'm25p,fast-read' property. Otherwise, according to SPI 
flash IC datasheet, it should be set to 40 MHz.

[1] spi_clk = ahb_clk/((clk_div + 1) * 2), where clk_div >= 0 and <= 63.

-- 
Cheers,
Piotr

> 
> Best
> 
> Adrian Schmutzler
> 
> [1] https://github.com/openwrt/openwrt/pull/2752#discussion_r375829096
> 
> 
> 
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> 


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