[PATCH 2/3] ramips: add RT6855A support to ethernet driver

[Chuanhong Guo]

Hi!

On Thu, Dec 24, 2020 at 12:52 AM Rafaël Carré <funman at videolan.org> wrote:
>
> TODO: document offsets in rt305x_mii_write ?

Please do so if you know what they mean.

>  [...]
> diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c
> index 292f11a170..7f3693e6c1 100644
> --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c
> +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c
> @@ -85,6 +85,7 @@
>  #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
>  #define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
>  #define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
> +#define RT305X_ESW_PCR0_WT_DONE                BIT(31)
>
>  #define RT305X_ESW_PCR1_WT_DONE                BIT(0)
>
> @@ -271,8 +272,13 @@ static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
>         int ret = 0;
>
>         while (1) {
> +#ifdef CONFIG_SOC_RT6855A
> +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR0) &
> +                     RT305X_ESW_PCR0_WT_DONE))
> +#else
>                 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
>                       RT305X_ESW_PCR1_WT_DONE))
> +#endif

Try using compatible strings to distinguish hardware, instead of
ifdefs like this.

>                         break;
>                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
>                         ret = 1;
> @@ -281,15 +287,27 @@ static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
>         }
>
>         write_data &= 0xffff;
> +#ifdef CONFIG_SOC_RT6855A
> +       esw_w32(esw, (write_data ) | (phy_register << 16) | (phy_addr << 24) | (1 << 30),
> +               RT305X_ESW_REG_PCR0);
> +       esw_w32(esw, (write_data ) | (phy_register << 16) | (phy_addr << 24) | (3 << 30),
> +               RT305X_ESW_REG_PCR0);
> +#else
>         esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
>                       (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
>                       (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
>                 RT305X_ESW_REG_PCR0);
> +#endif
>
>         t_start = jiffies;
>         while (1) {
> -               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
> -                           RT305X_ESW_PCR1_WT_DONE)
> +#ifdef CONFIG_SOC_RT6855A
> +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR0) &
> +                     RT305X_ESW_PCR0_WT_DONE))
> +#else
> +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
> +                     RT305X_ESW_PCR1_WT_DONE))
> +#endif

same as above.

>                         break;
>
>                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
> diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
> index 00f1a0e7e6..19f0dacaa5 100644
> --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
> +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
> @@ -294,6 +294,7 @@ enum fe_work_flag {
>  #define FE_PDMA_SIZE_4DWORDS   (0 << 4)
>  #define FE_PDMA_SIZE_8DWORDS   (1 << 4)
>  #define FE_PDMA_SIZE_16DWORDS  (2 << 4)
> +#define FE_PDMA_SIZE_32DWORDS  (3 << 4)
>
>  #define FE_US_CYC_CNT_MASK     0xff
>  #define FE_US_CYC_CNT_SHIFT    0x8
> diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt6855a.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt6855a.c
> new file mode 100644
> index 0000000000..3e883713eb
> --- /dev/null
> +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt6855a.c
> @@ -0,0 +1,102 @@
> +/*   This program is free software; you can redistribute it and/or modify
> + *   it under the terms of the GNU General Public License as published by
> + *   the Free Software Foundation; version 2 of the License
> + *
> + *   This program is distributed in the hope that it will be useful,
> + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *   GNU General Public License for more details.
> + *
> + *   Copyright (C) 2009-2015 John Crispin <blogic at openwrt.org>
> + *   Copyright (C) 2009-2015 Felix Fietkau <nbd at nbd.name>
> + *   Copyright (C) 2013-2015 Michael Lee <igvtee at gmail.com>
> + */
> +
> +#include <linux/module.h>
> +
> +#include <asm/mach-ralink/ralink_regs.h>
> +
> +#include "mtk_eth_soc.h"
> +#include "mdio_rt2880.h"
> +
> +static const u16 rt5350_reg_table[FE_REG_COUNT] = {
> +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,    // OK
> +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,    // RST_IDX
> +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,      // OK
> +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
> +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
> +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
> +       [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
> +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
> +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
> +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
> +       [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
> +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,  // OK
> +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,  // OK
> +       [FE_REG_FE_RST_GL] = 0,
> +       [FE_REG_FE_DMA_VID_BASE] = 0,
> +};
> +
> +static void rt5350_init_data(struct fe_soc_data *data,

Rename these functions with a rt6855a_ prefix instead.

-- 
Regards,
Chuanhong Guo