[OpenWrt-Devel] Pre UBoot initiliation required to get MDIO working.

[sven falempin]

To anyone with DTS and qcom MDIO/ESS knowledge,
please help, you are my only hope.

Using an QCOM ap.dk04.1-c1 / ipq4019 device,
I ran into an initialization problem for MDIO driver.

The problem only appeared when I started booting from the device,
because executing 'dhcp' in uboot , do some initialization that fix the problem.

I m running openWRT current, 4.19 kernel with 5.3-rc4 wireless code
and a few other patches, ( openwrt r10985-4364dd244c ) , and minor
tweaks.

Also , to run IPQ4019 and ESS, which kernel offer the better driver
support right now ?
4.14 ? 4.19 ? 5.3 ? 3.x is not possible. (regarding Voltage regulator
and RTC for example )

Nevertheless I am not sure if my DTS file could also be a source or trouble;
My DTS contains :
/*          */
   mdio_pins: mdio_pinmux {
    mux_1 {
     pins = "gpio6";
     function = "mdio"; // ipq4019-pinctrl 1000000.pinctrl: invalid
function mdio0 in map table
     bias-pull-up;
    };
    mux_2 {
     pins = "gpio7";
     function = "mdc";
     bias-pull-up;
    };
   };
/*          */
  tcsr: tcsr at 194b000 {
   status = "ok";
  };
  ess-switch at c000000 {
   status = "okay";
  };
/* */

  mdio at 90000 {
   status = "ok";
   pinctrl-0 = <&mdio_pins>;
   pinctrl-names = "default";
   phy-reset-gpio = <&tlmm 47 0>;
   status = "ok";
   bias-disable;
  };

/ * */

In the uboot vendor, the DHCP  'init' the ess, and enable the kernel
to detect the ethernet phy:
( only two are wired , and i only tested eth1 because it s the only
one that matters for now )

        u32 data;
        ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x3e3e3e);
        /*
         * configure Speed, Duplex.
         */
        ipq40xx_ess_sw_wr(S17_P0STATUS_REG, S17_PORT_SPEED(2) |
                                        S17_PORT_FULL_DUP |
                                        S17_TX_FLOW_EN |
                                        S17_RX_FLOW_EN);

        ipq40xx_ess_sw_wr(S17_P0LOOKUP_CTRL_REG, 0x140000);
        ipq40xx_ess_sw_wr(S17_P1LOOKUP_CTRL_REG, 0x140000);
        ipq40xx_ess_sw_wr(S17_P2LOOKUP_CTRL_REG, 0x140000);
        ipq40xx_ess_sw_wr(S17_P3LOOKUP_CTRL_REG, 0x140000);
        ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x140000);
        ipq40xx_ess_sw_wr(S17_P5LOOKUP_CTRL_REG, 0x140000);
        /*
        * HOL setting for Port0
        */
        ipq40xx_ess_sw_wr(S17_PORT0_HOL_CTRL0, 0x1e444444);
        ipq40xx_ess_sw_wr(S17_PORT0_HOL_CTRL1, 0x1c6);
        /*
        * HOL setting for Port1
        */
        ipq40xx_ess_sw_wr(S17_PORT1_HOL_CTRL0, 0x1e004444);
        ipq40xx_ess_sw_wr(S17_PORT1_HOL_CTRL1, 0x1c6);
        /*
        * HOL setting for Port2
        */
        ipq40xx_ess_sw_wr(S17_PORT2_HOL_CTRL0, 0x1e004444);
        ipq40xx_ess_sw_wr(S17_PORT2_HOL_CTRL1, 0x1c6);
        /*
        * HOL setting for Port3
        */
        ipq40xx_ess_sw_wr(S17_PORT3_HOL_CTRL0, 0x1e004444);
        ipq40xx_ess_sw_wr(S17_PORT3_HOL_CTRL1, 0x1c6);
        /*
        * HOL setting for Port4
        */
        ipq40xx_ess_sw_wr(S17_PORT4_HOL_CTRL0, 0x1e004444);
        ipq40xx_ess_sw_wr(S17_PORT4_HOL_CTRL1, 0x1c6);
        /*
        * HOL setting for Port5
        */
        ipq40xx_ess_sw_wr(S17_PORT5_HOL_CTRL0, 0x1e444444);
        ipq40xx_ess_sw_wr(S17_PORT5_HOL_CTRL1, 0x1c6);
        break;

        mdelay(1);
        /*
         * Enable Rx and Tx mac. // this one ?
         */
        ipq40xx_ess_sw_rd(S17_P0STATUS_REG, &data);
        ipq40xx_ess_sw_wr(S17_P0STATUS_REG, data |
                                S17_PORT_TX_MAC_EN |
                                S17_PORT_RX_MAC_EN);
        ipq40xx_ess_sw_rd(ESS_MIB_OFFSET, &data);
        ipq40xx_ess_sw_wr(ESS_MIB_OFFSET, data |
                                        ESS_MIB_EN);
        ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x7f7f7f);


Is there missing pieces in the MDIO / ESS driver , or can it be the DTS file ?


Best.


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