[OpenWrt-Devel] [PATCH 1/2] ath79: fix qca955x pcie0 memory size
Philippe Mathieu-Daudé
f4bug at amsat.org
Fri Feb 1 11:32:14 EST 2019
On 2/1/19 4:01 PM, Chuanhong Guo wrote:
> Hi!
>
> On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé <f4bug at amsat.org> wrote:
>> [...]
>> Now that you pointed this line, I am not sure it is correct...
>> It maps I/O (0x01000000) region of 1B (0 0x000001) from PCI 0x00000000
>> (0 0x00000000) at 0x0000000 (0x0000000) into cpu space.
>> But the DDR is already mapped at 0x0000000 in cpu address space...
>> Am I missing something?
> The atheros PCIE controller doesn't have an IO space at all. (at least
> the documentation doesn't mention it.)
> I'm not sure if it's possible to write a PCIE driver without IO space.
Yes we can.
> I guess the existing code just uses 1 byte of system memory as a
> placeholder.
OK, so we can clearly get ride of that space then :)
Cc'ing John who introduced the QCA in 53c474abbd.
SAn: Can you test this snippet on your board and resend a patch?
-- >8 --
--- a/target/linux/ath79/dts/qca9557.dtsi
+++ b/target/linux/ath79/dts/qca9557.dtsi
@@ -187,6 +187,5 @@
<0x14000000 0x1000>; /* CFG */
reg-names = "crp_base", "ctrl_base",
"cfg_base";
- ranges = <0x2000000 0 0x10000000
0x10000000 0 0x04000000 /* pci memory */
- 0x1000000 0 0x00000000
0x0000000 0 0x000001>; /* io space */
+ ranges = <0x02000000 0 0x10000000
0x10000000 0 0x02000000>;
interrupt-parent = <&intc2>;
interrupts = <1>;
@@ -209,6 +208,5 @@
<0x16000000 0x1000>; /* CFG */
reg-names = "crp_base", "ctrl_base",
"cfg_base";
- ranges = <0x2000000 0 0x12000000
0x12000000 0 0x02000000 /* pci memory */
- 0x1000000 0 0x00000000
0x0000000 0 0x000001>; /* io space */
+ ranges = <0x02000000 0 0x12000000
0x12000000 0 0x02000000>;
interrupt-parent = <&intc3>;
interrupts = <0>;
---
Regards,
Phil.
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