[OpenWrt-Devel] [PATCH 2/3] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions

[Ram Chandra Jangir]

Signed-off-by: Ram Chandra Jangir <rjangir at codeaurora.org>
---
 ...ctrl-Fixed-missing-RGMII-pincontrol-defin.patch | 54 ++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 target/linux/ipq806x/patches-4.14/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch

diff --git a/target/linux/ipq806x/patches-4.14/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch b/target/linux/ipq806x/patches-4.14/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
new file mode 100644
index 0000000..2add6d3
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.14/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
@@ -0,0 +1,54 @@
+From a3488aa9bed37c56e405967d44e821c484b5d6b9 Mon Sep 17 00:00:00 2001
+From: Ram Chandra Jangir <rjangir at codeaurora.org>
+Date: Fri, 28 Sep 2018 15:19:50 +0530
+Subject: [PATCH] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
+
+Signed-off-by: Ram Chandra Jangir <rjangir at codeaurora.org>
+---
+ drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+index bcb29c0..30b7809 100644
+--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
++++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+@@ -308,7 +308,7 @@ enum ipq8064_functions {
+ };
+
+ static const char * const mdio_groups[] = {
+-	"gpio0", "gpio1", "gpio10", "gpio11",
++	"gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
+ };
+
+ static const char * const mi2s_groups[] = {
+@@ -412,8 +412,8 @@ enum ipq8064_functions {
+ };
+
+ static const char * const rgmii2_groups[] = {
+-	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
+-	"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
++	"gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
++	"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
+ };
+
+ static const char * const sata_groups[] = {
+@@ -548,7 +548,7 @@ enum ipq8064_functions {
+ static const struct msm_pingroup ipq8064_groups[] = {
+	PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+-	PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++	PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
+@@ -612,7 +612,7 @@ enum ipq8064_functions {
+	PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+-	PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++	PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
+--
+1.9.1
-- 
1.9.1


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