[OpenWrt-Devel] lantiq DSL drivers / firmware info
Sylwester Petela
sscapi at gmail.com
Mon Jul 10 14:10:44 EDT 2017
These are some findings that I've along with Mathias Kresin made quite
time ago (hardware part):
On F3 vs F1 near transformer was capacitor .022j630p (annex B) .027j630p
(annex A) You can check that as on most images I don't see its value. As
for differences between boards I'll check it tomorrow when I replace F3
with HH5 (need to flash it first).
After all in my case stats between F1 and F3 at annexA are ~0,5dB, upload
sync is bit higher compared to when I was on F1 and HH5 as far as I
checked, download is same.
W dniu 2015-10-06 o 19:22, Mathias Kresin pisze:
> Hi Sylwester,
>
> the soldering on my HomeHub5a was done and I'm able to establish an
> Annex B ADSL connection with the device.
>
> The line stats are okay, but they do not match the values I had with
> the o2 Box 6431 before ripping of the Line Transformer. To confirm
> that nothing has changed with the phone line, I connected a VRX208
> based FritzBox (with the same xDSL Firmware Version) and I got the
> same values as with the o2 Box 6431.
>
> o2 Box 6431:
>
> Data Rate: Down: 17.296 Mb/s / Up:
> 1.180 Mb/s
> Line Attenuation (LATN): Down: 17.2dB / Up: 6.7dB
> Signal Attenuation (SATN): Down: 15.9dB / Up: 6.6dB
> Noise Margin (SNR): Down: 6.0dB / Up: 12.3dB
> Aggregate Transmit Power(ACTATP): Down: 18.2dB / Up: 11.1dB
> Max. Attainable Data Rate (ATTNDR): Down: 17.284 Mb/s / Up:
> 1.392 Mb/s
>
> HomeHub 5a @ Annex B:
>
> Data Rate: Down: 16.889 Mb/s / Up:
> 1.180 Mb/s
> Line Attenuation (LATN): Down: 14.6dB / Up: 7.1dB
> Signal Attenuation (SATN): Down: 13.4dB / Up: 7.1dB
> Noise Margin (SNR): Down: 6.3dB / Up: 12.5dB
> Aggregate Transmit Power(ACTATP): Down: 18.2dB / Up: 12.6dB
> Max. Attainable Data Rate (ATTNDR): Down: 17.016 Mb/s / Up:
> 1.356 Mb/s
>
> I had the impression that we still missed something. And yes, I was
> able to identify a few more different resistors (Line Transformer Pin
> counting is clockwise!):
>
> Annex A
> Line Transformer Pin 6 -> 24,95 Ohm R left -> empty solder pads
> -> VRX 208 Pin 37
> Line Transformer Pin 7 -> 24,95 Ohm R right -> empty solder pads
> -> VRX 208 Pin 45
>
> Line Transformer Pin 5 -> 68 Ohm R -> VRX 208 Pin 39
> Line Transformer Pin 8 -> 68 Ohm R -> VRX 208 Pin 43
>
> Annex B
> Line Transformer Pin 6 -> 10 Ohm R left -> 68 Ohm R -> VRX 208
> Pin 37
> Line Transformer Pin 7 -> 10 Ohm R right -> 68 Ohm R -> VRX 208
> Pin 45
>
> Line Transformer Pin 5 -> 0 Ohm R (bridge) between VRX 208 Pin
> 39/43 -> 0 Ohm R (bridge) -> VRX 208 Pin 39
> Line Transformer Pin 8 -> 0 Ohm R (bridge) between VRX 208 Pin
> 39/43 -> 0 Ohm R (bridge) -> VRX 208 Pin 43
What I see on F1, yes traces from inner pair of transformer goes through
49 ohm (between them) and then goes straight to (right resistor /cap
80/79pin) and somewhere else (cannot trace it) Outer pair goes straight
to ~70 ohm resistors each to somewhere under the vrx208 chip (need to
de-solder it to find out pins) and to (left/middle cap/resistor) 78/77
and 76/75.
> I used the following pictures for visualising and flowing the traces.
> The pictures are in the gimp format and have multiple layers:
>
> TD-W8980 - Annex A:
> https://www.dropbox.com/s/j6qoeoy1a479yrz/tp-link_w8980v1.xcf?dl=0
> o2 Box 6431 - Annex B:
> https://www.dropbox.com/s/jskzcnxvszdlraj/o2_6431.xcf?dl=0
>
>
> Can you confirm my findings with your devices?
>
> Do your line stats differ between your HH5 and your F3 at AnnexA as well?
>
>
> I could not yet identify all matching R's/solder pads on the HH5,
> since the HH5 board layout is way to different and hard to read. I'll
> try again later, when my eyes are rested.
>
> Mathias
As for F3 traces, I'll send You them tomorow.
Best Regards
Sylwester Petela
------End of QUOTE------
W dniu 10.07.2017 o 14:23, Damian Kaczkowski pisze:
> Hello all.
>
> I have done some research regarding soft-switching DSL Annex. I got
> few boards which are able to operate in Annex A or B without hardware
> mods of the hybrid. Seems that dsl_control is able to send some
> commands to the DSL PHY so it can sync with Annex A line while being
> equipped with Annex B DSL transformer which is a part of hybrid I
> suppose. I have tested the following boards:
> - AVM/1&1 FRITZ!Box 7330 SL
> - AVM/1&1 FRITZ!Box 7362 SL
> - AVM/1&1 FRITZ!Box Fon WLAN 7320
> - AVM/1&1 FRITZ!Box Fon WLAN 7360 SL
> - AVM FRITZ!Box WLAN 3370
>
> Non of them is "international edition". All are marked by vendor as
> Annex B only editions and all of them are equipped with DSL
> transformers matched to Lantiq Chips Annex B (that's what datasheets
> says).
>
> They are equipped with the following DSL transformers:
> UMEC UTB01930S 270uH, 2:1, Annex B, Supplementary For Lantiq’s
> XWAY™ VRX208 Chip (3370)
> LinkCom LAL0530 270uH, 2:1, Annex B, Supplementary For Lantiq’s
> XWAY™ VRX208 Chip (7362 SL, 7360 SL)
> VOGT unknown, unknown, Annex B, Suplementary
> for Lantiq AR9 Chip (7320, 7330 SL)
> MNC EP-832SG 1.4mH, 2:1, Annex A, Supplementary For Lantiq’s
> XWAY™ VRX208 Chip (TD-W8970V1, TD-W8980V1, TD-W9980V1)
> MNC EP-833SG 270uH, 2:1, Annex B, Supplementary For Lantiq’s
> XWAY™ VRX208 Chip (TD-W8970BV1, TD-W8980BV1, TD-W9980BV1)
>
> On Freetz firmware I was able to soft-switch all above AVM boards from
> Annex B to Annex A and successfully sync to Annex A/M DSLAM/Line.
>
> After switching firmware to LEDE/OpenWrt on those boards I am getting
> the same error as Andre got on TP-LINKs:
> 'DSL_CPE: Wrong combination of DSL PHY Firmware and hybrid type used!
> Please change one of it.'.
>
> To sum up:
> Freetz OS loaded with LEDE DSL firmware sync without a problem. So the
> problem is not the DSL firmware itself.
> Hybrid is also not a problem cause on Freetz OS I have successfully
> sync Annex B boards (soft-switched to Annex A) to Annex A line.
>
> I have done numerous tests and come to conclusion that dsl_control
> and/or driver implementation is the main problem and thing to focus
> on.
>
> LEDE dsl_control is not able to start the DSL PHYs (with Annex B
> transformers) loaded with Annex A firmware and sync them to Annex A
> line, but the same boards sync fine with Freetz OS + Freetz
> dsl_control.
>
> I spot that dsl_control on Freetz generates the adsl.cfg upon start.
> This adsl.cfg is generated with different sets of commands according
> to selected Annex.
>
> adsl.cfg content differs between board models/generation. Similar
> boards got the same adsl.cfg contents. This is probably due to
> different DSL transformer or whole hybrid? I need to double check and
> confirm this to be sure.
>
> Here is an example of adsl.cfg file content generated on 7320 SL board:
> For Annex B:
> #AVM ADSL Annex B, generated by dsl_control
> [WaitForConfiguration]={
> sics 1 1 1 3
> }
> [WaitForLinkActivate]={
> lfcs 1 1 1 1 0 0
> }
> [WaitForLinkActivate]={
> lfcs 0 1 1 0 0 0
> }
> [WaitForLinkActivate]={
> cw info 86 0 0x4801
> }
> [WaitForLinkActivate]={
> avmcrmw optn 25 0 0x2000
> }
> [WaitForLinkActivate]={
> cw cnfg 45 0 0xe
> }
> [WaitForLinkActivate]={
> avmcrmw info 103 1 0x2000
> }
>
> For Annex A:
> #AVM ADSL Annex A, generated by dsl_control
> [WaitForConfiguration]={
> sics 1 1 1 3
> }
> [WaitForLinkActivate]={
> lfcs 1 1 1 1 0 0
> }
> [WaitForLinkActivate]={
> lfcs 0 1 1 0 0 0
> }
> [WaitForLinkActivate]={
> cw info 86 0 0x4801
> }
> [WaitForLinkActivate]={
> avmcrmw optn 25 0 0x2000
> }
> [WaitForLinkActivate]={
> cw cnfg 45 0 0xe
> }
> [WaitForLinkActivate]={
> cw info 94 0 0x1467
> }
>
>
> Here is an example of adsl.cfg file content generated on 3370 board:
> For Annex B:
> #AVM ADSL Annex B
> [WaitForLinkActivate]={
> avmcrms info 103 1 0x2000
> }
> [WaitForLinkActivate]={
> avmcrmr info 111 8 0010
> }
> [WaitForLinkActivate]={
> avmcrms test 0 0 0x4000
> }
> [WaitForLinkActivate]={
> avmcrms dsl 13 0 0x0002
> }
> [WaitForLinkActivate]={
> avmcw cnfg 46 0 0xe
> }
> [WaitForLinkActivate]={
> avmcrms info 111 8 0x0004
> }
> [WaitForLinkActivate]={
> avmcrms dsl 13 0 0x0008
> }
>
> For Annex A:
> #AVM ADSL Annex A
> [WaitForLinkActivate]={
> avmcrmr info 111 8 0010
> }
> [WaitForLinkActivate]={
> avmcrms test 0 0 0x4000
> }
> [WaitForLinkActivate]={
> avmcrms dsl 13 0 0x0002
> }
> [WaitForLinkActivate]={
> avmcw cnfg 46 0 0xe
> }
> [WaitForLinkActivate]={
> avmcw moni 5 0 0x204B
> }
> [WaitForLinkActivate]={
> avmcw moni 5 1 0x0000
> }
> [WaitForLinkActivate]={
> avmcrms info 111 8 0x0004
> }
> [WaitForLinkActivate]={
> avmcrms dsl 13 0 0x0008
> }
>
>
> As you can see there are some AVM and non standard commands comparing
> to LEDE/OpenWrt dsl_control flavour. Those are for eg.:
> avmvig AVM_VersionInformationGet
> avmcr AVM_CmvRead
> avmcw AVM_CmvWrite
> avmcrms AVM_CmvReadModifySet
> avmcrmr AVM_CmvReadModifyReset
> avmpet AVM_ProdEchoTest
> avmhwrfit AVM_HWRFITest
> avmdsmmcs AVM_DSM_MacConfigSet
> cr CmvRead
> cw CmvWrite
>
>
> More can be found by looking into dsl_control file extracted from AVM
> boards firmwares (Freetz buildroot can do that).
> It also contains adsl.cfg commands if someone wants to debug this
> further without access to the boards itself.
>
> Example content of dsl_control:
> avm_dsl_cli_DsmMacConfigSet
> cw DSL_CPE_SCRIPT: CMV WR %s %d %d, value=0x%04x, retCode=%d
> mw %s %s %s DSL_CPE_SCRIPT: Dbg Memory write address=%08x,
> value=%04x, retCode=%d
> dsl_control: mw %08x fail
> mr dsl_control: error:mr parameter type mismatch!
>
>
>
> Anyone got an idea or could spare a hint on how to debug what AVMs
> dsl_control is actually doing/sending to the DSL PHY driver?
>
> Could anyone with deep Lantiq knowledge look into this please? My
> knowledge about Lantiq DSL tools/drivers ends here : (.
>
> What needs to be done so the LEDE/OpenWrt dsl_control could also be
> able to switch Annex on those and maybe other AR9/VR9 boards?
>
>
> I can assist in some tests if you need. I also got all TP-Links VR9
> boards (both Annexes) plus some other AR9/VR9/AR10 boards and also an
> Annex A/M ADSL/ADSL2+ DSLAMs (can't test VDSL right now).
>
>
> Greets.
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel at lists.openwrt.org
> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
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