[OpenWrt-Devel] [PATCH] mpc85xx: Add PTP node for TL-WD4900 in device tree

[Wojciech Dubowik]

PTP requires at least one timer to be 1PPS so describe it.
For testing, load kernel module gianfar_ptp and use ptp4l
from linuxptp.

Copied from FSL P1010RDB reference design.

Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik at neratec.com>
---
 .../mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts   | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
index 0d79dc0..2325006 100644
--- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
@@ -145,6 +145,19 @@
 		can1: can at 1d000 {
 			status = "disabled";
 		};
+
+		ptp_clock at b0e00 {
+			compatible = "fsl,etsec-ptp";
+			reg = <0xb0e00 0xb0>;
+			interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
+			fsl,cksel       = <1>;
+			fsl,tclk-period	= <5>;
+			fsl,tmr-prsc	= <2>;
+			fsl,tmr-add	= <0xcccccccd>;
+			fsl,tmr-fiper1	= <0x3b9ac9fb>; /* 1PPS */
+			fsl,tmr-fiper2	= <0x00018696>;
+			fsl,max-adj	= <249999999>;
+		};
 	};
 
 	pci0: pcie at ffe09000 {
-- 
1.9.1
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