[OpenWrt-Devel] [PATCH v2] lantiq: add phy led config support over devicetree bindings
John Crispin
blogic at openwrt.org
Sat Nov 21 14:14:05 EST 2015
On 21/11/2015 20:09, Florian Eckert wrote:
> Hallo,
>
> if you mean "CONFIG_OF_MDIO"? I have added this define because if we
> have no "openfirmware" a dummy function will be called. Or do you mean
> the whole patch?
>
> Regards
>
> Flo
ah i misread it and did not see the OF_ part. fine in this case
John
>
> Am 21.11.2015 6:55 nachm. schrieb "John Crispin" <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>:
>>
>> Hi
>>
>> 1 comment inline
>>
>> On 09/11/2015 13:44, Florian Eckert wrote:
>> > This patch adds the posibility to config the led behaviour of the
> lantiq phys
>> > over the devicetree bindings.It patches the
> 0023-NET-PHY-adds-driver-for-lantiq-PHY11G
>> > for 3.18 and 4.1. I have also added a register description overview for
>> > applicable values. This goes to the documentation folder in the
> linux kernel.
>> >
>> > Signed-off-by: Florian Eckert <Eckert.Florian at googlemail.com
> <mailto:Eckert.Florian at googlemail.com>>
>> > ---
>> >
>> > v2 add Signed-off-by marker
>> >
>> > ...023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch | 268
> ++++++++++++++++++++-
>> > ...023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch | 268
> ++++++++++++++++++++-
>> > 2 files changed, 534 insertions(+), 2 deletions(-)
>> > mode change 100644 => 100755
> target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
>> >
>> > diff --git
> a/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
> b/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
>> > old mode 100644
>> > new mode 100755
>> > index 6d1805f..55db4c7
>> > ---
> a/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
>> > +++
> b/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
>> > @@ -37,7 +37,7 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > obj-$(CONFIG_AT803X_PHY) += at803x.o
>> > --- /dev/null
>> > +++ b/drivers/net/phy/lantiq.c
>> > -@@ -0,0 +1,231 @@
>> > +@@ -0,0 +1,278 @@
>> > +/*
>> > + * This program is free software; you can redistribute it and/or
> modify
>> > + * it under the terms of the GNU General Public License as
> published by
>> > @@ -58,6 +58,7 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > +
>> > +#include <linux/module.h>
>> > +#include <linux/phy.h>
>> > ++#include <linux/of.h>
>> > +
>> > +#define MII_MMDCTRL 0x0d
>> > +#define MII_MMDDATA 0x0e
>> > @@ -104,6 +105,50 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > + return 0;
>> > +}
>> > +
>> > ++#if IS_ENABLED(CONFIG_OF_MDIO)
>>
>> we are inside a phy driver here that we talk to using a mdio bus. are
>> you sure this is required ?
>>
>> John
>>
>> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
>> > ++{
>> > ++ u32 tmp;
>> > ++
>> > ++ /* store the led values if one was passed by the devicetree */
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledch",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e0, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledcl",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e1, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e2, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e3, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e4, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e5, tmp);
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e6, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e7, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e8, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e9, tmp);
>> > ++
>> > ++ return 0;
>> > ++}
>> > ++#else
>> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
>> > ++{
>> > ++ return 0;
>> > ++}
>> > ++#endif /* CONFIG_OF_MDIO */
>> > ++
>> > +static int vr9_gphy_config_init(struct phy_device *phydev)
>> > +{
>> > + int err;
>> > @@ -129,6 +174,8 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > + vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
>> > + vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
>> > +
>> > ++ vr9_gphy_of_reg_init(phydev);
>> > ++
>> > + return 0;
>> > +}
>> > +
>> > @@ -269,3 +316,222 @@ Signed-off-by: John Crispin
> <blogic at openwrt.org <mailto:blogic at openwrt.org>>
>> > +MODULE_DESCRIPTION("Lantiq PHY drivers");
>> > +MODULE_AUTHOR("Daniel Schwierzeck
> <daniel.schwierzeck at googlemail.com
> <mailto:daniel.schwierzeck at googlemail.com>>");
>> > +MODULE_LICENSE("GPL");
>> > +--- /dev/null
>> > ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
>> > +@@ -0,0 +1,216 @@
>> > ++Lanitq PHY binding
>> > ++============================================
>> > ++
>> > ++This devicetree binding controls the lantiq ethernet phys led
> functionality.
>> > ++
>> > ++Example:
>> > ++ mdio at 0 {
>> > ++ #address-cells = <1>;
>> > ++ #size-cells = <0>;
>> > ++ compatible = "lantiq,xrx200-mdio";
>> > ++ phy5: ethernet-phy at 5 {
>> > ++ reg = <0x1>;
>> > ++ compatible = "lantiq,phy11g",
> "ethernet-phy-ieee802.3-c22";
>> > ++ };
>> > ++ phy11: ethernet-phy at 11 {
>> > ++ reg = <0x11>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led2h = <0x00>;
>> > ++ lantiq,led2l = <0x03>;
>> > ++ };
>> > ++ phy12: ethernet-phy at 12 {
>> > ++ reg = <0x12>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led1h = <0x00>;
>> > ++ lantiq,led1l = <0x03>;
>> > ++ };
>> > ++ phy13: ethernet-phy at 13 {
>> > ++ reg = <0x13>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led2h = <0x00>;
>> > ++ lantiq,led2l = <0x03>;
>> > ++ };
>> > ++ phy14: ethernet-phy at 14 {
>> > ++ reg = <0x14>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led1h = <0x00>;
>> > ++ lantiq,led1l = <0x03>;
>> > ++ };
>> > ++ };
>> > ++
>> > ++Register Description
>> > ++============================================
>> > ++
>> > ++LEDCH:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LEDCH 0x00C5
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++| FBF | SBF |RES | NACS |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++FBC 7:6 RW Fast Blink Frequency
>> > ++ ---
>> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency
>> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency
>> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency
>> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency
>> > ++
>> > ++SBF 5:4 RW Slow Blink Frequency
>> > ++ ---
>> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency
>> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency
>> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency
>> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency
>> > ++
>> > ++NACS 2:0 RW Inverse of Scan Function
>> > ++ ---
>> > ++ 0x0 (000b) NONE No Function
>> > ++ 0x1 (001b) LINK Complex function enabled when
> link is up
>> > ++ 0x2 (010b) PDOWN Complex function enabled when
> device is powered-down
>> > ++ 0x3 (011b) EEE Complex function enabled when
> device is in EEE mode
>> > ++ 0x4 (100b) ANEG Complex function enabled when
> auto-negotiation is running
>> > ++ 0x5 (101b) ABIST Complex function enabled when
> analog self-test is running
>> > ++ 0x6 (110b) CDIAG Complex function enabled when
> cable diagnostics are running
>> > ++ 0x7 (111b) TEST Complex function enabled when
> test mode is running
>> > ++
>> > ++LEDCL:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LEDCL 0x0067
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++|RES | SCAN |RES | CBLINK |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++SCAN 6:4 RW Complex Scan Configuration
>> > ++ ---
>> > ++ 000 B NONE No Function
>> > ++ 001 B LINK Complex function enabled when link
> is up
>> > ++ 010 B PDOWN Complex function enabled when
> device is powered-down
>> > ++ 011 B EEE Complex function enabled when device
> is in EEE mode
>> > ++ 100 B ANEG Complex function enabled when
> auto-negotiation is running
>> > ++ 101 B ABIST Complex function enabled when
> analog self-test is running
>> > ++ 110 B CDIAG Complex function enabled when
> cable diagnostics are running
>> > ++ 111 B TEST Complex function enabled when test
> mode is running
>> > ++
>> > ++CBLINK 2:0 RW Complex Blinking Configuration
>> > ++ ---
>> > ++ 000 B NONE No Function
>> > ++ 001 B LINK Complex function enabled when link
> is up
>> > ++ 010 B PDOWN Complex function enabled when
> device is powered-down
>> > ++ 011 B EEE Complex function enabled when device
> is in EEE mode
>> > ++ 100 B ANEG Complex function enabled when
> auto-negotiation is running
>> > ++ 101 B ABIST Complex function enabled when
> analog self-test is running
>> > ++ 110 B CDIAG Complex function enabled when
> cable diagnostics are running
>> > ++ 111 B TEST Complex function enabled when test
> mode is running
>> > ++
>> > ++LEDxH:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LED0H 0x0070
>> > ++LED1H 0x0020
>> > ++LED2H 0x0040
>> > ++LED3H 0x0040
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++| CON | BLINKF |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++CON 7:4 RW Constant On Configuration
>> > ++ ---
>> > ++ 0x0 (0000b) NONE LED does not light up constantly
>> > ++ 0x1 (0001b) LINK10 LED is on when link is 10
> Mbit/s
>> > ++ 0x2 (0010b) LINK100 LED is on when link is 100
> Mbit/s
>> > ++ 0x3 (0011b) LINK10X LED is on when link is
> 10/100 Mbit/s
>> > ++ 0x4 (0100b) LINK1000 LED is on when link is
> 1000 Mbit/s
>> > ++ 0x5 (0101b) LINK10_0 LED is on when link is
> 10/1000 Mbit/s
>> > ++ 0x6 (0110b) LINK100X LED is on when link is
> 100/1000 Mbit/s
>> > ++ 0x7 (0111b) LINK10XX LED is on when link is
> 10/100/1000 Mbit/s
>> > ++ 0x8 (1000b) PDOWN LED is on when device is
> powered-down
>> > ++ 0x9 (1001b) EEE LED is on when device is in
> EEE mode
>> > ++ 0xA (1010b) ANEG LED is on when
> auto-negotiation is running
>> > ++ 0xB (1011b) ABIST LED is on when analog
> self-test is running
>> > ++ 0xC (1100b) CDIAG LED is on when cable
> diagnostics are running
>> > ++
>> > ++BLINKF 3:0 RW Fast Blinking Configuration
>> > ++ ---
>> > ++ 0x0 (0000b) NONE No Blinking
>> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
>> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
>> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100
> Mbit/s
>> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000
> Mbit/s
>> > ++ 0x5 (0101b) LINK10_0 Blink when link is
> 10/1000 Mbit/s
>> > ++ 0x6 (0110b) LINK100X Blink when link is
> 100/1000 Mbit/s
>> > ++ 0x7 (0111b) LINK10XX Blink when link is
> 10/100/1000 Mbit/s
>> > ++ 0x8 (1000b) PDOWN Blink when device is
> powered-down
>> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode
>> > ++ 0xA (1010b) ANEG Blink when auto-negotiation
> is running
>> > ++ 0xB (1011b) ABIST Blink when analog self-test
> is running
>> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics
> are running
>> > ++
>> > ++LEDxL:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LED0L 0x0003
>> > ++LED1L 0x0000
>> > ++LED2L 0x0000
>> > ++LED3L 0x0020
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++| BLINKS | PULSE |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++BLINKS 7:4 RW Slow Blinkin Configuration
>> > ++ ---
>> > ++ 0x0 (0000b) NONE No Blinking
>> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
>> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
>> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100
> Mbit/s
>> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000
> Mbit/s
>> > ++ 0x5 (0101b) LINK10_0 Blink when link is
> 10/1000 Mbit/s
>> > ++ 0x6 (0110b) LINK100X Blink when link is
> 100/1000 Mbit/s
>> > ++ 0x7 (0111b) LINK10XX Blink when link is
> 10/100/1000 Mbit/s
>> > ++ 0x8 (1000b) PDOWN Blink when device is
> powered-down
>> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode
>> > ++ 0xA (1010b) ANEG Blink when auto-negotiation
> is running
>> > ++ 0xB (1011b) ABIST Blink when analog self-test
> is running
>> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics
> are runningning
>> > ++
>> > ++PULSE 3:0 RW Pulsing Configuration
>> > ++ The pulse field is a mask field by which
> certain events can be combined
>> > ++ ---
>> > ++ 0x0 (0000b) NONE No pulsing
>> > ++ 0x1 (0001b) TXACT Transmit activity
>> > ++ 0x2 (0010b) RXACT Receive activity
>> > ++ 0x4 (0100b) COL Collision
>> > ++ 0x8 (1000b) RES Reserved
>> > diff --git
> a/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
> b/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
>> > index 08e6b64..3f50a3b 100644
>> > ---
> a/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
>> > +++
> b/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
>> > @@ -37,7 +37,7 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > obj-$(CONFIG_AT803X_PHY) += at803x.o
>> > --- /dev/null
>> > +++ b/drivers/net/phy/lantiq.c
>> > -@@ -0,0 +1,231 @@
>> > +@@ -0,0 +1,278 @@
>> > +/*
>> > + * This program is free software; you can redistribute it and/or
> modify
>> > + * it under the terms of the GNU General Public License as
> published by
>> > @@ -58,6 +58,7 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > +
>> > +#include <linux/module.h>
>> > +#include <linux/phy.h>
>> > ++#include <linux/of.h>
>> > +
>> > +#define MII_MMDCTRL 0x0d
>> > +#define MII_MMDDATA 0x0e
>> > @@ -104,6 +105,50 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > + return 0;
>> > +}
>> > +
>> > ++#if IS_ENABLED(CONFIG_OF_MDIO)
>> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
>> > ++{
>> > ++ u32 tmp;
>> > ++
>> > ++ /* store the led values if one was passed by the devicetree */
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledch",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e0, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledcl",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e1, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e2, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e3, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e4, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e5, tmp);
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e6, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e7, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3h",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e8, tmp);
>> > ++
>> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3l",
> &tmp))
>> > ++ vr9_gphy_mmd_write(phydev, 0x1e9, tmp);
>> > ++
>> > ++ return 0;
>> > ++}
>> > ++#else
>> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
>> > ++{
>> > ++ return 0;
>> > ++}
>> > ++#endif /* CONFIG_OF_MDIO */
>> > ++
>> > +static int vr9_gphy_config_init(struct phy_device *phydev)
>> > +{
>> > + int err;
>> > @@ -129,6 +174,8 @@ Signed-off-by: John Crispin <blogic at openwrt.org
> <mailto:blogic at openwrt.org>>
>> > + vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
>> > + vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
>> > +
>> > ++ vr9_gphy_of_reg_init(phydev);
>> > ++
>> > + return 0;
>> > +}
>> > +
>> > @@ -269,3 +316,222 @@ Signed-off-by: John Crispin
> <blogic at openwrt.org <mailto:blogic at openwrt.org>>
>> > +MODULE_DESCRIPTION("Lantiq PHY drivers");
>> > +MODULE_AUTHOR("Daniel Schwierzeck
> <daniel.schwierzeck at googlemail.com
> <mailto:daniel.schwierzeck at googlemail.com>>");
>> > +MODULE_LICENSE("GPL");
>> > +--- /dev/null
>> > ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
>> > +@@ -0,0 +1,216 @@
>> > ++Lanitq PHY binding
>> > ++============================================
>> > ++
>> > ++This devicetree binding controls the lantiq ethernet phys led
> functionality.
>> > ++
>> > ++Example:
>> > ++ mdio at 0 {
>> > ++ #address-cells = <1>;
>> > ++ #size-cells = <0>;
>> > ++ compatible = "lantiq,xrx200-mdio";
>> > ++ phy5: ethernet-phy at 5 {
>> > ++ reg = <0x1>;
>> > ++ compatible = "lantiq,phy11g",
> "ethernet-phy-ieee802.3-c22";
>> > ++ };
>> > ++ phy11: ethernet-phy at 11 {
>> > ++ reg = <0x11>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led2h = <0x00>;
>> > ++ lantiq,led2l = <0x03>;
>> > ++ };
>> > ++ phy12: ethernet-phy at 12 {
>> > ++ reg = <0x12>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led1h = <0x00>;
>> > ++ lantiq,led1l = <0x03>;
>> > ++ };
>> > ++ phy13: ethernet-phy at 13 {
>> > ++ reg = <0x13>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led2h = <0x00>;
>> > ++ lantiq,led2l = <0x03>;
>> > ++ };
>> > ++ phy14: ethernet-phy at 14 {
>> > ++ reg = <0x14>;
>> > ++ compatible = "lantiq,phy22f",
> "ethernet-phy-ieee802.3-c22";
>> > ++ lantiq,led1h = <0x00>;
>> > ++ lantiq,led1l = <0x03>;
>> > ++ };
>> > ++ };
>> > ++
>> > ++Register Description
>> > ++============================================
>> > ++
>> > ++LEDCH:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LEDCH 0x00C5
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++| FBF | SBF |RES | NACS |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++FBC 7:6 RW Fast Blink Frequency
>> > ++ ---
>> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency
>> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency
>> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency
>> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency
>> > ++
>> > ++SBF 5:4 RW Slow Blink Frequency
>> > ++ ---
>> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency
>> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency
>> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency
>> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency
>> > ++
>> > ++NACS 2:0 RW Inverse of Scan Function
>> > ++ ---
>> > ++ 0x0 (000b) NONE No Function
>> > ++ 0x1 (001b) LINK Complex function enabled when
> link is up
>> > ++ 0x2 (010b) PDOWN Complex function enabled when
> device is powered-down
>> > ++ 0x3 (011b) EEE Complex function enabled when
> device is in EEE mode
>> > ++ 0x4 (100b) ANEG Complex function enabled when
> auto-negotiation is running
>> > ++ 0x5 (101b) ABIST Complex function enabled when
> analog self-test is running
>> > ++ 0x6 (110b) CDIAG Complex function enabled when
> cable diagnostics are running
>> > ++ 0x7 (111b) TEST Complex function enabled when
> test mode is running
>> > ++
>> > ++LEDCL:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LEDCL 0x0067
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++|RES | SCAN |RES | CBLINK |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++SCAN 6:4 RW Complex Scan Configuration
>> > ++ ---
>> > ++ 000 B NONE No Function
>> > ++ 001 B LINK Complex function enabled when link
> is up
>> > ++ 010 B PDOWN Complex function enabled when
> device is powered-down
>> > ++ 011 B EEE Complex function enabled when device
> is in EEE mode
>> > ++ 100 B ANEG Complex function enabled when
> auto-negotiation is running
>> > ++ 101 B ABIST Complex function enabled when
> analog self-test is running
>> > ++ 110 B CDIAG Complex function enabled when
> cable diagnostics are running
>> > ++ 111 B TEST Complex function enabled when test
> mode is running
>> > ++
>> > ++CBLINK 2:0 RW Complex Blinking Configuration
>> > ++ ---
>> > ++ 000 B NONE No Function
>> > ++ 001 B LINK Complex function enabled when link
> is up
>> > ++ 010 B PDOWN Complex function enabled when
> device is powered-down
>> > ++ 011 B EEE Complex function enabled when device
> is in EEE mode
>> > ++ 100 B ANEG Complex function enabled when
> auto-negotiation is running
>> > ++ 101 B ABIST Complex function enabled when
> analog self-test is running
>> > ++ 110 B CDIAG Complex function enabled when
> cable diagnostics are running
>> > ++ 111 B TEST Complex function enabled when test
> mode is running
>> > ++
>> > ++LEDxH:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LED0H 0x0070
>> > ++LED1H 0x0020
>> > ++LED2H 0x0040
>> > ++LED3H 0x0040
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++| CON | BLINKF |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++CON 7:4 RW Constant On Configuration
>> > ++ ---
>> > ++ 0x0 (0000b) NONE LED does not light up constantly
>> > ++ 0x1 (0001b) LINK10 LED is on when link is 10
> Mbit/s
>> > ++ 0x2 (0010b) LINK100 LED is on when link is 100
> Mbit/s
>> > ++ 0x3 (0011b) LINK10X LED is on when link is
> 10/100 Mbit/s
>> > ++ 0x4 (0100b) LINK1000 LED is on when link is
> 1000 Mbit/s
>> > ++ 0x5 (0101b) LINK10_0 LED is on when link is
> 10/1000 Mbit/s
>> > ++ 0x6 (0110b) LINK100X LED is on when link is
> 100/1000 Mbit/s
>> > ++ 0x7 (0111b) LINK10XX LED is on when link is
> 10/100/1000 Mbit/s
>> > ++ 0x8 (1000b) PDOWN LED is on when device is
> powered-down
>> > ++ 0x9 (1001b) EEE LED is on when device is in
> EEE mode
>> > ++ 0xA (1010b) ANEG LED is on when
> auto-negotiation is running
>> > ++ 0xB (1011b) ABIST LED is on when analog
> self-test is running
>> > ++ 0xC (1100b) CDIAG LED is on when cable
> diagnostics are running
>> > ++
>> > ++BLINKF 3:0 RW Fast Blinking Configuration
>> > ++ ---
>> > ++ 0x0 (0000b) NONE No Blinking
>> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
>> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
>> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100
> Mbit/s
>> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000
> Mbit/s
>> > ++ 0x5 (0101b) LINK10_0 Blink when link is
> 10/1000 Mbit/s
>> > ++ 0x6 (0110b) LINK100X Blink when link is
> 100/1000 Mbit/s
>> > ++ 0x7 (0111b) LINK10XX Blink when link is
> 10/100/1000 Mbit/s
>> > ++ 0x8 (1000b) PDOWN Blink when device is
> powered-down
>> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode
>> > ++ 0xA (1010b) ANEG Blink when auto-negotiation
> is running
>> > ++ 0xB (1011b) ABIST Blink when analog self-test
> is running
>> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics
> are running
>> > ++
>> > ++LEDxL:
>> > ++
>> > ++Name Hardware Reset Value
>> > ++LED0L 0x0003
>> > ++LED1L 0x0000
>> > ++LED2L 0x0000
>> > ++LED3L 0x0020
>> > ++
>> > ++| 15 | | | | | | | 8 |
>> > ++=========================================
>> > ++| RES |
>> > ++=========================================
>> > ++
>> > ++| 7 | | | | | | | 0 |
>> > ++=========================================
>> > ++| BLINKS | PULSE |
>> > ++=========================================
>> > ++
>> > ++Field Bits Type Description
>> > ++BLINKS 7:4 RW Slow Blinkin Configuration
>> > ++ ---
>> > ++ 0x0 (0000b) NONE No Blinking
>> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
>> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
>> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100
> Mbit/s
>> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000
> Mbit/s
>> > ++ 0x5 (0101b) LINK10_0 Blink when link is
> 10/1000 Mbit/s
>> > ++ 0x6 (0110b) LINK100X Blink when link is
> 100/1000 Mbit/s
>> > ++ 0x7 (0111b) LINK10XX Blink when link is
> 10/100/1000 Mbit/s
>> > ++ 0x8 (1000b) PDOWN Blink when device is
> powered-down
>> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode
>> > ++ 0xA (1010b) ANEG Blink when auto-negotiation
> is running
>> > ++ 0xB (1011b) ABIST Blink when analog self-test
> is running
>> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics
> are runningning
>> > ++
>> > ++PULSE 3:0 RW Pulsing Configuration
>> > ++ The pulse field is a mask field by which
> certain events can be combined
>> > ++ ---
>> > ++ 0x0 (0000b) NONE No pulsing
>> > ++ 0x1 (0001b) TXACT Transmit activity
>> > ++ 0x2 (0010b) RXACT Receive activity
>> > ++ 0x4 (0100b) COL Collision
>> > ++ 0x8 (1000b) RES Reserved
>> >
>
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