[OpenWrt-Devel] [PATCH v3 1/2] pinctrl/lantiq: introduce new dedicated tables

[Martin Schiller]

On 11/17/2015 at 4:10 PM, John Crispin wrote:
>
>
> On 17/11/2015 16:06, Daniel Schwierzeck wrote:
> > 2015-11-17 13:48 GMT+01:00 Martin Schiller <mschiller at tdt.de>:
> >> This patch introduces new dedicated "pinctrl-ase", "pinctrl-danube",
> >> "pinctrl-xrx100" and "pinctrl-xrx200" configuration tables.
> >>
> >> Based on the newest Lantiq Hardware Description it turend out, that
> there are
> >> some differences in the GPIO alternative functions of the Danube,
> xRX100 and
> >> xRX200 families, which makes it impossible to use only one xway_mfp
> table.
> >>
> >> This patch is also the first step to add support for the xRX300
> family.
> >>
> >> Signed-off-by: Martin Schiller <mschiller at tdt.de>
> >> ---
> >>  .../patches-3.18/0150-lantiq-pinctrl-xway.patch    | 1118
> +++++++++++++++++++-
> >>  .../patches-4.1/0150-lantiq-pinctrl-xway.patch     | 1118
> +++++++++++++++++++-
> >>  2 files changed, 2214 insertions(+), 22 deletions(-)
> >>
> >
> >> ++
> >> ++static const unsigned xrx200_pins_usif_spi[] = {GPIO11, GPIO12,
> GPIO38};
> >> ++static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
> >> ++static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
> >> ++static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
> >> ++
> >
> >> ++
> >> ++static const unsigned xrx200_pins_spi[] = {GPIO16, GPIO17,
> GPIO18};
> >> ++static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
> >> ++static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
> >> ++static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
> >> ++static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
> >> ++static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
> >> ++static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
> >> ++
> >
> > while you are at it, could you also add dedicated controls for the
> SPI
> > and USIF-SPI pins for all SoC's like:
> >
> > static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
> > static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
> > static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
> >
> > static const unsigned xrx200_pins_spi_di[] = {GPIO16};
> > static const unsigned xrx200_pins_spi_do[] = {GPIO17};
> > static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
> >

OK, that will be in the next version of my patch.

> > I have SPI and USIF-SPI drivers which are mostly ready for upstream
> > submission and their DT bindings depend on dedicated pin controls.
> >
> > Thanks,
> > Daniel
>
> there are also some fixes for mux functions inside ugw6.1.1. you might
> want to look at those and merge them.
>

In ugw6.1.1 there are the following patches for the pinctrl-xway driver:

8000-pinctrl-support-for-ar10-nand-drivers.patch:
Adds support for "AR10" (BTW: I hate this names, it's just the xRX300 family)
NAND IOs which will be integrated with the next version of my patch in the
xRX300 section.

8005-pinctrl-add-arc-jtag-pins.patch:
This Patch only adds a mux group "arc_jtag" which will set some pins to GPIO.
If I want to do that, I could simply do it in the dts with

arc_jtag {
lantiq,pins = "io9", "io10", "io11", "io14", "io19";
...
};

So, this patch is unnecessary in my opinion.


8006-pinctrl-lantiq-fix-spi-cs2-pin.patch:
Fixes the pins_spi_cs2 in the xway section to GPIO22.
I'm not sure if i should patch this deprecated code which can't be finally
fixed anyway.

8009-pinctrl-add-usif-pins.patch:
Adds some usif stuff, but my patch does it a cleaner way.

8011-pinctrl-add-usif-uart-pins.patch:
same as above.

8013-pinctrl-add-led-pins-to-support-xrx200.patch:
Same as the arc-jtag stuff.

8014-pinctrl-add-sysfs-support-for-utils.patch:
Adds sysfs interface to the pinctrl driver. I don't know why this is needed
and so I won't include this changes for now.

Martin
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