[RFC 3/4] realtek: rtl838x: refactor hpe_1920-24g dts

[Evan Jobling]

The HPE JG924A, JG925A and JG926A share the same base.
Prepare base device for adding the PoE enabled switch support.

Signed-off-by: Evan Jobling <evan.jobling at mslsc.com.au>
---
 .../realtek/dts/rtl8382_hpe_1920-24g.dts      | 62 +-----------------
 .../realtek/dts/rtl8382_hpe_1920-24g.dtsi     | 63 +++++++++++++++++++
 2 files changed, 64 insertions(+), 61 deletions(-)
 create mode 100644 target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi

diff --git a/target/linux/realtek/dts/rtl8382_hpe_1920-24g.dts b/target/linux/realtek/dts/rtl8382_hpe_1920-24g.dts
index 61781c708e..cc92b144b5 100644
--- a/target/linux/realtek/dts/rtl8382_hpe_1920-24g.dts
+++ b/target/linux/realtek/dts/rtl8382_hpe_1920-24g.dts
@@ -1,68 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "rtl8382_hpe_1920.dtsi"
+#include "rtl8382_hpe_1920-24g.dtsi"
 
 / {
 	compatible = "hpe,1920-24g", "realtek,rtl838x-soc";
 	model = "HPE 1920-24G (JG924A)";
 };
-
-&mdio {
-	EXTERNAL_PHY(0)
-	EXTERNAL_PHY(1)
-	EXTERNAL_PHY(2)
-	EXTERNAL_PHY(3)
-	EXTERNAL_PHY(4)
-	EXTERNAL_PHY(5)
-	EXTERNAL_PHY(6)
-	EXTERNAL_PHY(7)
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(0, 1, qsgmii)
-		SWITCH_PORT(1, 2, qsgmii)
-		SWITCH_PORT(2, 3, qsgmii)
-		SWITCH_PORT(3, 4, qsgmii)
-		SWITCH_PORT(4, 5, qsgmii)
-		SWITCH_PORT(5, 6, qsgmii)
-		SWITCH_PORT(6, 7, qsgmii)
-		SWITCH_PORT(7, 8, qsgmii)
-
-		SWITCH_PORT(8, 9, internal)
-		SWITCH_PORT(9, 10, internal)
-		SWITCH_PORT(10, 11, internal)
-		SWITCH_PORT(11, 12, internal)
-		SWITCH_PORT(12, 13, internal)
-		SWITCH_PORT(13, 14, internal)
-		SWITCH_PORT(14, 15, internal)
-		SWITCH_PORT(15, 16, internal)
-
-		SWITCH_PORT(16, 17, qsgmii)
-		SWITCH_PORT(17, 18, qsgmii)
-		SWITCH_PORT(18, 19, qsgmii)
-		SWITCH_PORT(19, 20, qsgmii)
-		SWITCH_PORT(20, 21, qsgmii)
-		SWITCH_PORT(21, 22, qsgmii)
-		SWITCH_PORT(22, 23, qsgmii)
-		SWITCH_PORT(23, 24, qsgmii)
-
-		SWITCH_PORT(24, 25, qsgmii)
-		SWITCH_PORT(25, 26, qsgmii)
-		SWITCH_PORT(26, 27, qsgmii)
-		SWITCH_PORT(27, 28, qsgmii)
-
-		port at 28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi b/target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi
new file mode 100644
index 0000000000..b724fc42d2
--- /dev/null
+++ b/target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8382_hpe_1920.dtsi"
+
+&mdio {
+	EXTERNAL_PHY(0)
+	EXTERNAL_PHY(1)
+	EXTERNAL_PHY(2)
+	EXTERNAL_PHY(3)
+	EXTERNAL_PHY(4)
+	EXTERNAL_PHY(5)
+	EXTERNAL_PHY(6)
+	EXTERNAL_PHY(7)
+};
+
+&switch0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		SWITCH_PORT(0, 1, qsgmii)
+		SWITCH_PORT(1, 2, qsgmii)
+		SWITCH_PORT(2, 3, qsgmii)
+		SWITCH_PORT(3, 4, qsgmii)
+		SWITCH_PORT(4, 5, qsgmii)
+		SWITCH_PORT(5, 6, qsgmii)
+		SWITCH_PORT(6, 7, qsgmii)
+		SWITCH_PORT(7, 8, qsgmii)
+
+		SWITCH_PORT(8, 9, internal)
+		SWITCH_PORT(9, 10, internal)
+		SWITCH_PORT(10, 11, internal)
+		SWITCH_PORT(11, 12, internal)
+		SWITCH_PORT(12, 13, internal)
+		SWITCH_PORT(13, 14, internal)
+		SWITCH_PORT(14, 15, internal)
+		SWITCH_PORT(15, 16, internal)
+
+		SWITCH_PORT(16, 17, qsgmii)
+		SWITCH_PORT(17, 18, qsgmii)
+		SWITCH_PORT(18, 19, qsgmii)
+		SWITCH_PORT(19, 20, qsgmii)
+		SWITCH_PORT(20, 21, qsgmii)
+		SWITCH_PORT(21, 22, qsgmii)
+		SWITCH_PORT(22, 23, qsgmii)
+		SWITCH_PORT(23, 24, qsgmii)
+
+		SWITCH_PORT(24, 25, qsgmii)
+		SWITCH_PORT(25, 26, qsgmii)
+		SWITCH_PORT(26, 27, qsgmii)
+		SWITCH_PORT(27, 28, qsgmii)
+
+		port at 28 {
+			ethernet = <&ethernet0>;
+			reg = <28>;
+			phy-mode = "internal";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
-- 
2.39.5