[PATCH 2/3] ramips: ethernet: ralink: fix MT7620A_GDMA regs

[Luiz Angelo Daros de Luca]

Registers in MT7620A_GDMA_OFFSET range were incorrect, except for the
first one GDM_FWD_CFG (which is actually the only one in use).
The next and last register is GDM_SHPR_CFG. All others are not mentioned
in docs.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca at gmail.com>
---
 .../ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h   | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
index 968db366cf..6b81946e30 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
@@ -152,10 +152,7 @@ enum fe_work_flag {
 #define MT7620A_GDMA_OFFSET		0x0600
 #endif
 #define	MT7620A_GDMA1_FWD_CFG		(MT7620A_GDMA_OFFSET + 0x00)
-#define MT7620A_FE_GDMA1_SCH_CFG	(MT7620A_GDMA_OFFSET + 0x04)
-#define MT7620A_FE_GDMA1_SHPR_CFG	(MT7620A_GDMA_OFFSET + 0x08)
-#define MT7620A_FE_GDMA1_MAC_ADRL	(MT7620A_GDMA_OFFSET + 0x0C)
-#define MT7620A_FE_GDMA1_MAC_ADRH	(MT7620A_GDMA_OFFSET + 0x10)
+#define MT7620A_FE_GDMA1_SHPR_CFG	(MT7620A_GDMA_OFFSET + 0x04)
 
 #define MT7620A_RESET_FE	BIT(21)
 #define MT7620A_RESET_ESW	BIT(23)
-- 
2.34.0