[PATCH] cn913x: add support for iEi Puzzle-M901/Puzzle-M902
Ian Chang
ianchang at ieiworld.com
Wed May 26 01:43:30 PDT 2021
Hi Robert
I will modify the M901/M902 device tree and upload it after verification
> On a semi-related note, are you planning to add support for M801 to
> OpenWrt as well?
We will focus on M901/M902 products first, and then we will consider whether to add support for M801 in OpenWrt in the future.
Best Regards
Ian Chang
-----Original Message-----
From: Robert Marko <robimarko at gmail.com>
Sent: Monday, May 24, 2021 5:57 PM
To: eveans2002 at gmail.com
Cc: OpenWrt Development List <openwrt-devel at lists.openwrt.org>; ianchang <ianchang at ieiworld.com>
Subject: Re: [PATCH] cn913x: add support for iEi Puzzle-M901/Puzzle-M902
Hi Ian,
On Sun, 23 May 2021 at 19:59, <eveans2002 at gmail.com> wrote:
>
> From: ianchang <ianchang at ieiworld.com>
>
> Hardware specification
> ----------------------
> * CN9130 SoC, Quad-core ARMv8 Cortex-72 @ 2200 MHz
> * 4 GB DDR
> * 4 GB eMMC
> * 4 MB (SPI Flash)
> * 6 x 2.5 Gigabit ports (Puzzle-M901)
> - External PHY with 6 ports (AQR112R)
> * 6 x 2.5 Gigabit ports (Puzzle-M902)
> - External PHY with 6 ports (AQR112R)
> 3 x 10 Gigabit ports (Puzzle-M902)
> - External PHY with 3 ports (AQR113R)
>
> * 4 x Front panel LED
> * 1 x USB 3.0
> * Reset button on Rear panel
> * UART (115200 8N1,header on PCB)
>
> Signed-off-by: ianchang <ianchang at ieiworld.com>
This looks like a very interesting device.
Since my colleagues have added support for M801 in upstream Linux I
think there are a few improvements that will need to be made to the
device tree files for M901.
Could you please send the board support patches to upstream Linux
first as they did for M801?
On a semi-related note, are you planning to add support for M801 to
OpenWrt as well?
Thanks,
Robert
> ---
> .../base-files/etc/board.d/02_network | 9 +-
> target/linux/mvebu/cortexa72/config-5.4 | 14 +
> .../boot/dts/marvell/armada-ap807-quad.dtsi | 93 +
> .../arm64/boot/dts/marvell/armada-ap807.dtsi | 30 +
> .../arm64/boot/dts/marvell/armada-ap80x.dtsi | 464 ++++
> .../arm64/boot/dts/marvell/armada-cp115.dtsi | 12 +
> .../arm64/boot/dts/marvell/armada-cp11x.dtsi | 573 +++++
> .../dts/marvell/puzzle-armada-common.dtsi | 11 +
> .../boot/dts/marvell/puzzle-armada-cp110.dtsi | 12 +
> .../arm64/boot/dts/marvell/puzzle-cn9130.dtsi | 37 +
> .../dts/marvell/puzzle-m901-cn9130-db.dts | 429 ++++
> .../dts/marvell/puzzle-m901-cn9131-db.dts | 243 +++
> .../dts/marvell/puzzle-m902-cn9130-db.dts | 430 ++++
> .../dts/marvell/puzzle-m902-cn9131-db.dts | 247 +++
> .../dts/marvell/puzzle-m902-cn9132-db.dts | 261 +++
> target/linux/mvebu/files/drivers/rtc/Kconfig | 1943 +++++++++++++++++
> target/linux/mvebu/files/drivers/rtc/Makefile | 189 ++
> .../mvebu/files/drivers/rtc/rtc-rx8130.c | 807 +++++++
> target/linux/mvebu/image/cortexa72.mk | 20 +
> 19 files changed, 5823 insertions(+), 1 deletion(-)
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts
> create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts
> create mode 100644 target/linux/mvebu/files/drivers/rtc/Kconfig
> create mode 100644 target/linux/mvebu/files/drivers/rtc/Makefile
> create mode 100644 target/linux/mvebu/files/drivers/rtc/rtc-rx8130.c
>
> diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> index 9ab3c8174d..9ad043b343 100755
> --- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> +++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> @@ -21,8 +21,15 @@ marvell,armada8040-db)
> marvell,armada7040-db)
> ucidef_set_interfaces_lan_wan "eth0 eth2" "eth1"
> ;;
> +marvell,cn9131)
> + ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
> + ;;
> +marvell,cn9132)
> + ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5 eth10 eth11 eth12" "eth0"
> + ;;
> *)
> - ucidef_set_interface_lan "eth0"
> +# ucidef_set_interface_lan "eth0"
> + ucidef_set_interfaces_lan_wan "eth0 eth3" "eth6"
> ;;
> esac
>
> diff --git a/target/linux/mvebu/cortexa72/config-5.4 b/target/linux/mvebu/cortexa72/config-5.4
> index 5727ae5918..919f579157 100644
> --- a/target/linux/mvebu/cortexa72/config-5.4
> +++ b/target/linux/mvebu/cortexa72/config-5.4
> @@ -175,3 +175,17 @@ CONFIG_THREAD_INFO_IN_TASK=y
> CONFIG_UNMAP_KERNEL_AT_EL0=y
> CONFIG_VMAP_STACK=y
> CONFIG_ZONE_DMA32=y
> +# CONFIG_PUZZLE-M90x
> +CONFIG_RTC_DRV_RX8130=y
> +# CONFIG_RTC_DRV_MV is not set
> +# CONFIG_RTC_DRV_ARMADA38X is not set
> +# Character devices
> +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
> +CONFIG_DEVMEM=y
> +CONFIG_NVME_CORE=y
> +CONFIG_BLK_DEV_NVME=y
> +# CONFIG_NVME_MULTIPATH is not set
> +# CONFIG_NVME_FC is not set
> +# CONFIG_NVME_TCP is not set
> +# CONFIG_NVME_TARGET is not set
> +# end of NVME Support
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> new file mode 100644
> index 0000000000..68782f161f
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for Marvell Armada AP807 Quad
> + *
> + * Copyright (C) 2019 Marvell Technology Group Ltd.
> + */
> +
> +#include "armada-ap807.dtsi"
> +
> +/ {
> + model = "Marvell Armada AP807 Quad";
> + compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x000>;
> + enable-method = "psci";
> + #cooling-cells = <2>;
> + clocks = <&cpu_clk 0>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_0>;
> + };
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x001>;
> + enable-method = "psci";
> + #cooling-cells = <2>;
> + clocks = <&cpu_clk 0>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_0>;
> + };
> + cpu2: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x100>;
> + enable-method = "psci";
> + #cooling-cells = <2>;
> + clocks = <&cpu_clk 1>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_1>;
> + };
> + cpu3: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x101>;
> + enable-method = "psci";
> + #cooling-cells = <2>;
> + clocks = <&cpu_clk 1>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + cache-size = <0x80000>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + cache-size = <0x80000>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + };
> + };
> +};
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
> new file mode 100644
> index 0000000000..1ada2f5c43
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for Marvell Armada AP807
> + *
> + * Copyright (C) 2019 Marvell Technology Group Ltd.
> + */
> +
> +#define AP_NAME ap807
> +#include "armada-ap80x.dtsi"
> +
> +/ {
> + model = "Marvell Armada AP807";
> + compatible = "marvell,armada-ap807";
> +};
> +
> +&ap_syscon0 {
> + ap_clk: clock {
> + compatible = "marvell,ap807-clock";
> + #clock-cells = <1>;
> + };
> +};
> +
> +&ap_syscon1 {
> + cpu_clk: clock-cpu {
> + compatible = "marvell,ap807-cpu-clock";
> + clocks = <&ap_clk 0>, <&ap_clk 1>;
> + #clock-cells = <1>;
> + status = "okay";
> + };
> +};
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> new file mode 100644
> index 0000000000..8536c2d553
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> @@ -0,0 +1,464 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell Technology Group Ltd.
> + *
> + * Device Tree file for Marvell Armada AP80x.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + gpio0 = &ap_gpio;
> + spi0 = &spi0;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /*
> + * This area matches the mapping done with a
> + * mainline U-Boot, and should be updated by the
> + * bootloader.
> + */
> +
> + psci-area at 4000000 {
> + reg = <0x0 0x4000000 0x0 0x200000>;
> + no-map;
> + };
> + };
> +
> + AP_NAME {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + config-space at f0000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges = <0x0 0x0 0xf0000000 0x1000000>;
> +
> + smmu: iommu at 5000000 {
> + compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
> + reg = <0x100000 0x100000>;
> + dma-coherent;
> + #iommu-cells = <1>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller at 210000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + reg = <0x210000 0x10000>,
> + <0x220000 0x20000>,
> + <0x240000 0x20000>,
> + <0x260000 0x20000>;
> +
> + gic_v2m0: v2m at 280000 {
> + compatible = "arm,gic-v2m-frame";
> + msi-controller;
> + reg = <0x280000 0x1000>;
> + arm,msi-base-spi = <160>;
> + arm,msi-num-spis = <32>;
> + };
> + gic_v2m1: v2m at 290000 {
> + compatible = "arm,gic-v2m-frame";
> + msi-controller;
> + reg = <0x290000 0x1000>;
> + arm,msi-base-spi = <192>;
> + arm,msi-num-spis = <32>;
> + };
> + gic_v2m2: v2m at 2a0000 {
> + compatible = "arm,gic-v2m-frame";
> + msi-controller;
> + reg = <0x2a0000 0x1000>;
> + arm,msi-base-spi = <224>;
> + arm,msi-num-spis = <32>;
> + };
> + gic_v2m3: v2m at 2b0000 {
> + compatible = "arm,gic-v2m-frame";
> + msi-controller;
> + reg = <0x2b0000 0x1000>;
> + arm,msi-base-spi = <256>;
> + arm,msi-num-spis = <32>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a72-pmu";
> + interrupt-parent = <&pic>;
> + interrupts = <17>;
> + };
> +
> + odmi: odmi at 300000 {
> + compatible = "marvell,odmi-controller";
> + interrupt-controller;
> + msi-controller;
> + marvell,odmi-frames = <4>;
> + reg = <0x300000 0x4000>,
> + <0x304000 0x4000>,
> + <0x308000 0x4000>,
> + <0x30C000 0x4000>;
> + marvell,spi-base = <128>, <136>, <144>, <152>;
> + };
> +
> + gicp: gicp at 3f0040 {
> + compatible = "marvell,ap806-gicp";
> + reg = <0x3f0040 0x10>;
> + marvell,spi-ranges = <64 64>, <288 64>;
> + msi-controller;
> + };
> +
> + pic: interrupt-controller at 3f0100 {
> + compatible = "marvell,armada-8k-pic";
> + reg = <0x3f0100 0x10>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sei: interrupt-controller at 3f0200 {
> + compatible = "marvell,ap806-sei";
> + reg = <0x3f0200 0x40>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + msi-controller;
> + };
> +
> + xor at 400000 {
> + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> + reg = <0x400000 0x1000>,
> + <0x410000 0x1000>;
> + msi-parent = <&gic_v2m0>;
> + clocks = <&ap_clk 3>;
> + dma-coherent;
> + iommus = <&smmu 0x1>;
> + };
> +
> + xor at 420000 {
> + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> + reg = <0x420000 0x1000>,
> + <0x430000 0x1000>;
> + msi-parent = <&gic_v2m0>;
> + clocks = <&ap_clk 3>;
> + dma-coherent;
> + iommus = <&smmu 0x2>;
> + };
> +
> + xor at 440000 {
> + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> + reg = <0x440000 0x1000>,
> + <0x450000 0x1000>;
> + msi-parent = <&gic_v2m0>;
> + clocks = <&ap_clk 3>;
> + dma-coherent;
> + };
> +
> + xor at 460000 {
> + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> + reg = <0x460000 0x1000>,
> + <0x470000 0x1000>;
> + msi-parent = <&gic_v2m0>;
> + clocks = <&ap_clk 3>;
> + dma-coherent;
> + };
> +
> + spi0: spi at 510600 {
> + compatible = "marvell,armada-380-spi";
> + reg = <0x510600 0x50>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ap_clk 3>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c at 511000 {
> + compatible = "marvell,mv78230-i2c";
> + reg = <0x511000 0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ap_clk 3>;
> + status = "disabled";
> + };
> +
> + uart0: serial at 512000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x512000 0x100>;
> + reg-shift = <2>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <1>;
> + clocks = <&ap_clk 3>;
> + status = "disabled";
> + };
> +
> + uart1: serial at 512100 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x512100 0x100>;
> + reg-shift = <2>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <1>;
> + clocks = <&ap_clk 3>;
> + status = "disabled";
> +
> + };
> +
> + watchdog: watchdog at 610000 {
> + compatible = "arm,sbsa-gwdt";
> + reg = <0x610000 0x1000>, <0x600000 0x1000>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + ap_sdhci0: sdhci at 6e0000 {
> + compatible = "marvell,armada-ap806-sdhci";
> + reg = <0x6e0000 0x300>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core";
> + clocks = <&ap_clk 4>;
> + dma-coherent;
> + iommus = <&smmu 0x5>;
> + marvell,xenon-phy-slow-mode;
> + status = "disabled";
> + };
> +
> + ap_syscon0: system-controller at 6f4000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0x6f4000 0x2000>;
> +
> + ap_pinctrl: pinctrl {
> + compatible = "marvell,ap806-pinctrl";
> +
> + uart0_pins: uart0-pins {
> + marvell,pins = "mpp11", "mpp19";
> + marvell,function = "uart0";
> + };
> + };
> +
> + ap_gpio: gpio at 1040 {
> + compatible = "marvell,armada-8k-gpio";
> + offset = <0x1040>;
> + ngpios = <20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&ap_pinctrl 0 0 20>;
> + };
> + };
> +
> + ap_syscon1: system-controller at 6f8000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0x6f8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ap_thermal: thermal-sensor at 80 {
> + compatible = "marvell,armada-ap806-thermal";
> + reg = <0x80 0x10>;
> + interrupt-parent = <&sei>;
> + interrupts = <18>;
> + #thermal-sensor-cells = <1>;
> + };
> + };
> + };
> + };
> +
> + /*
> + * The thermal IP features one internal sensor plus, if applicable, one
> + * remote channel wired to one sensor per CPU.
> + *
> + * Only one thermal zone per AP/CP may trigger interrupts at a time, the
> + * first one that will have a critical trip point will be chosen.
> + */
> + thermal-zones {
> + ap_thermal_ic: ap-thermal-ic {
> + polling-delay-passive = <0>; /* Interrupt driven */
> + polling-delay = <0>; /* Interrupt driven */
> +
> + thermal-sensors = <&ap_thermal 0>;
> +
> + trips {
> + ap_crit: ap-crit {
> + temperature = <100000>; /* mC degrees */
> + hysteresis = <2000>; /* mC degrees */
> + type = "critical";
> + };
> + };
> +
> + cooling-maps { };
> + };
> +
> + ap_thermal_cpu0: ap-thermal-cpu0 {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&ap_thermal 1>;
> +
> + trips {
> + cpu0_hot: cpu0-hot {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu0_emerg: cpu0-emerg {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + map0_hot: map0-hot {
> + trip = <&cpu0_hot>;
> + cooling-device = <&cpu0 1 2>,
> + <&cpu1 1 2>;
> + };
> + map0_emerg: map0-ermerg {
> + trip = <&cpu0_emerg>;
> + cooling-device = <&cpu0 3 3>,
> + <&cpu1 3 3>;
> + };
> + };
> + };
> +
> + ap_thermal_cpu1: ap-thermal-cpu1 {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&ap_thermal 2>;
> +
> + trips {
> + cpu1_hot: cpu1-hot {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu1_emerg: cpu1-emerg {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + map1_hot: map1-hot {
> + trip = <&cpu1_hot>;
> + cooling-device = <&cpu0 1 2>,
> + <&cpu1 1 2>;
> + };
> + map1_emerg: map1-emerg {
> + trip = <&cpu1_emerg>;
> + cooling-device = <&cpu0 3 3>,
> + <&cpu1 3 3>;
> + };
> + };
> + };
> +
> + ap_thermal_cpu2: ap-thermal-cpu2 {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&ap_thermal 3>;
> +
> + trips {
> + cpu2_hot: cpu2-hot {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu2_emerg: cpu2-emerg {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + map2_hot: map2-hot {
> + trip = <&cpu2_hot>;
> + cooling-device = <&cpu2 1 2>,
> + <&cpu3 1 2>;
> + };
> + map2_emerg: map2-emerg {
> + trip = <&cpu2_emerg>;
> + cooling-device = <&cpu2 3 3>,
> + <&cpu3 3 3>;
> + };
> + };
> + };
> +
> + ap_thermal_cpu3: ap-thermal-cpu3 {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&ap_thermal 4>;
> +
> + trips {
> + cpu3_hot: cpu3-hot {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu3_emerg: cpu3-emerg {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + map3_hot: map3-bhot {
> + trip = <&cpu3_hot>;
> + cooling-device = <&cpu2 1 2>,
> + <&cpu3 1 2>;
> + };
> + map3_emerg: map3-emerg {
> + trip = <&cpu3_emerg>;
> + cooling-device = <&cpu2 3 3>,
> + <&cpu3 3 3>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp115.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
> new file mode 100644
> index 0000000000..1d0a9653e6
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell Technology Group Ltd.
> + *
> + * Device Tree file for Marvell Armada CP115.
> + */
> +
> +#define CP11X_TYPE cp115
> +
> +#include "armada-cp11x.dtsi"
> +
> +#undef CP11X_TYPE
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> new file mode 100644
> index 0000000000..ec27e32d61
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> @@ -0,0 +1,573 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2016 Marvell Technology Group Ltd.
> + *
> + * Device Tree file for Marvell Armada CP11x.
> + */
> +
> +#include <dt-bindings/interrupt-controller/mvebu-icu.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +#include "puzzle-armada-common.dtsi"
> +
> +#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
> +
> +/ {
> + /*
> + * The contents of the node are defined below, in order to
> + * save one indentation level
> + */
> + CP11X_NAME: CP11X_NAME { };
> +
> + /*
> + * CPs only have one sensor in the thermal IC.
> + *
> + * The cooling maps are empty as there are no cooling devices.
> + */
> +// thermal-zones {
> +// CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
> +// polling-delay-passive = <0>; /* Interrupt driven */
> +// polling-delay = <0>; /* Interrupt driven */
> +
> +// thermal-sensors = <&CP11X_LABEL(thermal) 0>;
> +
> +// trips {
> +// CP11X_LABEL(crit): crit {
> +// temperature = <100000>; /* mC degrees */
> +// hysteresis = <2000>; /* mC degrees */
> +// type = "critical";
> +// };
> +// };
> +
> +// cooling-maps { };
> +// };
> +// };
> +};
> +
> +&CP11X_NAME {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
> + ranges;
> +
> + config-space at CP11X_BASE {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
> +
> + CP11X_LABEL(ethernet): ethernet at 0 {
> + compatible = "marvell,armada-7k-pp22";
> + reg = <0x0 0x100000>, <0x129000 0xb000>;
> + clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
> + <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
> + <&CP11X_LABEL(clk) 1 18>;
> + clock-names = "pp_clk", "gop_clk",
> + "mg_clk", "mg_core_clk", "axi_clk";
> + marvell,system-controller = <&CP11X_LABEL(syscon0)>;
> + status = "disabled";
> + dma-coherent;
> +
> + CP11X_LABEL(eth0): eth0 {
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
> + <43 IRQ_TYPE_LEVEL_HIGH>,
> + <47 IRQ_TYPE_LEVEL_HIGH>,
> + <51 IRQ_TYPE_LEVEL_HIGH>,
> + <55 IRQ_TYPE_LEVEL_HIGH>,
> + <59 IRQ_TYPE_LEVEL_HIGH>,
> + <63 IRQ_TYPE_LEVEL_HIGH>,
> + <67 IRQ_TYPE_LEVEL_HIGH>,
> + <71 IRQ_TYPE_LEVEL_HIGH>,
> + <129 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hif0", "hif1", "hif2",
> + "hif3", "hif4", "hif5", "hif6", "hif7",
> + "hif8", "link";
> + port-id = <0>;
> + gop-port-id = <0>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(eth1): eth1 {
> + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
> + <44 IRQ_TYPE_LEVEL_HIGH>,
> + <48 IRQ_TYPE_LEVEL_HIGH>,
> + <52 IRQ_TYPE_LEVEL_HIGH>,
> + <56 IRQ_TYPE_LEVEL_HIGH>,
> + <60 IRQ_TYPE_LEVEL_HIGH>,
> + <64 IRQ_TYPE_LEVEL_HIGH>,
> + <68 IRQ_TYPE_LEVEL_HIGH>,
> + <72 IRQ_TYPE_LEVEL_HIGH>,
> + <128 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hif0", "hif1", "hif2",
> + "hif3", "hif4", "hif5", "hif6", "hif7",
> + "hif8", "link";
> + port-id = <1>;
> + gop-port-id = <2>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(eth2): eth2 {
> + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
> + <45 IRQ_TYPE_LEVEL_HIGH>,
> + <49 IRQ_TYPE_LEVEL_HIGH>,
> + <53 IRQ_TYPE_LEVEL_HIGH>,
> + <57 IRQ_TYPE_LEVEL_HIGH>,
> + <61 IRQ_TYPE_LEVEL_HIGH>,
> + <65 IRQ_TYPE_LEVEL_HIGH>,
> + <69 IRQ_TYPE_LEVEL_HIGH>,
> + <73 IRQ_TYPE_LEVEL_HIGH>,
> + <127 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hif0", "hif1", "hif2",
> + "hif3", "hif4", "hif5", "hif6", "hif7",
> + "hif8", "link";
> + port-id = <2>;
> + gop-port-id = <3>;
> + status = "disabled";
> + };
> + };
> +
> + CP11X_LABEL(comphy): phy at 120000 {
> + compatible = "marvell,comphy-cp110";
> + reg = <0x120000 0x6000>;
> + marvell,system-controller = <&CP11X_LABEL(syscon0)>;
> + clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
> + <&CP11X_LABEL(clk) 1 18>;
> + clock-names = "mg_clk", "mg_core_clk", "axi_clk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CP11X_LABEL(comphy0): phy at 0 {
> + reg = <0>;
> + #phy-cells = <1>;
> + };
> +
> + CP11X_LABEL(comphy1): phy at 1 {
> + reg = <1>;
> + #phy-cells = <1>;
> + };
> +
> + CP11X_LABEL(comphy2): phy at 2 {
> + reg = <2>;
> + #phy-cells = <1>;
> + };
> +
> + CP11X_LABEL(comphy3): phy at 3 {
> + reg = <3>;
> + #phy-cells = <1>;
> + };
> +
> + CP11X_LABEL(comphy4): phy at 4 {
> + reg = <4>;
> + #phy-cells = <1>;
> + };
> +
> + CP11X_LABEL(comphy5): phy at 5 {
> + reg = <5>;
> + #phy-cells = <1>;
> + };
> + };
> +
> + CP11X_LABEL(mdio): mdio at 12a200 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,orion-mdio";
> + reg = <0x12a200 0x10>;
> + clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
> + <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(xmdio): mdio at 12a600 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,xmdio";
> + reg = <0x12a600 0x10>;
> + clocks = <&CP11X_LABEL(clk) 1 5>,
> + <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(icu): interrupt-controller at 1e0000 {
> + compatible = "marvell,cp110-icu";
> + reg = <0x1e0000 0x440>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + CP11X_LABEL(icu_nsr): interrupt-controller at 10 {
> + compatible = "marvell,cp110-icu-nsr";
> + reg = <0x10 0x20>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + msi-parent = <&gicp>;
> + };
> +
> + CP11X_LABEL(icu_sei): interrupt-controller at 50 {
> + compatible = "marvell,cp110-icu-sei";
> + reg = <0x50 0x10>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + msi-parent = <&sei>;
> + };
> + };
> +
> + CP11X_LABEL(rtc): rtc at 284000 {
> + compatible = "marvell,armada-8k-rtc";
> + reg = <0x284000 0x20>, <0x284080 0x24>;
> + reg-names = "rtc", "rtc-soc";
> + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + CP11X_LABEL(syscon0): system-controller at 440000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0x440000 0x2000>;
> +
> + CP11X_LABEL(clk): clock {
> + compatible = "marvell,cp110-clock";
> + #clock-cells = <2>;
> + };
> +
> + CP11X_LABEL(gpio1): gpio at 100 {
> + compatible = "marvell,armada-8k-gpio";
> + offset = <0x100>;
> + ngpios = <32>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
> + interrupt-controller;
> + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
> + <85 IRQ_TYPE_LEVEL_HIGH>,
> + <84 IRQ_TYPE_LEVEL_HIGH>,
> + <83 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <2>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(gpio2): gpio at 140 {
> + compatible = "marvell,armada-8k-gpio";
> + offset = <0x140>;
> + ngpios = <31>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
> + interrupt-controller;
> + interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
> + <81 IRQ_TYPE_LEVEL_HIGH>,
> + <80 IRQ_TYPE_LEVEL_HIGH>,
> + <79 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <2>;
> + status = "disabled";
> + };
> + };
> +
> + CP11X_LABEL(thermal): thermal at 400078 {
> + compatible = "marvell,armada-cp110-thermal";
> + reg = <0x400078 0x4>,
> + <0x400070 0x8>;
> + };
> +// CP11X_LABEL(syscon1): system-controller at 400000 {
> +// compatible = "syscon", "simple-mfd";
> +// reg = <0x400000 0x1000>;
> +// #address-cells = <1>;
> +// #size-cells = <1>;
> +
> +// CP11X_LABEL(thermal): thermal-sensor at 70 {
> +// compatible = "marvell,armada-cp110-thermal";
> +// reg = <0x70 0x10>;
> +// interrupts-extended =
> +// <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
> +// #thermal-sensor-cells = <1>;
> +// };
> +// };
> +
> + CP11X_LABEL(usb3_0): usb at 500000 {
> + compatible = "marvell,armada-8k-xhci",
> + "generic-xhci";
> + reg = <0x500000 0x4000>;
> + dma-coherent;
> + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 22>,
> + <&CP11X_LABEL(clk) 1 16>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(usb3_1): usb at 510000 {
> + compatible = "marvell,armada-8k-xhci",
> + "generic-xhci";
> + reg = <0x510000 0x4000>;
> + dma-coherent;
> + interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 23>,
> + <&CP11X_LABEL(clk) 1 16>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(sata0): sata at 540000 {
> + compatible = "marvell,armada-8k-ahci";
> + reg = <0x540000 0x30000>;
> + dma-coherent;
> + clocks = <&CP11X_LABEL(clk) 1 15>,
> + <&CP11X_LABEL(clk) 1 16>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sata-port at 0 {
> + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0>;
> + };
> +
> + sata-port at 1 {
> + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <1>;
> + };
> + };
> +
> + CP11X_LABEL(xor0): xor at 6a0000 {
> + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> + reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
> + dma-coherent;
> + msi-parent = <&gic_v2m0>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 8>,
> + <&CP11X_LABEL(clk) 1 14>;
> + };
> +
> + CP11X_LABEL(xor1): xor at 6c0000 {
> + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> + reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
> + dma-coherent;
> + msi-parent = <&gic_v2m0>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 7>,
> + <&CP11X_LABEL(clk) 1 14>;
> + };
> +
> + CP11X_LABEL(spi0): spi at 700600 {
> + compatible = "marvell,armada-380-spi";
> + reg = <0x700600 0x50>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + clock-names = "core", "axi";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(spi1): spi at 700680 {
> + compatible = "marvell,armada-380-spi";
> + reg = <0x700680 0x50>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "core", "axi";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(i2c0): i2c at 701000 {
> + compatible = "marvell,mv78230-i2c";
> + reg = <0x701000 0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(i2c1): i2c at 701100 {
> + compatible = "marvell,mv78230-i2c";
> + reg = <0x701100 0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(uart0): serial at 702000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x702000 0x100>;
> + reg-shift = <2>;
> + interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <1>;
> + clock-names = "baudclk", "apb_pclk";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(uart1): serial at 702100 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x702100 0x100>;
> + reg-shift = <2>;
> + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <1>;
> + clock-names = "baudclk", "apb_pclk";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(uart2): serial at 702200 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x702200 0x100>;
> + reg-shift = <2>;
> + interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <1>;
> + clock-names = "baudclk", "apb_pclk";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(uart3): serial at 702300 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x702300 0x100>;
> + reg-shift = <2>;
> + interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <1>;
> + clock-names = "baudclk", "apb_pclk";
> + clocks = <&CP11X_LABEL(clk) 1 21>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(nand_controller): nand at 720000 {
> + /*
> + * Due to the limitation of the pins available
> + * this controller is only usable on the CPM
> + * for A7K and on the CPS for A8K.
> + */
> + compatible = "marvell,armada-8k-nand-controller",
> + "marvell,armada370-nand-controller";
> + reg = <0x720000 0x54>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 2>,
> + <&CP11X_LABEL(clk) 1 17>;
> + marvell,system-controller = <&CP11X_LABEL(syscon0)>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(trng): trng at 760000 {
> + compatible = "marvell,armada-8k-rng",
> + "inside-secure,safexcel-eip76";
> + reg = <0x760000 0x7d>;
> + interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 25>,
> + <&CP11X_LABEL(clk) 1 17>;
> + status = "okay";
> + };
> +
> + CP11X_LABEL(sdhci0): sdhci at 780000 {
> + compatible = "marvell,armada-cp110-sdhci";
> + reg = <0x780000 0x300>;
> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core", "axi";
> + clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
> + dma-coherent;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(crypto): crypto at 800000 {
> + compatible = "inside-secure,safexcel-eip197b";
> + reg = <0x800000 0x200000>;
> + interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
> + <88 IRQ_TYPE_LEVEL_HIGH>,
> + <89 IRQ_TYPE_LEVEL_HIGH>,
> + <90 IRQ_TYPE_LEVEL_HIGH>,
> + <91 IRQ_TYPE_LEVEL_HIGH>,
> + <92 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "mem", "ring0", "ring1",
> + "ring2", "ring3", "eip";
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 26>,
> + <&CP11X_LABEL(clk) 1 17>;
> + dma-coherent;
> + };
> + };
> +
> + CP11X_LABEL(pcie0): pcie at CP11X_PCIE0_BASE {
> + compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
> + reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
> + <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
> + reg-names = "ctrl", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + device_type = "pci";
> + dma-coherent;
> + msi-parent = <&gic_v2m0>;
> +
> + bus-range = <0 0xff>;
> + /* non-prefetchable memory */
> + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> + num-lanes = <1>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(pcie1): pcie at CP11X_PCIE1_BASE {
> + compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
> + reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
> + <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
> + reg-names = "ctrl", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + device_type = "pci";
> + dma-coherent;
> + msi-parent = <&gic_v2m0>;
> +
> + bus-range = <0 0xff>;
> + /* non-prefetchable memory */
> + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
> +
> + num-lanes = <1>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
> + status = "disabled";
> + };
> +
> + CP11X_LABEL(pcie2): pcie at CP11X_PCIE2_BASE {
> + compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
> + reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
> + <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
> + reg-names = "ctrl", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + device_type = "pci";
> + dma-coherent;
> + msi-parent = <&gic_v2m0>;
> +
> + bus-range = <0 0xff>;
> + /* non-prefetchable memory */
> + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> +
> + num-lanes = <1>;
> + clock-names = "core", "reg";
> + clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
> + status = "disabled";
> + };
> +};
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi
> new file mode 100644
> index 0000000000..c04c6c4750
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2016 Marvell Technology Group Ltd.
> + */
> +
> +/* Common definitions used by Armada 7K/8K DTs */
> +#define PASTER(x, y) x ## y
> +#define EVALUATOR(x, y) PASTER(x, y)
> +#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
> +#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
> +#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi
> new file mode 100644
> index 0000000000..4fd33b0fa5
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell Technology Group Ltd.
> + *
> + * Device Tree file for Marvell Armada CP110.
> + */
> +
> +#define CP11X_TYPE cp110
> +
> +#include "armada-cp11x.dtsi"
> +
> +#undef CP11X_TYPE
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi
> new file mode 100644
> index 0000000000..a2b7e5ec97
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9130 SoC.
> + */
> +
> +#include "armada-ap807-quad.dtsi"
> +
> +/ {
> + model = "Marvell Armada CN9130 SoC";
> + compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
> + "marvell,armada-ap807";
> +};
> +
> +/*
> + * Instantiate the internal CP115
> + */
> +
> +#define CP11X_NAME cp0
> +#define CP11X_BASE f2000000
> +#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
> + 0xe0000000 + ((iface - 1) * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
> +#define CP11X_PCIE0_BASE f2600000
> +#define CP11X_PCIE1_BASE f2620000
> +#define CP11X_PCIE2_BASE f2640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts
> new file mode 100644
> index 0000000000..44046fa30d
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts
> @@ -0,0 +1,429 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9130-DB board.
> + */
> +
> +#include "puzzle-cn9130.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Puzzle-M901";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + aliases {
> + i2c0 = &cp0_i2c0;
> + ethernet0 = &cp0_eth0;
> + ethernet1 = &cp0_eth1;
> + ethernet2 = &cp0_eth2;
> + gpio1 = &cp0_gpio1;
> + gpio2 = &cp0_gpio2;
> + spi1 = &cp0_spi0;
> + spi2 = &cp0_spi1;
> + serial1 = &cp0_uart0;
> + };
> +
> + memory at 00000000 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>;
> + };
> +
> + ap0_reg_sd_vccq: ap0_sd_vccq at 0 {
> +// compatible = "regulator-gpio";
> +// regulator-name = "ap0_sd_vccq";
> +// regulator-min-microvolt = <1800000>;
> +// regulator-max-microvolt = <3300000>;
> +// gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
> +// states = <1800000 0x1 3300000 0x0>;
> + };
> +
> +/*
> + cp0_reg_usb3_vbus0: cp0_usb3_vbus at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp0-xhci0-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
> + };
> +
> + cp0_usb3_0_phy0: cp0_usb3_phy at 0 {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp0_reg_usb3_vbus0>;
> + };
> +
> + cp0_reg_usb3_vbus1: cp0_usb3_vbus at 1 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp0-xhci1-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> + cp0_usb3_0_phy1: cp0_usb3_phy at 1 {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp0_reg_usb3_vbus1>;
> + };
> +
> + cp0_reg_sd_vccq: cp0_sd_vccq at 0 {
> + compatible = "regulator-gpio";
> + regulator-name = "cp0_sd_vccq";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
> + states = <1800000 0x1
> + 3300000 0x0>;
> + };
> +
> + cp0_reg_sd_vcc: cp0_sd_vcc at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp0_sd_vcc";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +*/
> +
> + cp0_sfp_eth0: sfp-eth at 0 {
> +// compatible = "sff,sfp";
> +// i2c-bus = <&cp0_sfpp0_i2c>;
> +// los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
> +// mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
> +// tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
> +// tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
> + /*
> + * SFP cages are unconnected on early PCBs because of an the I2C
> + * lanes not being connected. Prevent the port for being
> + * unusable by disabling the SFP node.
> + */
> +// status = "disabled";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&cp0_uart0 {
> + status = "okay";
> +};
> +
> +/* on-board eMMC - U9 */
> +&ap_sdhci0 {
> + pinctrl-names = "default";
> + bus-width = <8>;
> + status = "okay";
> + mmc-ddr-1_8v;
> + mmc-hs400-1_8v;
> +// vqmmc-supply = <&ap0_reg_sd_vccq>;
> +};
> +
> +&cp0_crypto {
> + status = "okay";
> +};
> +
> +&cp0_xmdio {
> + status = "okay";
> + phy0: ethernet-phy at 0 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <2>;
> + };
> + phy1: ethernet-phy at 1 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <0>;
> + };
> + phy2: ethernet-phy at 2 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <8>;
> + };
> +};
> +
> +&cp0_ethernet {
> + status = "okay";
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp0_eth0 {
> + status = "okay";
> + phy-mode = "2500base-x";
> + phys = <&cp0_comphy2 0>;
> +// phy = <&phy0>;
> + managed = "in-band-status";
> +};
> +
> +&cp0_eth1 {
> + status = "okay";
> + phy-mode = "2500base-x";
> + phys = <&cp0_comphy4 1>;
> +// phy = <&phy1>;
> + managed = "in-band-status";
> +};
> +
> +&cp0_eth2 {
> + status = "okay";
> + phy-mode = "2500base-x";
> + phys = <&cp0_comphy5 2>;
> +// phy = <&phy2>;
> + managed = "in-band-status";
> +};
> +
> +&cp0_gpio1 {
> + status = "okay";
> +};
> +
> +&cp0_gpio2 {
> + status = "okay";
> +};
> +
> +&cp0_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_i2c0_pins>;
> + status = "okay";
> + clock-frequency = <100000>;
> + rtc at 32 {
> + compatible = "epson,rx8130";
> + reg = <0x32>;
> + wakeup-source;
> + };
> +};
> +
> +/*
> +&cp0_i2c1 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + // SLM-1521-V2 - U3
> + i2c-mux at 72 { // verify address - depends on dpr
> + compatible = "nxp,pca9544";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x72>;
> + cp0_sfpp0_i2c: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + // U12
> + cp0_module_expander1: pca9555 at 21 {
> + compatible = "nxp,pca9555";
> + pinctrl-names = "default";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x21>;
> + };
> +
> + };
> + };
> +};
> +*/
> +
> +/*
> +&cp0_mdio {
> + status = "okay";
> +
> + phy0: ethernet-phy at 0 {
> + reg = <0>;
> + };
> +
> + phy1: ethernet-phy at 1 {
> + reg = <1>;
> + };
> +};
> +*/
> +
> +/* U54 */
> +/*
> +&cp0_nand_controller {
> + pinctrl-names = "default";
> + pinctrl-0 = <&nand_pins &nand_rb>;
> +
> + nand at 0 {
> + reg = <0>;
> + label = "main-storage";
> + nand-rb = <0>;
> + nand-ecc-mode = "hw";
> + nand-on-flash-bbt;
> + nand-ecc-strength = <8>;
> + nand-ecc-step-size = <512>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0 0x200000>;
> + };
> + partition at 200000 {
> + label = "Linux";
> + reg = <0x200000 0xd00000>;
> + };
> + partition at 1000000 {
> + label = "Filesystem";
> + reg = <0x1000000 0x3f000000>;
> + };
> + };
> + };
> +};
> +*/
> +
> +/* SLM-1521-V2, CON6 */
> +&cp0_pcie0 {
> + status = "okay";
> + num-lanes = <2>;
> + num-viewport = <8>;
> + /* Generic PHY, providing serdes lanes */
> + phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
> +};
> +
> +/*
> +&cp0_sata0 {
> + status = "okay";
> +
> + // SLM-1521-V2, CON2
> + sata-port at 1 {
> + status = "okay";
> + // Generic PHY, providing serdes lanes
> + phys = <&cp0_comphy5 1>;
> + };
> +};
> +*/
> +
> +/* CON 28 */
> +/*
> +&cp0_sdhci0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_sdhci_pins
> + &cp0_sdhci_cd_pins>;
> + bus-width = <4>;
> + cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + vqmmc-supply = <&cp0_reg_sd_vccq>;
> + vmmc-supply = <&cp0_reg_sd_vcc>;
> +};
> +*/
> +
> +/* U55 */
> +&cp0_spi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_spi0_pins>;
> + reg = <0x700680 0x50>, /* control */
> + <0x2000000 0x1000000>; /* CS0 */
> + status = "okay";
> +
> + spi-flash at 0 {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> + /* On-board MUX does not allow higher frequencies */
> + spi-max-frequency = <40000000>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0x0 0x1f0000>;
> + };
> + partition at 1f0000 {
> + label = "U-Boot ENV Factory";
> + reg = <0x1f0000 0x10000>;
> + };
> + partition at 200000 {
> + label = "Reserved";
> + reg = <0x200000 0x1f0000>;
> + };
> + partition at 3f0000 {
> + label = "U-Boot ENV";
> + reg = <0x3f0000 0x10000>;
> + };
> +
> + };
> + };
> +};
> +
> +&cp0_syscon0 {
> + cp0_pinctrl: pinctrl {
> + compatible = "marvell,cp115-standalone-pinctrl";
> +
> + cp0_i2c0_pins: cp0-i2c-pins-0 {
> + marvell,pins = "mpp37", "mpp38";
> + marvell,function = "i2c0";
> + };
> + cp0_i2c1_pins: cp0-i2c-pins-1 {
> + marvell,pins = "mpp35", "mpp36";
> + marvell,function = "i2c1";
> + };
> + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
> + marvell,pins = "mpp0", "mpp1", "mpp2",
> + "mpp3", "mpp4", "mpp5",
> + "mpp6", "mpp7", "mpp8",
> + "mpp9", "mpp10", "mpp11";
> + marvell,function = "ge0";
> + };
> + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
> + marvell,pins = "mpp44", "mpp45", "mpp46",
> + "mpp47", "mpp48", "mpp49",
> + "mpp50", "mpp51", "mpp52",
> + "mpp53", "mpp54", "mpp55";
> + marvell,function = "ge1";
> + };
> + cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
> + marvell,pins = "mpp43";
> + marvell,function = "gpio";
> + };
> + cp0_sdhci_pins: cp0-sdhi-pins-0 {
> + marvell,pins = "mpp56", "mpp57", "mpp58",
> + "mpp59", "mpp60", "mpp61";
> + marvell,function = "sdio";
> + };
> + cp0_spi0_pins: cp0-spi-pins-0 {
> + marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> + marvell,function = "spi1";
> + };
> + nand_pins: nand-pins {
> + marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
> + "mpp19", "mpp20", "mpp21", "mpp22",
> + "mpp23", "mpp24", "mpp25", "mpp26",
> + "mpp27";
> + marvell,function = "dev";
> + };
> + nand_rb: nand-rb {
> + marvell,pins = "mpp13";
> + marvell,function = "nf";
> + };
> + };
> +};
> +
> +/*
> +&cp0_usb3_0 {
> + status = "okay";
> + usb-phy = <&cp0_usb3_0_phy0>;
> + phy-names = "usb";
> +};
> +
> +&cp0_usb3_1 {
> + status = "okay";
> + usb-phy = <&cp0_usb3_0_phy1>;
> + phy-names = "usb";
> +};
> +*/
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts
> new file mode 100644
> index 0000000000..3010c59ca3
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts
> @@ -0,0 +1,243 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9131-DB board.
> + */
> +
> +#include "puzzle-m901-cn9130-db.dts"
> +
> +/ {
> + model = "Puzzle-M901";
> + compatible = "marvell,cn9131", "marvell,cn9130",
> + "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> + aliases {
> + i2c0 = &cp1_i2c0;
> + ethernet3 = &cp1_eth0;
> + ethernet4 = &cp1_eth1;
> + ethernet5 = &cp1_eth2;
> + gpio3 = &cp1_gpio1;
> + gpio4 = &cp1_gpio2;
> + };
> +
> + cp1_reg_usb3_vbus0: cp1_usb3_vbus at 0 {
> +/*
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_xhci0_vbus_pins>;
> + regulator-name = "cp1-xhci0-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
> +*/
> + };
> +
> + cp1_usb3_0_phy0: cp1_usb3_phy0 {
> +/*
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp1_reg_usb3_vbus0>;
> +*/
> + };
> +
> + cp1_sfp_eth1: sfp-eth1 {
> +/*
> + compatible = "sff,sfp";
> + i2c-bus = <&cp1_i2c0>;
> + los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
> + mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
> + tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
> + tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_sfp_pins>;
> +*/
> + /*
> + * SFP cages are unconnected on early PCBs because of an the I2C
> + * lanes not being connected. Prevent the port for being
> + * unusable by disabling the SFP node.
> + */
> +// status = "disabled";
> + };
> +};
> +
> +/*
> + * Instantiate the first slave CP115
> + */
> +
> +#define CP11X_NAME cp1
> +#define CP11X_BASE f6000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE f6600000
> +#define CP11X_PCIE1_BASE f6620000
> +#define CP11X_PCIE2_BASE f6640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp1_crypto {
> + status = "okay";
> +};
> +
> +&cp1_xmdio {
> + status = "okay";
> + cp1_nbaset_phy0: ethernet-phy at 3 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <2>;
> + };
> + cp1_nbaset_phy1: ethernet-phy at 4 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <0>;
> + };
> + cp1_nbaset_phy2: ethernet-phy at 5 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <8>;
> + };
> +};
> +
> +&cp1_ethernet {
> + status = "okay";
> +};
> +
> +/* CON50 */
> +&cp1_eth0 {
> + status = "okay";
> +// phy = <&cp1_nbaset_phy0>;
> + phy-mode = "2500base-x";
> + phys = <&cp1_comphy2 0>;
> + managed = "in-band-status";
> +};
> +
> +&cp1_eth1 {
> + status = "okay";
> +// phy = <&cp1_nbaset_phy1>;
> + phy-mode = "2500base-x";
> + phys = <&cp1_comphy4 1>;
> + managed = "in-band-status";
> +};
> +
> +&cp1_eth2 {
> + status = "okay";
> +// phy = <&cp1_nbaset_phy2>;
> + phy-mode = "2500base-x";
> + phys = <&cp1_comphy5 2>;
> + managed = "in-band-status";
> +};
> +
> +&cp1_sata0 {
> + status = "okay";
> + sata-port at 1 {
> + status = "okay";
> + phys = <&cp1_comphy0 1>;
> + };
> +};
> +
> +&cp1_gpio1 {
> + status = "okay";
> +};
> +
> +&cp1_gpio2 {
> + status = "okay";
> +};
> +
> +&cp1_i2c0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_i2c0_pins>;
> + clock-frequency = <100000>;
> +};
> +
> +/* CON40 */
> +/*
> +&cp1_pcie0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_pcie_reset_pins>;
> + num-lanes = <2>;
> + num-viewport = <8>;
> + marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> + // Generic PHY, providing serdes lanes
> + phys = <&cp1_comphy0 0
> + &cp1_comphy1 0>;
> +};
> +*/
> +
> +/* U24 */
> +/*
> +&cp1_spi1 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_spi0_pins>;
> + reg = <0x700680 0x50>;
> +
> + spi-flash at 0 {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> + // On-board MUX does not allow higher frequencies
> + spi-max-frequency = <40000000>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot-1";
> + reg = <0x0 0x200000>;
> + };
> +
> + partition at 400000 {
> + label = "Filesystem-1";
> + reg = <0x200000 0xe00000>;
> + };
> + };
> + };
> +
> +};
> +*/
> +
> +&cp1_syscon0 {
> + cp1_pinctrl: pinctrl {
> + compatible = "marvell,cp115-standalone-pinctrl";
> +
> + cp1_i2c0_pins: cp1-i2c-pins-0 {
> + marvell,pins = "mpp37", "mpp38";
> + marvell,function = "i2c0";
> + };
> + cp1_spi0_pins: cp1-spi-pins-0 {
> + marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> + marvell,function = "spi1";
> + };
> + cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
> + marvell,pins = "mpp3";
> + marvell,function = "gpio";
> + };
> + cp1_sfp_pins: sfp-pins {
> + marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
> + marvell,function = "gpio";
> + };
> + cp1_pcie_reset_pins: cp1-pcie-reset-pins {
> + marvell,pins = "mpp0";
> + marvell,function = "gpio";
> + };
> + };
> +};
> +
> +/* CON58 */
> +&cp1_usb3_1 {
> + status = "okay";
> +// usb-phy = <&cp1_usb3_0_phy1>;
> + phys = <&cp1_comphy3 1>;
> + phy-names = "usb";
> +};
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts
> new file mode 100644
> index 0000000000..62eaabc741
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts
> @@ -0,0 +1,430 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9130-DB board.
> + */
> +
> +#include "puzzle-cn9130.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Puzzle-M902";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + aliases {
> + i2c0 = &cp0_i2c0;
> + ethernet0 = &cp0_eth0;
> + ethernet1 = &cp0_eth1;
> + ethernet2 = &cp0_eth2;
> + gpio1 = &cp0_gpio1;
> + gpio2 = &cp0_gpio2;
> + spi1 = &cp0_spi0;
> + spi2 = &cp0_spi1;
> + serial1 = &cp0_uart0;
> + };
> +
> + memory at 00000000 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>;
> + };
> +
> + ap0_reg_sd_vccq: ap0_sd_vccq at 0 {
> +// compatible = "regulator-gpio";
> +// regulator-name = "ap0_sd_vccq";
> +// regulator-min-microvolt = <1800000>;
> +// regulator-max-microvolt = <3300000>;
> +// gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
> +// states = <1800000 0x1 3300000 0x0>;
> + };
> +
> +/*
> + cp0_reg_usb3_vbus0: cp0_usb3_vbus at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp0-xhci0-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
> + };
> +
> + cp0_usb3_0_phy0: cp0_usb3_phy at 0 {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp0_reg_usb3_vbus0>;
> + };
> +
> + cp0_reg_usb3_vbus1: cp0_usb3_vbus at 1 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp0-xhci1-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> + cp0_usb3_0_phy1: cp0_usb3_phy at 1 {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp0_reg_usb3_vbus1>;
> + };
> +
> + cp0_reg_sd_vccq: cp0_sd_vccq at 0 {
> + compatible = "regulator-gpio";
> + regulator-name = "cp0_sd_vccq";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
> + states = <1800000 0x1
> + 3300000 0x0>;
> + };
> +
> + cp0_reg_sd_vcc: cp0_sd_vcc at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp0_sd_vcc";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +*/
> +
> + cp0_sfp_eth0: sfp-eth at 0 {
> +// compatible = "sff,sfp";
> +// i2c-bus = <&cp0_sfpp0_i2c>;
> +// los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
> +// mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
> +// tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
> +// tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
> + /*
> + * SFP cages are unconnected on early PCBs because of an the I2C
> + * lanes not being connected. Prevent the port for being
> + * unusable by disabling the SFP node.
> + */
> +// status = "disabled";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&cp0_uart0 {
> + status = "okay";
> +};
> +
> +/* on-board eMMC - U9 */
> +&ap_sdhci0 {
> + pinctrl-names = "default";
> + bus-width = <8>;
> + status = "okay";
> + mmc-ddr-1_8v;
> + mmc-hs400-1_8v;
> +// vqmmc-supply = <&ap0_reg_sd_vccq>;
> +};
> +
> +
> +&cp0_crypto {
> + status = "okay";
> +};
> +
> +&cp0_xmdio {
> + status = "okay";
> + phy0: ethernet-phy at 0 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <2>;
> + };
> + phy1: ethernet-phy at 1 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <0>;
> + };
> + phy2: ethernet-phy at 2 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <8>;
> + };
> +};
> +
> +&cp0_ethernet {
> + status = "okay";
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp0_eth0 {
> + status = "okay";
> + phy-mode = "10gbase-kr";
> + phys = <&cp0_comphy2 0>;
> +// phy = <&phy0>;
> + managed = "in-band-status";
> +};
> +
> +&cp0_eth1 {
> + status = "okay";
> + phy-mode = "2500base-x";
> + phys = <&cp0_comphy4 1>;
> +// phy = <&phy1>;
> + managed = "in-band-status";
> +};
> +
> +&cp0_eth2 {
> + status = "okay";
> + phy-mode = "2500base-x";
> + phys = <&cp0_comphy1 2>;
> +// phy = <&phy2>;
> + managed = "in-band-status";
> +};
> +
> +&cp0_gpio1 {
> + status = "okay";
> +};
> +
> +&cp0_gpio2 {
> + status = "okay";
> +};
> +
> +&cp0_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_i2c0_pins>;
> + status = "okay";
> + clock-frequency = <100000>;
> + rtc at 32 {
> + compatible = "epson,rx8130";
> + reg = <0x32>;
> + wakeup-source;
> + };
> +};
> +
> +&cp0_i2c1 {
> + clock-frequency = <100000>;
> +};
> +
> +/*
> +&cp0_i2c1 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + // SLM-1521-V2 - U3
> + i2c-mux at 72 { // verify address - depends on dpr
> + compatible = "nxp,pca9544";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x72>;
> + cp0_sfpp0_i2c: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + // U12
> + cp0_module_expander1: pca9555 at 21 {
> + compatible = "nxp,pca9555";
> + pinctrl-names = "default";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x21>;
> + };
> +
> + };
> + };
> +};
> +*/
> +
> +/*
> +&cp0_mdio {
> + status = "okay";
> +
> + phy0: ethernet-phy at 0 {
> + reg = <0>;
> + };
> +
> + phy1: ethernet-phy at 1 {
> + reg = <1>;
> + };
> +};
> +*/
> +
> +/* U54 */
> +/*
> +&cp0_nand_controller {
> + pinctrl-names = "default";
> + pinctrl-0 = <&nand_pins &nand_rb>;
> +
> + nand at 0 {
> + reg = <0>;
> + label = "main-storage";
> + nand-rb = <0>;
> + nand-ecc-mode = "hw";
> + nand-on-flash-bbt;
> + nand-ecc-strength = <8>;
> + nand-ecc-step-size = <512>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0 0x200000>;
> + };
> + partition at 200000 {
> + label = "Linux";
> + reg = <0x200000 0xd00000>;
> + };
> + partition at 1000000 {
> + label = "Filesystem";
> + reg = <0x1000000 0x3f000000>;
> + };
> + };
> + };
> +};
> +*/
> +
> +/* SLM-1521-V2, CON6 */
> +&cp0_sata0 {
> + status = "okay";
> + sata-port at 1 {
> + status = "okay";
> + phys = <&cp0_comphy0 1>;
> + };
> +};
> +
> +&cp0_pcie2 {
> + status = "okay";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + /* Generic PHY, providing serdes lanes */
> + phys = <&cp0_comphy5 2>;
> +};
> +
> +/* CON 28 */
> +/*
> +&cp0_sdhci0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_sdhci_pins
> + &cp0_sdhci_cd_pins>;
> + bus-width = <4>;
> + cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + vqmmc-supply = <&cp0_reg_sd_vccq>;
> + vmmc-supply = <&cp0_reg_sd_vcc>;
> +};
> +*/
> +
> +/* U55 */
> +&cp0_spi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_spi0_pins>;
> + reg = <0x700680 0x50>, /* control */
> + <0x2000000 0x1000000>; /* CS0 */
> + status = "okay";
> +
> + spi-flash at 0 {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> + /* On-board MUX does not allow higher frequencies */
> + spi-max-frequency = <40000000>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0x0 0x1f0000>;
> + };
> + partition at 1f0000 {
> + label = "U-Boot ENV Factory";
> + reg = <0x1f0000 0x10000>;
> + };
> + partition at 200000 {
> + label = "Reserved";
> + reg = <0x200000 0x1f0000>;
> + };
> + partition at 3f0000 {
> + label = "U-Boot ENV";
> + reg = <0x3f0000 0x10000>;
> + };
> +
> + };
> + };
> +};
> +
> +&cp0_syscon0 {
> + cp0_pinctrl: pinctrl {
> + compatible = "marvell,cp115-standalone-pinctrl";
> +
> + cp0_i2c0_pins: cp0-i2c-pins-0 {
> + marvell,pins = "mpp37", "mpp38";
> + marvell,function = "i2c0";
> + };
> + cp0_i2c1_pins: cp0-i2c-pins-1 {
> + marvell,pins = "mpp35", "mpp36";
> + marvell,function = "i2c1";
> + };
> + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
> + marvell,pins = "mpp0", "mpp1", "mpp2",
> + "mpp3", "mpp4", "mpp5",
> + "mpp6", "mpp7", "mpp8",
> + "mpp9", "mpp10", "mpp11";
> + marvell,function = "ge0";
> + };
> + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
> + marvell,pins = "mpp44", "mpp45", "mpp46",
> + "mpp47", "mpp48", "mpp49",
> + "mpp50", "mpp51", "mpp52",
> + "mpp53", "mpp54", "mpp55";
> + marvell,function = "ge1";
> + };
> + cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
> + marvell,pins = "mpp43";
> + marvell,function = "gpio";
> + };
> + cp0_sdhci_pins: cp0-sdhi-pins-0 {
> + marvell,pins = "mpp56", "mpp57", "mpp58",
> + "mpp59", "mpp60", "mpp61";
> + marvell,function = "sdio";
> + };
> + cp0_spi0_pins: cp0-spi-pins-0 {
> + marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> + marvell,function = "spi1";
> + };
> + nand_pins: nand-pins {
> + marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
> + "mpp19", "mpp20", "mpp21", "mpp22",
> + "mpp23", "mpp24", "mpp25", "mpp26",
> + "mpp27";
> + marvell,function = "dev";
> + };
> + nand_rb: nand-rb {
> + marvell,pins = "mpp13";
> + marvell,function = "nf";
> + };
> + };
> +};
> +
> +/*
> +&cp0_usb3_0 {
> + status = "okay";
> + usb-phy = <&cp0_usb3_0_phy0>;
> + phy-names = "usb";
> +};
> +*/
> +
> +&cp0_usb3_1 {
> + status = "okay";
> +// usb-phy = <&cp0_usb3_0_phy1>;
> + phys = <&cp0_comphy3 1>;
> + phy-names = "usb";
> +};
> +
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts
> new file mode 100644
> index 0000000000..87c7c8fe67
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts
> @@ -0,0 +1,247 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9131-DB board.
> + */
> +
> +#include "puzzle-m902-cn9130-db.dts"
> +
> +/ {
> + model = "Puzzle-M902";
> + compatible = "marvell,cn9131", "marvell,cn9130",
> + "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> + aliases {
> + i2c0 = &cp1_i2c0;
> + ethernet3 = &cp1_eth0;
> + ethernet4 = &cp1_eth1;
> + ethernet5 = &cp1_eth2;
> + gpio3 = &cp1_gpio1;
> + gpio4 = &cp1_gpio2;
> + };
> +
> + cp1_reg_usb3_vbus0: cp1_usb3_vbus at 0 {
> +/*
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_xhci0_vbus_pins>;
> + regulator-name = "cp1-xhci0-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
> +*/
> + };
> +
> + cp1_usb3_0_phy0: cp1_usb3_phy0 {
> +/*
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp1_reg_usb3_vbus0>;
> +*/
> + };
> +
> + cp1_sfp_eth1: sfp-eth1 {
> +/*
> + compatible = "sff,sfp";
> + i2c-bus = <&cp1_i2c0>;
> + los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
> + mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
> + tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
> + tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_sfp_pins>;
> +*/
> + /*
> + * SFP cages are unconnected on early PCBs because of an the I2C
> + * lanes not being connected. Prevent the port for being
> + * unusable by disabling the SFP node.
> + */
> +// status = "disabled";
> + };
> +};
> +
> +/*
> + * Instantiate the first slave CP115
> + */
> +
> +#define CP11X_NAME cp1
> +#define CP11X_BASE f4000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE f4600000
> +#define CP11X_PCIE1_BASE f4620000
> +#define CP11X_PCIE2_BASE f4640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp1_crypto {
> + status = "okay";
> +};
> +
> +&cp1_xmdio {
> + status = "okay";
> + cp1_nbaset_phy0: ethernet-phy at 3 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <2>;
> + };
> + cp1_nbaset_phy1: ethernet-phy at 4 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <0>;
> + };
> + cp1_nbaset_phy2: ethernet-phy at 5 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <8>;
> + };
> +};
> +
> +&cp1_ethernet {
> + status = "okay";
> +};
> +
> +/* CON50 */
> +&cp1_eth0 {
> + status = "okay";
> +// phy = <&cp1_nbaset_phy0>;
> + phy-mode = "10gbase-kr";
> + phys = <&cp1_comphy2 0>;
> + managed = "in-band-status";
> +};
> +
> +&cp1_eth1 {
> + status = "okay";
> +// phy = <&cp1_nbaset_phy1>;
> + phy-mode = "2500base-x";
> + phys = <&cp1_comphy4 1>;
> + managed = "in-band-status";
> +};
> +
> +&cp1_eth2 {
> + status = "okay";
> +// phy = <&cp1_nbaset_phy2>;
> + phy-mode = "2500base-x";
> + phys = <&cp1_comphy1 2>;
> + managed = "in-band-status";
> +};
> +
> +/*
> +&cp1_sata0 {
> + status = "okay";
> + sata-port at 1 {
> + status = "okay";
> + phys = <&cp1_comphy0 1>;
> + };
> +};
> +*/
> +
> +&cp1_gpio1 {
> + status = "okay";
> +};
> +
> +&cp1_gpio2 {
> + status = "okay";
> +};
> +
> +&cp1_i2c0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_i2c0_pins>;
> + clock-frequency = <100000>;
> +};
> +
> +/* CON40 */
> +/*
> +&cp1_pcie0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_pcie_reset_pins>;
> + num-lanes = <2>;
> + num-viewport = <8>;
> + marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> + // Generic PHY, providing serdes lanes
> + phys = <&cp1_comphy0 0
> + &cp1_comphy1 0>;
> +};
> +*/
> +
> +/* U24 */
> +/*
> +&cp1_spi1 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp1_spi0_pins>;
> + reg = <0x700680 0x50>;
> +
> + spi-flash at 0 {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> + // On-board MUX does not allow higher frequencies
> + spi-max-frequency = <40000000>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot-1";
> + reg = <0x0 0x200000>;
> + };
> +
> + partition at 400000 {
> + label = "Filesystem-1";
> + reg = <0x200000 0xe00000>;
> + };
> + };
> + };
> +
> +};
> +*/
> +
> +&cp1_syscon0 {
> + cp1_pinctrl: pinctrl {
> + compatible = "marvell,cp115-standalone-pinctrl";
> +
> + cp1_i2c0_pins: cp1-i2c-pins-0 {
> + marvell,pins = "mpp37", "mpp38";
> + marvell,function = "i2c0";
> + };
> + cp1_spi0_pins: cp1-spi-pins-0 {
> + marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> + marvell,function = "spi1";
> + };
> + cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
> + marvell,pins = "mpp3";
> + marvell,function = "gpio";
> + };
> + cp1_sfp_pins: sfp-pins {
> + marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
> + marvell,function = "gpio";
> + };
> + cp1_pcie_reset_pins: cp1-pcie-reset-pins {
> + marvell,pins = "mpp0";
> + marvell,function = "gpio";
> + };
> + };
> +};
> +
> +/* CON58 */
> +/*
> +&cp1_usb3_1 {
> + status = "okay";
> +// usb-phy = <&cp1_usb3_0_phy1>;
> + phys = <&cp1_comphy3 1>;
> + phy-names = "usb";
> +};
> +*/
> +
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts
> new file mode 100644
> index 0000000000..e144865686
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts
> @@ -0,0 +1,261 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9132-DB board.
> + */
> +
> +#include "puzzle-m902-cn9131-db.dts"
> +
> +/ {
> + model = "Puzzle-M902";
> + compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
> + "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> + aliases {
> + gpio5 = &cp2_gpio1;
> + gpio6 = &cp2_gpio2;
> + ethernet6 = &cp2_eth0;
> + ethernet7 = &cp2_eth1;
> + ethernet8 = &cp2_eth2;
> + };
> +
> + cp2_reg_usb3_vbus0: cp2_usb3_vbus at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp2-xhci0-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
> + };
> +
> + cp2_usb3_0_phy0: cp2_usb3_phy0 {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp2_reg_usb3_vbus0>;
> + };
> +
> + cp2_reg_usb3_vbus1: cp2_usb3_vbus at 1 {
> + compatible = "regulator-fixed";
> + regulator-name = "cp2-xhci1-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
> + };
> +
> + cp2_usb3_0_phy1: cp2_usb3_phy1 {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <&cp2_reg_usb3_vbus1>;
> + };
> +
> + cp2_reg_sd_vccq: cp2_sd_vccq at 0 {
> + compatible = "regulator-gpio";
> + regulator-name = "cp2_sd_vcc";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
> + states = <1800000 0x1 3300000 0x0>;
> + };
> +
> + cp2_sfp_eth0: sfp-eth0 {
> + compatible = "sff,sfp";
> + i2c-bus = <&cp2_sfpp0_i2c>;
> + los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
> + mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
> + tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
> + tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
> + /*
> + * SFP cages are unconnected on early PCBs because of an the I2C
> + * lanes not being connected. Prevent the port for being
> + * unusable by disabling the SFP node.
> + */
> + status = "disabled";
> + };
> +};
> +
> +/*
> + * Instantiate the second slave CP115
> + */
> +
> +#define CP11X_NAME cp2
> +#define CP11X_BASE f6000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE f6600000
> +#define CP11X_PCIE1_BASE f6620000
> +#define CP11X_PCIE2_BASE f6640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp2_crypto {
> + status = "okay";
> +};
> +
> +&cp2_ethernet {
> + status = "okay";
> +};
> +
> +&cp2_xmdio {
> + status = "okay";
> + cp2_nbaset_phy0: ethernet-phy at 6 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <2>;
> + };
> + cp2_nbaset_phy1: ethernet-phy at 7 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <0>;
> + };
> + cp2_nbaset_phy2: ethernet-phy at 8 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <8>;
> + };
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp2_eth0 {
> + status = "okay";
> +// phy = <&cp2_nbaset_phy0>;
> + phy-mode = "10gbase-kr";
> + phys = <&cp2_comphy2 0>;
> + managed = "in-band-status";
> +};
> +
> +&cp2_eth1 {
> + status = "okay";
> +// phy = <&cp2_nbaset_phy1>;
> + phy-mode = "2500base-x";
> + phys = <&cp2_comphy4 1>;
> + managed = "in-band-status";
> +};
> +
> +&cp2_eth2 {
> + status = "okay";
> +// phy = <&cp2_nbaset_phy2>;
> + phy-mode = "2500base-x";
> + phys = <&cp2_comphy1 2>;
> + managed = "in-band-status";
> +};
> +
> +&cp2_gpio1 {
> + status = "okay";
> +};
> +
> +&cp2_gpio2 {
> + status = "okay";
> +};
> +
> +&cp2_i2c0 {
> + clock-frequency = <100000>;
> +
> + /* SLM-1521-V2 - U3 */
> + i2c-mux at 72 {
> + compatible = "nxp,pca9544";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x72>;
> + cp2_sfpp0_i2c: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /* U12 */
> + cp2_module_expander1: pca9555 at 21 {
> + compatible = "nxp,pca9555";
> + pinctrl-names = "default";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x21>;
> + };
> + };
> + };
> +};
> +
> +/* SLM-1521-V2, CON6 */
> +/*
> +&cp2_pcie0 {
> + status = "okay";
> + num-lanes = <2>;
> + num-viewport = <8>;
> + // Generic PHY, providing serdes lanes
> + phys = <&cp2_comphy0 0
> + &cp2_comphy1 0>;
> +};
> +*/
> +
> +/* SLM-1521-V2, CON8 */
> +/*
> +&cp2_pcie2 {
> + status = "okay";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + // Generic PHY, providing serdes lanes
> + phys = <&cp2_comphy5 2>;
> +};
> +
> +&cp2_sata0 {
> + status = "okay";
> +
> + // SLM-1521-V2, CON4
> + sata-port at 0 {
> + // Generic PHY, providing serdes lanes
> + phys = <&cp2_comphy2 0>;
> + };
> +};
> +*/
> +
> +/* CON 2 on SLM-1683 - microSD */
> +&cp2_sdhci0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp2_sdhci_pins>;
> + bus-width = <4>;
> + cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
> + vqmmc-supply = <&cp2_reg_sd_vccq>;
> +};
> +
> +&cp2_syscon0 {
> + cp2_pinctrl: pinctrl {
> + compatible = "marvell,cp115-standalone-pinctrl";
> +
> + cp2_i2c0_pins: cp2-i2c-pins-0 {
> + marvell,pins = "mpp37", "mpp38";
> + marvell,function = "i2c0";
> + };
> + cp2_sdhci_pins: cp2-sdhi-pins-0 {
> + marvell,pins = "mpp56", "mpp57", "mpp58",
> + "mpp59", "mpp60", "mpp61";
> + marvell,function = "sdio";
> + };
> + };
> +};
> +
> +/*
> +&cp2_usb3_0 {
> + status = "okay";
> + usb-phy = <&cp2_usb3_0_phy0>;
> + phy-names = "usb";
> +};
> +*/
> +
> +/* SLM-1521-V2, CON11 */
> +/*
> +&cp2_usb3_1 {
> + status = "okay";
> + usb-phy = <&cp2_usb3_0_phy1>;
> + phy-names = "usb";
> + // Generic PHY, providing serdes lanes
> + phys = <&cp2_comphy3 1>;
> +};
> +*/
> diff --git a/target/linux/mvebu/files/drivers/rtc/Kconfig b/target/linux/mvebu/files/drivers/rtc/Kconfig
> new file mode 100644
> index 0000000000..15487edb43
> --- /dev/null
> +++ b/target/linux/mvebu/files/drivers/rtc/Kconfig
> @@ -0,0 +1,1943 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# RTC class/drivers configuration
> +#
> +
> +config RTC_LIB
> + bool
> +
> +config RTC_MC146818_LIB
> + bool
> + select RTC_LIB
> +
> +menuconfig RTC_CLASS
> + bool "Real Time Clock"
> + default n
> + depends on !S390 && !UML
> + select RTC_LIB
> + help
> + Generic RTC class support. If you say yes here, you will
> + be allowed to plug one or more RTCs to your system. You will
> + probably want to enable one or more of the interfaces below.
> +
> +if RTC_CLASS
> +
> +config RTC_HCTOSYS
> + bool "Set system time from RTC on startup and resume"
> + default y
> + help
> + If you say yes here, the system time (wall clock) will be set using
> + the value read from a specified RTC device. This is useful to avoid
> + unnecessary fsck runs at boot time, and to network better.
> +
> +config RTC_HCTOSYS_DEVICE
> + string "RTC used to set the system time"
> + depends on RTC_HCTOSYS
> + default "rtc0"
> + help
> + The RTC device that will be used to (re)initialize the system
> + clock, usually rtc0. Initialization is done when the system
> + starts up, and when it resumes from a low power state. This
> + device should record time in UTC, since the kernel won't do
> + timezone correction.
> +
> + The driver for this RTC device must be loaded before late_initcall
> + functions run, so it must usually be statically linked.
> +
> + This clock should be battery-backed, so that it reads the correct
> + time when the system boots from a power-off state. Otherwise, your
> + system will need an external clock source (like an NTP server).
> +
> + If the clock you specify here is not battery backed, it may still
> + be useful to reinitialize system time when resuming from system
> + sleep states. Do not specify an RTC here unless it stays powered
> + during all this system's supported sleep states.
> +
> +config RTC_SYSTOHC
> + bool "Set the RTC time based on NTP synchronization"
> + default y
> + help
> + If you say yes here, the system time (wall clock) will be stored
> + in the RTC specified by RTC_HCTOSYS_DEVICE approximately every 11
> + minutes if userspace reports synchronized NTP status.
> +
> +config RTC_SYSTOHC_DEVICE
> + string "RTC used to synchronize NTP adjustment"
> + depends on RTC_SYSTOHC
> + default RTC_HCTOSYS_DEVICE if RTC_HCTOSYS
> + default "rtc0"
> + help
> + The RTC device used for NTP synchronization. The main difference
> + between RTC_HCTOSYS_DEVICE and RTC_SYSTOHC_DEVICE is that this
> + one can sleep when setting time, because it runs in the workqueue
> + context.
> +
> +config RTC_DEBUG
> + bool "RTC debug support"
> + help
> + Say yes here to enable debugging support in the RTC framework
> + and individual RTC drivers.
> +
> +config RTC_NVMEM
> + bool "RTC non volatile storage support"
> + select NVMEM
> + default RTC_CLASS
> + help
> + Say yes here to add support for the non volatile (often battery
> + backed) storage present on RTCs.
> +
> +comment "RTC interfaces"
> +
> +config RTC_INTF_SYSFS
> + bool "/sys/class/rtc/rtcN (sysfs)"
> + depends on SYSFS
> + default RTC_CLASS
> + help
> + Say yes here if you want to use your RTCs using sysfs interfaces,
> + /sys/class/rtc/rtc0 through /sys/.../rtcN.
> +
> + If unsure, say Y.
> +
> +config RTC_INTF_PROC
> + bool "/proc/driver/rtc (procfs for rtcN)"
> + depends on PROC_FS
> + default RTC_CLASS
> + help
> + Say yes here if you want to use your system clock RTC through
> + the proc interface, /proc/driver/rtc.
> + Other RTCs will not be available through that API.
> + If there is no RTC for the system clock, then the first RTC(rtc0)
> + is used by default.
> +
> + If unsure, say Y.
> +
> +config RTC_INTF_DEV
> + bool "/dev/rtcN (character devices)"
> + default RTC_CLASS
> + help
> + Say yes here if you want to use your RTCs using the /dev
> + interfaces, which "udev" sets up as /dev/rtc0 through
> + /dev/rtcN.
> +
> + You may want to set up a symbolic link so one of these
> + can be accessed as /dev/rtc, which is a name
> + expected by "hwclock" and some other programs. Recent
> + versions of "udev" are known to set up the symlink for you.
> +
> + If unsure, say Y.
> +
> +config RTC_INTF_DEV_UIE_EMUL
> + bool "RTC UIE emulation on dev interface"
> + depends on RTC_INTF_DEV
> + help
> + Provides an emulation for RTC_UIE if the underlying rtc chip
> + driver does not expose RTC_UIE ioctls. Those requests generate
> + once-per-second update interrupts, used for synchronization.
> +
> + The emulation code will read the time from the hardware
> + clock several times per second, please enable this option
> + only if you know that you really need it.
> +
> +config RTC_DRV_TEST
> + tristate "Test driver/device"
> + help
> + If you say yes here you get support for the
> + RTC test driver. It's a software RTC which can be
> + used to test the RTC subsystem APIs. It gets
> + the time from the system clock.
> + You want this driver only if you are doing development
> + on the RTC subsystem. Please read the source code
> + for further details.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-test.
> +
> +comment "I2C RTC drivers"
> +
> +if I2C
> +
> +config RTC_DRV_88PM860X
> + tristate "Marvell 88PM860x"
> + depends on MFD_88PM860X
> + help
> + If you say yes here you get support for RTC function in Marvell
> + 88PM860x chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-88pm860x.
> +
> +config RTC_DRV_88PM80X
> + tristate "Marvell 88PM80x"
> + depends on MFD_88PM800
> + help
> + If you say yes here you get support for RTC function in Marvell
> + 88PM80x chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-88pm80x.
> +
> +config RTC_DRV_ABB5ZES3
> + select REGMAP_I2C
> + tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3"
> + help
> + If you say yes here you get support for the Abracon
> + AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ab-b5ze-s3.
> +
> +config RTC_DRV_ABEOZ9
> + select REGMAP_I2C
> + tristate "Abracon AB-RTCMC-32.768kHz-EOZ9"
> + help
> + If you say yes here you get support for the Abracon
> + AB-RTCMC-32.768kHz-EOA9 I2C RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ab-e0z9.
> +
> +config RTC_DRV_ABX80X
> + tristate "Abracon ABx80x"
> + select WATCHDOG_CORE if WATCHDOG
> + help
> + If you say yes here you get support for Abracon AB080X and AB180X
> + families of ultra-low-power battery- and capacitor-backed real-time
> + clock chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-abx80x.
> +
> +config RTC_DRV_AC100
> + tristate "X-Powers AC100"
> + depends on MFD_AC100
> + help
> + If you say yes here you get support for the real-time clock found
> + in X-Powers AC100 family peripheral ICs.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ac100.
> +
> +config RTC_DRV_BRCMSTB
> + tristate "Broadcom STB wake-timer"
> + depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
> + default ARCH_BRCMSTB || BMIPS_GENERIC
> + help
> + If you say yes here you get support for the wake-timer found on
> + Broadcom STB SoCs (BCM7xxx).
> +
> + This driver can also be built as a module. If so, the module will
> + be called rtc-brcmstb-waketimer.
> +
> +config RTC_DRV_AS3722
> + tristate "ams AS3722 RTC driver"
> + depends on MFD_AS3722
> + help
> + If you say yes here you get support for the RTC of ams AS3722 PMIC
> + chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-as3722.
> +
> +config RTC_DRV_DS1307
> + tristate "Dallas/Maxim DS1307/37/38/39/40/41, ST M41T00, EPSON RX-8025, ISL12057"
> + select REGMAP_I2C
> + help
> + If you say yes here you get support for various compatible RTC
> + chips (often with battery backup) connected with I2C. This driver
> + should handle DS1307, DS1337, DS1338, DS1339, DS1340, DS1341,
> + ST M41T00, EPSON RX-8025, Intersil ISL12057 and probably other chips.
> + In some cases the RTC must already have been initialized (by
> + manufacturing or a bootloader).
> +
> + The first seven registers on these chips hold an RTC, and other
> + registers may add features such as NVRAM, a trickle charger for
> + the RTC/NVRAM backup power, and alarms. NVRAM is visible in
> + sysfs, but other chip features may not be available.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1307.
> +
> +config RTC_DRV_DS1307_CENTURY
> + bool "Century bit support for rtc-ds1307"
> + depends on RTC_DRV_DS1307
> + default n
> + help
> + The DS1307 driver suffered from a bug where it was enabling the
> + century bit inconditionnally but never used it when reading the time.
> + It made the driver unable to support dates beyond 2099.
> + Setting this option will add proper support for the century bit but if
> + the time was previously set using a kernel predating this option,
> + reading the date will return a date in the next century.
> + To solve that, you could boot a kernel without this option set, set
> + the RTC date and then boot a kernel with this option set.
> +
> +config RTC_DRV_DS1374
> + tristate "Dallas/Maxim DS1374"
> + help
> + If you say yes here you get support for Dallas Semiconductor
> + DS1374 real-time clock chips. If an interrupt is associated
> + with the device, the alarm functionality is supported.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1374.
> +
> +config RTC_DRV_DS1374_WDT
> + bool "Dallas/Maxim DS1374 watchdog timer"
> + depends on RTC_DRV_DS1374
> + help
> + If you say Y here you will get support for the
> + watchdog timer in the Dallas Semiconductor DS1374
> + real-time clock chips.
> +
> +config RTC_DRV_DS1672
> + tristate "Dallas/Maxim DS1672"
> + help
> + If you say yes here you get support for the
> + Dallas/Maxim DS1672 timekeeping chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1672.
> +
> +config RTC_DRV_HYM8563
> + tristate "Haoyu Microelectronics HYM8563"
> + depends on OF
> + help
> + Say Y to enable support for the HYM8563 I2C RTC chip. Apart
> + from the usual rtc functions it provides a clock output of
> + up to 32kHz.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-hym8563.
> +
> +config RTC_DRV_LP8788
> + tristate "TI LP8788 RTC driver"
> + depends on MFD_LP8788
> + help
> + Say Y to enable support for the LP8788 RTC/ALARM driver.
> +
> +config RTC_DRV_MAX6900
> + tristate "Maxim MAX6900"
> + help
> + If you say yes here you will get support for the
> + Maxim MAX6900 I2C RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max6900.
> +
> +config RTC_DRV_MAX8907
> + tristate "Maxim MAX8907"
> + depends on MFD_MAX8907 || COMPILE_TEST
> + select REGMAP_IRQ
> + help
> + If you say yes here you will get support for the
> + RTC of Maxim MAX8907 PMIC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max8907.
> +
> +config RTC_DRV_MAX8925
> + tristate "Maxim MAX8925"
> + depends on MFD_MAX8925
> + help
> + If you say yes here you will get support for the
> + RTC of Maxim MAX8925 PMIC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max8925.
> +
> +config RTC_DRV_MAX8998
> + tristate "Maxim MAX8998"
> + depends on MFD_MAX8998
> + help
> + If you say yes here you will get support for the
> + RTC of Maxim MAX8998 PMIC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max8998.
> +
> +config RTC_DRV_MAX8997
> + tristate "Maxim MAX8997"
> + depends on MFD_MAX8997
> + help
> + If you say yes here you will get support for the
> + RTC of Maxim MAX8997 PMIC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max8997.
> +
> +config RTC_DRV_MAX77686
> + tristate "Maxim MAX77686"
> + depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
> + help
> + If you say yes here you will get support for the
> + RTC of Maxim MAX77686/MAX77620/MAX77802 PMIC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max77686.
> +
> +config RTC_DRV_MESON_VRTC
> + tristate "Amlogic Meson Virtual RTC"
> + depends on ARCH_MESON || COMPILE_TEST
> + default m if ARCH_MESON
> + help
> + If you say yes here you will get support for the
> + Virtual RTC of Amlogic SoCs.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-meson-vrtc.
> +
> +config RTC_DRV_RK808
> + tristate "Rockchip RK805/RK808/RK809/RK817/RK818 RTC"
> + depends on MFD_RK808
> + help
> + If you say yes here you will get support for the
> + RTC of RK805, RK809 and RK817, RK808 and RK818 PMIC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rk808-rtc.
> +
> +config RTC_DRV_RS5C372
> + tristate "Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A"
> + help
> + If you say yes here you get support for the
> + Ricoh R2025S/D, RS5C372A, RS5C372B, RV5C386, and RV5C387A RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rs5c372.
> +
> +config RTC_DRV_ISL1208
> + tristate "Intersil ISL1208"
> + help
> + If you say yes here you get support for the
> + Intersil ISL1208 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-isl1208.
> +
> +config RTC_DRV_ISL12022
> + tristate "Intersil ISL12022"
> + help
> + If you say yes here you get support for the
> + Intersil ISL12022 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-isl12022.
> +
> +config RTC_DRV_ISL12026
> + tristate "Intersil ISL12026"
> + depends on OF || COMPILE_TEST
> + help
> + If you say yes here you get support for the
> + Intersil ISL12026 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-isl12026.
> +
> +config RTC_DRV_X1205
> + tristate "Xicor/Intersil X1205"
> + help
> + If you say yes here you get support for the
> + Xicor/Intersil X1205 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-x1205.
> +
> +config RTC_DRV_PCF8523
> + tristate "NXP PCF8523"
> + help
> + If you say yes here you get support for the NXP PCF8523 RTC
> + chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pcf8523.
> +
> +config RTC_DRV_PCF85063
> + tristate "NXP PCF85063"
> + select REGMAP_I2C
> + help
> + If you say yes here you get support for the PCF85063 RTC chip
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pcf85063.
> +
> +config RTC_DRV_PCF85363
> + tristate "NXP PCF85363"
> + select REGMAP_I2C
> + help
> + If you say yes here you get support for the PCF85363 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pcf85363.
> +
> + The nvmem interface will be named pcf85363-#, where # is the
> + zero-based instance number.
> +
> +config RTC_DRV_PCF8563
> + tristate "Philips PCF8563/Epson RTC8564"
> + help
> + If you say yes here you get support for the
> + Philips PCF8563 RTC chip. The Epson RTC8564
> + should work as well.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pcf8563.
> +
> +config RTC_DRV_PCF8583
> + tristate "Philips PCF8583"
> + help
> + If you say yes here you get support for the Philips PCF8583
> + RTC chip found on Acorn RiscPCs. This driver supports the
> + platform specific method of retrieving the current year from
> + the RTC's SRAM. It will work on other platforms with the same
> + chip, but the year will probably have to be tweaked.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pcf8583.
> +
> +config RTC_DRV_M41T80
> + tristate "ST M41T62/65/M41T80/81/82/83/84/85/87 and compatible"
> + help
> + If you say Y here you will get support for the ST M41T60
> + and M41T80 RTC chips series. Currently, the following chips are
> + supported: M41T62, M41T65, M41T80, M41T81, M41T82, M41T83, M41ST84,
> + M41ST85, M41ST87, and MicroCrystal RV4162.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-m41t80.
> +
> +config RTC_DRV_M41T80_WDT
> + bool "ST M41T65/M41T80 series RTC watchdog timer"
> + depends on RTC_DRV_M41T80
> + help
> + If you say Y here you will get support for the
> + watchdog timer in the ST M41T60 and M41T80 RTC chips series.
> +config RTC_DRV_BD70528
> + tristate "ROHM BD70528 PMIC RTC"
> + depends on MFD_ROHM_BD70528 && (BD70528_WATCHDOG || !BD70528_WATCHDOG)
> + help
> + If you say Y here you will get support for the RTC
> + on ROHM BD70528 Power Management IC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-bd70528.
> +
> +config RTC_DRV_BQ32K
> + tristate "TI BQ32000"
> + help
> + If you say Y here you will get support for the TI
> + BQ32000 I2C RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-bq32k.
> +
> +config RTC_DRV_DM355EVM
> + tristate "TI DaVinci DM355 EVM RTC"
> + depends on MFD_DM355EVM_MSP
> + help
> + Supports the RTC firmware in the MSP430 on the DM355 EVM.
> +
> +config RTC_DRV_TWL92330
> + bool "TI TWL92330/Menelaus"
> + depends on MENELAUS
> + help
> + If you say yes here you get support for the RTC on the
> + TWL92330 "Menelaus" power management chip, used with OMAP2
> + platforms. The support is integrated with the rest of
> + the Menelaus driver; it's not separate module.
> +
> +config RTC_DRV_TWL4030
> + tristate "TI TWL4030/TWL5030/TWL6030/TPS659x0"
> + depends on TWL4030_CORE
> + depends on OF
> + help
> + If you say yes here you get support for the RTC on the
> + TWL4030/TWL5030/TWL6030 family chips, used mostly with OMAP3 platforms.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-twl.
> +
> +config RTC_DRV_PALMAS
> + tristate "TI Palmas RTC driver"
> + depends on MFD_PALMAS
> + help
> + If you say yes here you get support for the RTC of TI PALMA series PMIC
> + chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-palma.
> +
> +config RTC_DRV_TPS6586X
> + tristate "TI TPS6586X RTC driver"
> + depends on MFD_TPS6586X
> + help
> + TI Power Management IC TPS6586X supports RTC functionality
> + along with alarm. This driver supports the RTC driver for
> + the TPS6586X RTC module.
> +
> +config RTC_DRV_TPS65910
> + tristate "TI TPS65910 RTC driver"
> + depends on MFD_TPS65910
> + help
> + If you say yes here you get support for the RTC on the
> + TPS65910 chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-tps65910.
> +
> +config RTC_DRV_TPS80031
> + tristate "TI TPS80031/TPS80032 RTC driver"
> + depends on MFD_TPS80031
> + help
> + TI Power Management IC TPS80031 supports RTC functionality
> + along with alarm. This driver supports the RTC driver for
> + the TPS80031 RTC module.
> +
> +config RTC_DRV_RC5T583
> + tristate "RICOH 5T583 RTC driver"
> + depends on MFD_RC5T583
> + help
> + If you say yes here you get support for the RTC on the
> + RICOH 5T583 chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rc5t583.
> +
> +config RTC_DRV_S35390A
> + tristate "Seiko Instruments S-35390A"
> + select BITREVERSE
> + help
> + If you say yes here you will get support for the Seiko
> + Instruments S-35390A.
> +
> + This driver can also be built as a module. If so the module
> + will be called rtc-s35390a.
> +
> +config RTC_DRV_FM3130
> + tristate "Ramtron FM3130"
> + help
> + If you say Y here you will get support for the
> + Ramtron FM3130 RTC chips.
> + Ramtron FM3130 is a chip with two separate devices inside,
> + RTC clock and FRAM. This driver provides only RTC functionality.
> +
> + This driver can also be built as a module. If so the module
> + will be called rtc-fm3130.
> +
> +config RTC_DRV_RX8010
> + tristate "Epson RX8010SJ"
> + help
> + If you say yes here you get support for the Epson RX8010SJ RTC
> + chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rx8010.
> +
> +config RTC_DRV_RX8581
> + tristate "Epson RX-8571/RX-8581"
> + select REGMAP_I2C
> + help
> + If you say yes here you will get support for the Epson RX-8571/
> + RX-8581.
> +
> + This driver can also be built as a module. If so the module
> + will be called rtc-rx8581.
> +
> +config RTC_DRV_RX8025
> + tristate "Epson RX-8025SA/NB"
> + help
> + If you say yes here you get support for the Epson
> + RX-8025SA/NB RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rx8025.
> +
> +config RTC_DRV_RX8130
> + tristate "Epson RX8130CE"
> + help
> + If you say yes here you get support for the Epson
> + RX8130CE RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rx8130.
> +
> +config RTC_DRV_EM3027
> + tristate "EM Microelectronic EM3027"
> + help
> + If you say yes here you get support for the EM
> + Microelectronic EM3027 RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-em3027.
> +
> +config RTC_DRV_RV3028
> + tristate "Micro Crystal RV3028"
> + select REGMAP_I2C
> + help
> + If you say yes here you get support for the Micro Crystal
> + RV3028.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rv3028.
> +
> +config RTC_DRV_RV8803
> + tristate "Micro Crystal RV8803, Epson RX8900"
> + help
> + If you say yes here you get support for the Micro Crystal RV8803 and
> + Epson RX8900 RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rv8803.
> +
> +config RTC_DRV_S5M
> + tristate "Samsung S2M/S5M series"
> + depends on MFD_SEC_CORE || COMPILE_TEST
> + select REGMAP_IRQ
> + help
> + If you say yes here you will get support for the
> + RTC of Samsung S2MPS14 and S5M PMIC series.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-s5m.
> +
> +config RTC_DRV_SD3078
> + tristate "ZXW Shenzhen whwave SD3078"
> + select REGMAP_I2C
> + help
> + If you say yes here you get support for the ZXW Shenzhen whwave
> + SD3078 RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-sd3078
> +
> +endif # I2C
> +
> +comment "SPI RTC drivers"
> +
> +if SPI_MASTER
> +
> +config RTC_DRV_M41T93
> + tristate "ST M41T93"
> + help
> + If you say yes here you will get support for the
> + ST M41T93 SPI RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-m41t93.
> +
> +config RTC_DRV_M41T94
> + tristate "ST M41T94"
> + help
> + If you say yes here you will get support for the
> + ST M41T94 SPI RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-m41t94.
> +
> +config RTC_DRV_DS1302
> + tristate "Dallas/Maxim DS1302"
> + depends on SPI
> + help
> + If you say yes here you get support for the Dallas DS1302 RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1302.
> +
> +config RTC_DRV_DS1305
> + tristate "Dallas/Maxim DS1305/DS1306"
> + help
> + Select this driver to get support for the Dallas/Maxim DS1305
> + and DS1306 real time clock chips. These support a trickle
> + charger, alarms, and NVRAM in addition to the clock.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1305.
> +
> +config RTC_DRV_DS1343
> + select REGMAP_SPI
> + tristate "Dallas/Maxim DS1343/DS1344"
> + help
> + If you say yes here you get support for the
> + Dallas/Maxim DS1343 and DS1344 real time clock chips.
> + Support for trickle charger, alarm is provided.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1343.
> +
> +config RTC_DRV_DS1347
> + select REGMAP_SPI
> + tristate "Dallas/Maxim DS1347"
> + help
> + If you say yes here you get support for the
> + Dallas/Maxim DS1347 chips.
> +
> + This driver only supports the RTC feature, and not other chip
> + features such as alarms.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1347.
> +
> +config RTC_DRV_DS1390
> + tristate "Dallas/Maxim DS1390/93/94"
> + help
> + If you say yes here you get support for the
> + Dallas/Maxim DS1390/93/94 chips.
> +
> + This driver supports the RTC feature and trickle charging but not
> + other chip features such as alarms.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1390.
> +
> +config RTC_DRV_MAX6916
> + tristate "Maxim MAX6916"
> + help
> + If you say yes here you will get support for the
> + Maxim MAX6916 SPI RTC chip.
> +
> + This driver only supports the RTC feature, and not other chip
> + features such as alarms.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max6916.
> +
> +config RTC_DRV_R9701
> + tristate "Epson RTC-9701JE"
> + help
> + If you say yes here you will get support for the
> + Epson RTC-9701JE SPI RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-r9701.
> +
> +config RTC_DRV_RX4581
> + tristate "Epson RX-4581"
> + help
> + If you say yes here you will get support for the Epson RX-4581.
> +
> + This driver can also be built as a module. If so the module
> + will be called rtc-rx4581.
> +
> +config RTC_DRV_RX6110
> + tristate "Epson RX-6110"
> + select REGMAP_SPI
> + help
> + If you say yes here you will get support for the Epson RX-6610.
> +
> + This driver can also be built as a module. If so the module
> + will be called rtc-rx6110.
> +
> +config RTC_DRV_RS5C348
> + tristate "Ricoh RS5C348A/B"
> + help
> + If you say yes here you get support for the
> + Ricoh RS5C348A and RS5C348B RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rs5c348.
> +
> +config RTC_DRV_MAX6902
> + tristate "Maxim MAX6902"
> + help
> + If you say yes here you will get support for the
> + Maxim MAX6902 SPI RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-max6902.
> +
> +config RTC_DRV_PCF2123
> + tristate "NXP PCF2123"
> + select REGMAP_SPI
> + help
> + If you say yes here you get support for the NXP PCF2123
> + RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pcf2123.
> +
> +config RTC_DRV_MCP795
> + tristate "Microchip MCP795"
> + help
> + If you say yes here you will get support for the Microchip MCP795.
> +
> + This driver can also be built as a module. If so the module
> + will be called rtc-mcp795.
> +
> +endif # SPI_MASTER
> +
> +#
> +# Helper to resolve issues with configs that have SPI enabled but I2C
> +# modular. See SND_SOC_I2C_AND_SPI for more information
> +#
> +config RTC_I2C_AND_SPI
> + tristate
> + default m if I2C=m
> + default y if I2C=y
> + default y if SPI_MASTER=y
> +
> +comment "SPI and I2C RTC drivers"
> +
> +config RTC_DRV_DS3232
> + tristate "Dallas/Maxim DS3232/DS3234"
> + depends on RTC_I2C_AND_SPI
> + select REGMAP_I2C if I2C
> + select REGMAP_SPI if SPI_MASTER
> + help
> + If you say yes here you get support for Dallas Semiconductor
> + DS3232 and DS3234 real-time clock chips. If an interrupt is associated
> + with the device, the alarm functionality is supported.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds3232.
> +
> +config RTC_DRV_DS3232_HWMON
> + bool "HWMON support for Dallas/Maxim DS3232/DS3234"
> + depends on RTC_DRV_DS3232 && HWMON && !(RTC_DRV_DS3232=y && HWMON=m)
> + default y
> + help
> + Say Y here if you want to expose temperature sensor data on
> + rtc-ds3232
> +
> +config RTC_DRV_PCF2127
> + tristate "NXP PCF2127"
> + depends on RTC_I2C_AND_SPI
> + select REGMAP_I2C if I2C
> + select REGMAP_SPI if SPI_MASTER
> + select WATCHDOG_CORE if WATCHDOG
> + help
> + If you say yes here you get support for the NXP PCF2127/29 RTC
> + chips with integrated quartz crystal for industrial applications.
> + Both chips also have watchdog timer and tamper switch detection
> + features.
> +
> + PCF2127 has an additional feature of 512 bytes battery backed
> + memory that's accessible using nvmem interface.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pcf2127.
> +
> +config RTC_DRV_RV3029C2
> + tristate "Micro Crystal RV3029/3049"
> + depends on RTC_I2C_AND_SPI
> + select REGMAP_I2C if I2C
> + select REGMAP_SPI if SPI_MASTER
> + help
> + If you say yes here you get support for the Micro Crystal
> + RV3029 and RV3049 RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rv3029c2.
> +
> +config RTC_DRV_RV3029_HWMON
> + bool "HWMON support for RV3029/3049"
> + depends on RTC_DRV_RV3029C2 && HWMON
> + depends on !(RTC_DRV_RV3029C2=y && HWMON=m)
> + default y
> + help
> + Say Y here if you want to expose temperature sensor data on
> + rtc-rv3029.
> +
> +comment "Platform RTC drivers"
> +
> +# this 'CMOS' RTC driver is arch dependent because it requires
> +# <asm/mc146818rtc.h> defining CMOS_READ/CMOS_WRITE, and a
> +# global rtc_lock ... it's not yet just another platform_device.
> +
> +config RTC_DRV_CMOS
> + tristate "PC-style 'CMOS'"
> + depends on X86 || ARM || PPC || MIPS || SPARC64
> + default y if X86
> + select RTC_MC146818_LIB
> + help
> + Say "yes" here to get direct support for the real time clock
> + found in every PC or ACPI-based system, and some other boards.
> + Specifically the original MC146818, compatibles like those in
> + PC south bridges, the DS12887 or M48T86, some multifunction
> + or LPC bus chips, and so on.
> +
> + Your system will need to define the platform device used by
> + this driver, otherwise it won't be accessible. This means
> + you can safely enable this driver if you don't know whether
> + or not your board has this kind of hardware.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-cmos.
> +
> +config RTC_DRV_ALPHA
> + bool "Alpha PC-style CMOS"
> + depends on ALPHA
> + select RTC_MC146818_LIB
> + default y
> + help
> + Direct support for the real-time clock found on every Alpha
> + system, specifically MC146818 compatibles. If in doubt, say Y.
> +
> +config RTC_DRV_VRTC
> + tristate "Virtual RTC for Intel MID platforms"
> + depends on X86_INTEL_MID
> + default y if X86_INTEL_MID
> +
> + help
> + Say "yes" here to get direct support for the real time clock
> + found on Moorestown platforms. The VRTC is a emulated RTC that
> + derives its clock source from a real RTC in the PMIC. The MC146818
> + style programming interface is mostly conserved, but any
> + updates are done via IPC calls to the system controller FW.
> +
> +config RTC_DRV_DS1216
> + tristate "Dallas DS1216"
> + depends on SNI_RM
> + help
> + If you say yes here you get support for the Dallas DS1216 RTC chips.
> +
> +config RTC_DRV_DS1286
> + tristate "Dallas DS1286"
> + depends on HAS_IOMEM
> + help
> + If you say yes here you get support for the Dallas DS1286 RTC chips.
> +
> +config RTC_DRV_DS1511
> + tristate "Dallas DS1511"
> + depends on HAS_IOMEM
> + help
> + If you say yes here you get support for the
> + Dallas DS1511 timekeeping/watchdog chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1511.
> +
> +config RTC_DRV_DS1553
> + tristate "Maxim/Dallas DS1553"
> + depends on HAS_IOMEM
> + help
> + If you say yes here you get support for the
> + Maxim/Dallas DS1553 timekeeping chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1553.
> +
> +config RTC_DRV_DS1685_FAMILY
> + tristate "Dallas/Maxim DS1685 Family"
> + help
> + If you say yes here you get support for the Dallas/Maxim DS1685
> + family of real time chips. This family includes the DS1685/DS1687,
> + DS1689/DS1693, DS17285/DS17287, DS17485/DS17487, and
> + DS17885/DS17887 chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1685.
> +
> +choice
> + prompt "Subtype"
> + depends on RTC_DRV_DS1685_FAMILY
> + default RTC_DRV_DS1685
> +
> +config RTC_DRV_DS1685
> + bool "DS1685/DS1687"
> + help
> + This enables support for the Dallas/Maxim DS1685/DS1687 real time
> + clock chip.
> +
> + This chip is commonly found in SGI O2 (IP32) and SGI Octane (IP30)
> + systems, as well as EPPC-405-UC modules by electronic system design
> + GmbH.
> +
> +config RTC_DRV_DS1689
> + bool "DS1689/DS1693"
> + help
> + This enables support for the Dallas/Maxim DS1689/DS1693 real time
> + clock chip.
> +
> + This is an older RTC chip, supplanted by the DS1685/DS1687 above,
> + which supports a few minor features such as Vcc, Vbat, and Power
> + Cycle counters, plus a customer-specific, 8-byte ROM/Serial number.
> +
> + It also works for the even older DS1688/DS1691 RTC chips, which are
> + virtually the same and carry the same model number. Both chips
> + have 114 bytes of user NVRAM.
> +
> +config RTC_DRV_DS17285
> + bool "DS17285/DS17287"
> + help
> + This enables support for the Dallas/Maxim DS17285/DS17287 real time
> + clock chip.
> +
> + This chip features 2kb of extended NV-SRAM. It may possibly be
> + found in some SGI O2 systems (rare).
> +
> +config RTC_DRV_DS17485
> + bool "DS17485/DS17487"
> + help
> + This enables support for the Dallas/Maxim DS17485/DS17487 real time
> + clock chip.
> +
> + This chip features 4kb of extended NV-SRAM.
> +
> +config RTC_DRV_DS17885
> + bool "DS17885/DS17887"
> + help
> + This enables support for the Dallas/Maxim DS17885/DS17887 real time
> + clock chip.
> +
> + This chip features 8kb of extended NV-SRAM.
> +
> +endchoice
> +
> +config RTC_DRV_DS1742
> + tristate "Maxim/Dallas DS1742/1743"
> + depends on HAS_IOMEM
> + help
> + If you say yes here you get support for the
> + Maxim/Dallas DS1742/1743 timekeeping chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds1742.
> +
> +config RTC_DRV_DS2404
> + tristate "Maxim/Dallas DS2404"
> + help
> + If you say yes here you get support for the
> + Dallas DS2404 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ds2404.
> +
> +config RTC_DRV_DA9052
> + tristate "Dialog DA9052/DA9053 RTC"
> + depends on PMIC_DA9052
> + help
> + Say y here to support the RTC driver for Dialog Semiconductor
> + DA9052-BC and DA9053-AA/Bx PMICs.
> +
> +config RTC_DRV_DA9055
> + tristate "Dialog Semiconductor DA9055 RTC"
> + depends on MFD_DA9055
> + help
> + If you say yes here you will get support for the
> + RTC of the Dialog DA9055 PMIC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-da9055
> +
> +config RTC_DRV_DA9063
> + tristate "Dialog Semiconductor DA9063/DA9062 RTC"
> + depends on MFD_DA9063 || MFD_DA9062
> + help
> + If you say yes here you will get support for the RTC subsystem
> + for the Dialog Semiconductor PMIC chips DA9063 and DA9062.
> +
> + This driver can also be built as a module. If so, the module
> + will be called "rtc-da9063".
> +
> +config RTC_DRV_EFI
> + tristate "EFI RTC"
> + depends on EFI && !X86
> + help
> + If you say yes here you will get support for the EFI
> + Real Time Clock.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-efi.
> +
> +config RTC_DRV_STK17TA8
> + tristate "Simtek STK17TA8"
> + depends on HAS_IOMEM
> + help
> + If you say yes here you get support for the
> + Simtek STK17TA8 timekeeping chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-stk17ta8.
> +
> +config RTC_DRV_M48T86
> + tristate "ST M48T86/Dallas DS12887"
> + help
> + If you say Y here you will get support for the
> + ST M48T86 and Dallas DS12887 RTC chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-m48t86.
> +
> +config RTC_DRV_M48T35
> + tristate "ST M48T35"
> + depends on HAS_IOMEM
> + help
> + If you say Y here you will get support for the
> + ST M48T35 RTC chip.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-m48t35".
> +
> +config RTC_DRV_M48T59
> + tristate "ST M48T59/M48T08/M48T02"
> + depends on HAS_IOMEM
> + help
> + If you say Y here you will get support for the
> + ST M48T59 RTC chip and compatible ST M48T08 and M48T02.
> +
> + These chips are usually found in Sun SPARC and UltraSPARC
> + workstations.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-m48t59".
> +
> +config RTC_DRV_MSM6242
> + tristate "Oki MSM6242"
> + depends on HAS_IOMEM
> + help
> + If you say yes here you get support for the Oki MSM6242
> + timekeeping chip. It is used in some Amiga models (e.g. A2000).
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-msm6242.
> +
> +config RTC_DRV_BQ4802
> + tristate "TI BQ4802"
> + depends on HAS_IOMEM
> + help
> + If you say Y here you will get support for the TI
> + BQ4802 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-bq4802.
> +
> +config RTC_DRV_RP5C01
> + tristate "Ricoh RP5C01"
> + depends on HAS_IOMEM
> + help
> + If you say yes here you get support for the Ricoh RP5C01
> + timekeeping chip. It is used in some Amiga models (e.g. A3000
> + and A4000).
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-rp5c01.
> +
> +config RTC_DRV_V3020
> + tristate "EM Microelectronic V3020"
> + help
> + If you say yes here you will get support for the
> + EM Microelectronic v3020 RTC chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-v3020.
> +
> +config RTC_DRV_WM831X
> + tristate "Wolfson Microelectronics WM831x RTC"
> + depends on MFD_WM831X
> + help
> + If you say yes here you will get support for the RTC subsystem
> + of the Wolfson Microelectronics WM831X series PMICs.
> +
> + This driver can also be built as a module. If so, the module
> + will be called "rtc-wm831x".
> +
> +config RTC_DRV_WM8350
> + tristate "Wolfson Microelectronics WM8350 RTC"
> + depends on MFD_WM8350
> + help
> + If you say yes here you will get support for the RTC subsystem
> + of the Wolfson Microelectronics WM8350.
> +
> + This driver can also be built as a module. If so, the module
> + will be called "rtc-wm8350".
> +
> +config RTC_DRV_SC27XX
> + tristate "Spreadtrum SC27xx RTC"
> + depends on MFD_SC27XX_PMIC || COMPILE_TEST
> + help
> + If you say Y here you will get support for the RTC subsystem
> + of the Spreadtrum SC27xx series PMICs. The SC27xx series PMICs
> + includes the SC2720, SC2721, SC2723, SC2730 and SC2731 chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-sc27xx.
> +
> +config RTC_DRV_SPEAR
> + tristate "SPEAR ST RTC"
> + depends on PLAT_SPEAR || COMPILE_TEST
> + default y
> + help
> + If you say Y here you will get support for the RTC found on
> + spear
> +
> +config RTC_DRV_PCF50633
> + depends on MFD_PCF50633
> + tristate "NXP PCF50633 RTC"
> + help
> + If you say yes here you get support for the RTC subsystem of the
> + NXP PCF50633 used in embedded systems.
> +
> +config RTC_DRV_AB3100
> + tristate "ST-Ericsson AB3100 RTC"
> + depends on AB3100_CORE
> + default y if AB3100_CORE
> + help
> + Select this to enable the ST-Ericsson AB3100 Mixed Signal IC RTC
> + support. This chip contains a battery- and capacitor-backed RTC.
> +
> +config RTC_DRV_AB8500
> + tristate "ST-Ericsson AB8500 RTC"
> + depends on AB8500_CORE
> + select RTC_INTF_DEV
> + select RTC_INTF_DEV_UIE_EMUL
> + help
> + Select this to enable the ST-Ericsson AB8500 power management IC RTC
> + support. This chip contains a battery- and capacitor-backed RTC.
> +
> +config RTC_DRV_OPAL
> + tristate "IBM OPAL RTC driver"
> + depends on PPC_POWERNV
> + default y
> + help
> + If you say yes here you get support for the PowerNV platform RTC
> + driver based on OPAL interfaces.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-opal.
> +
> +config RTC_DRV_ZYNQMP
> + tristate "Xilinx Zynq Ultrascale+ MPSoC RTC"
> + depends on OF
> + help
> + If you say yes here you get support for the RTC controller found on
> + Xilinx Zynq Ultrascale+ MPSoC.
> +
> +config RTC_DRV_CROS_EC
> + tristate "Chrome OS EC RTC driver"
> + depends on CROS_EC
> + help
> + If you say yes here you will get support for the
> + Chrome OS Embedded Controller's RTC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-cros-ec.
> +
> +comment "on-CPU RTC drivers"
> +
> +config RTC_DRV_ASM9260
> + tristate "Alphascale asm9260 RTC"
> + depends on MACH_ASM9260 || COMPILE_TEST
> + help
> + If you say yes here you get support for the RTC on the
> + Alphascale asm9260 SoC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-asm9260.
> +
> +config RTC_DRV_DAVINCI
> + tristate "TI DaVinci RTC"
> + depends on ARCH_DAVINCI_DM365 || COMPILE_TEST
> + help
> + If you say yes here you get support for the RTC on the
> + DaVinci platforms (DM365).
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-davinci.
> +
> +config RTC_DRV_DIGICOLOR
> + tristate "Conexant Digicolor RTC"
> + depends on ARCH_DIGICOLOR || COMPILE_TEST
> + help
> + If you say yes here you get support for the RTC on Conexant
> + Digicolor platforms. This currently includes the CX92755 SoC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-digicolor.
> +
> +config RTC_DRV_IMXDI
> + tristate "Freescale IMX DryIce Real Time Clock"
> + depends on ARCH_MXC
> + help
> + Support for Freescale IMX DryIce RTC
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-imxdi".
> +
> +config RTC_DRV_FSL_FTM_ALARM
> + tristate "Freescale FlexTimer alarm timer"
> + depends on ARCH_LAYERSCAPE || SOC_LS1021A
> + select FSL_RCPM
> + default y
> + help
> + For the FlexTimer in LS1012A, LS1021A, LS1028A, LS1043A, LS1046A,
> + LS1088A, LS208xA, we can use FTM as the wakeup source.
> +
> + Say y here to enable FTM alarm support. The FTM alarm provides
> + alarm functions for wakeup system from deep sleep.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-fsl-ftm-alarm".
> +
> +config RTC_DRV_MESON
> + tristate "Amlogic Meson RTC"
> + depends on (ARM && ARCH_MESON) || COMPILE_TEST
> + select REGMAP_MMIO
> + help
> + Support for the RTC block on the Amlogic Meson6, Meson8, Meson8b
> + and Meson8m2 SoCs.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-meson".
> +
> +config RTC_DRV_OMAP
> + tristate "TI OMAP Real Time Clock"
> + depends on ARCH_OMAP || ARCH_DAVINCI || COMPILE_TEST
> + depends on OF
> + depends on PINCTRL
> + select GENERIC_PINCONF
> + help
> + Say "yes" here to support the on chip real time clock
> + present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx.
> +
> + This driver can also be built as a module, if so, module
> + will be called rtc-omap.
> +
> +config HAVE_S3C_RTC
> + bool
> + help
> + This will include RTC support for Samsung SoCs. If
> + you want to include RTC support for any machine, kindly
> + select this in the respective mach-XXXX/Kconfig file.
> +
> +config RTC_DRV_S3C
> + tristate "Samsung S3C series SoC RTC"
> + depends on ARCH_S3C64XX || HAVE_S3C_RTC || COMPILE_TEST
> + help
> + RTC (Realtime Clock) driver for the clock inbuilt into the
> + Samsung S3C24XX series of SoCs. This can provide periodic
> + interrupt rates from 1Hz to 64Hz for user programs, and
> + wakeup from Alarm.
> +
> + The driver currently supports the common features on all the
> + S3C24XX range, such as the S3C2410, S3C2412, S3C2413, S3C2440
> + and S3C2442.
> +
> + This driver can also be build as a module. If so, the module
> + will be called rtc-s3c.
> +
> +config RTC_DRV_EP93XX
> + tristate "Cirrus Logic EP93XX"
> + depends on ARCH_EP93XX || COMPILE_TEST
> + help
> + If you say yes here you get support for the
> + RTC embedded in the Cirrus Logic EP93XX processors.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ep93xx.
> +
> +config RTC_DRV_SA1100
> + tristate "SA11x0/PXA2xx/PXA910"
> + depends on ARCH_SA1100 || ARCH_PXA || ARCH_MMP
> + help
> + If you say Y here you will get access to the real time clock
> + built into your SA11x0 or PXA2xx CPU.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-sa1100.
> +
> +config RTC_DRV_SH
> + tristate "SuperH On-Chip RTC"
> + depends on SUPERH || ARCH_RENESAS
> + help
> + Say Y here to enable support for the on-chip RTC found in
> + most SuperH processors. This RTC is also found in RZ/A SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-sh.
> +
> +config RTC_DRV_VR41XX
> + tristate "NEC VR41XX"
> + depends on CPU_VR41XX || COMPILE_TEST
> + help
> + If you say Y here you will get access to the real time clock
> + built into your NEC VR41XX CPU.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-vr41xx.
> +
> +config RTC_DRV_PL030
> + tristate "ARM AMBA PL030 RTC"
> + depends on ARM_AMBA
> + help
> + If you say Y here you will get access to ARM AMBA
> + PrimeCell PL030 RTC found on certain ARM SOCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-pl030.
> +
> +config RTC_DRV_PL031
> + tristate "ARM AMBA PL031 RTC"
> + depends on ARM_AMBA
> + help
> + If you say Y here you will get access to ARM AMBA
> + PrimeCell PL031 RTC found on certain ARM SOCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-pl031.
> +
> +config RTC_DRV_AT91RM9200
> + tristate "AT91RM9200 or some AT91SAM9 RTC"
> + depends on ARCH_AT91 || COMPILE_TEST
> + help
> + Driver for the internal RTC (Realtime Clock) module found on
> + Atmel AT91RM9200's and some AT91SAM9 chips. On AT91SAM9 chips
> + this is powered by the backup power supply.
> +
> +config RTC_DRV_AT91SAM9
> + tristate "AT91SAM9 RTT as RTC"
> + depends on ARCH_AT91 || COMPILE_TEST
> + depends on OF && HAS_IOMEM
> + select MFD_SYSCON
> + help
> + Some AT91SAM9 SoCs provide an RTT (Real Time Timer) block which
> + can be used as an RTC thanks to the backup power supply (e.g. a
> + small coin cell battery) which keeps this block and the GPBR
> + (General Purpose Backup Registers) block powered when the device
> + is shutdown.
> + Some AT91SAM9 SoCs provide a real RTC block, on those ones you'd
> + probably want to use the real RTC block instead of the "RTT as an
> + RTC" driver.
> +
> +config RTC_DRV_AU1XXX
> + tristate "Au1xxx Counter0 RTC support"
> + depends on MIPS_ALCHEMY
> + help
> + This is a driver for the Au1xxx on-chip Counter0 (Time-Of-Year
> + counter) to be used as a RTC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-au1xxx.
> +
> +config RTC_DRV_RS5C313
> + tristate "Ricoh RS5C313"
> + depends on SH_LANDISK
> + help
> + If you say yes here you get support for the Ricoh RS5C313 RTC chips.
> +
> +config RTC_DRV_GENERIC
> + tristate "Generic RTC support"
> + # Please consider writing a new RTC driver instead of using the generic
> + # RTC abstraction
> + depends on PARISC || M68K || PPC || SUPERH32 || COMPILE_TEST
> + help
> + Say Y or M here to enable RTC support on systems using the generic
> + RTC abstraction. If you do not know what you are doing, you should
> + just say Y.
> +
> +config RTC_DRV_PXA
> + tristate "PXA27x/PXA3xx"
> + depends on ARCH_PXA
> + select RTC_DRV_SA1100
> + help
> + If you say Y here you will get access to the real time clock
> + built into your PXA27x or PXA3xx CPU. This RTC is actually 2 RTCs
> + consisting of an SA1100 compatible RTC and the extended PXA RTC.
> +
> + This RTC driver uses PXA RTC registers available since pxa27x
> + series (RDxR, RYxR) instead of legacy RCNR, RTAR.
> +
> +config RTC_DRV_VT8500
> + tristate "VIA/WonderMedia 85xx SoC RTC"
> + depends on ARCH_VT8500 || COMPILE_TEST
> + help
> + If you say Y here you will get access to the real time clock
> + built into your VIA VT8500 SoC or its relatives.
> +
> +
> +config RTC_DRV_SUN4V
> + bool "SUN4V Hypervisor RTC"
> + depends on SPARC64
> + help
> + If you say Y here you will get support for the Hypervisor
> + based RTC on SUN4V systems.
> +
> +config RTC_DRV_SUN6I
> + bool "Allwinner A31 RTC"
> + default MACH_SUN6I || MACH_SUN8I
> + depends on COMMON_CLK
> + depends on ARCH_SUNXI || COMPILE_TEST
> + help
> + If you say Y here you will get support for the RTC found in
> + some Allwinner SoCs like the A31 or the A64.
> +
> +config RTC_DRV_SUNXI
> + tristate "Allwinner sun4i/sun7i RTC"
> + depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
> + help
> + If you say Y here you will get support for the RTC found on
> + Allwinner A10/A20.
> +
> +config RTC_DRV_STARFIRE
> + bool "Starfire RTC"
> + depends on SPARC64
> + help
> + If you say Y here you will get support for the RTC found on
> + Starfire systems.
> +
> +config RTC_DRV_TX4939
> + tristate "TX4939 SoC"
> + depends on SOC_TX4939 || COMPILE_TEST
> + help
> + Driver for the internal RTC (Realtime Clock) module found on
> + Toshiba TX4939 SoC.
> +
> +config RTC_DRV_MV
> + tristate "Marvell SoC RTC"
> + depends on ARCH_DOVE || ARCH_MVEBU || COMPILE_TEST
> + help
> + If you say yes here you will get support for the in-chip RTC
> + that can be found in some of Marvell's SoC devices, such as
> + the Kirkwood 88F6281 and 88F6192.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-mv.
> +
> +config RTC_DRV_ARMADA38X
> + tristate "Armada 38x Marvell SoC RTC"
> + depends on ARCH_MVEBU || COMPILE_TEST
> + help
> + If you say yes here you will get support for the in-chip RTC
> + that can be found in the Armada 38x Marvell's SoC device
> +
> + This driver can also be built as a module. If so, the module
> + will be called armada38x-rtc.
> +
> +config RTC_DRV_CADENCE
> + tristate "Cadence RTC driver"
> + depends on OF && HAS_IOMEM
> + help
> + If you say Y here you will get access to Cadence RTC IP
> + found on certain SOCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-cadence.
> +
> +config RTC_DRV_FTRTC010
> + tristate "Faraday Technology FTRTC010 RTC"
> + depends on HAS_IOMEM
> + default ARCH_GEMINI
> + help
> + If you say Y here you will get support for the
> + Faraday Technolog FTRTC010 found on e.g. Gemini SoC's.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ftrtc010.
> +
> +config RTC_DRV_PS3
> + tristate "PS3 RTC"
> + depends on PPC_PS3
> + help
> + If you say yes here you will get support for the RTC on PS3.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ps3.
> +
> +config RTC_DRV_COH901331
> + tristate "ST-Ericsson COH 901 331 RTC"
> + depends on ARCH_U300 || COMPILE_TEST
> + help
> + If you say Y here you will get access to ST-Ericsson
> + COH 901 331 RTC clock found in some ST-Ericsson Mobile
> + Platforms.
> +
> + This driver can also be built as a module. If so, the module
> + will be called "rtc-coh901331".
> +
> +
> +config RTC_DRV_STMP
> + tristate "Freescale STMP3xxx/i.MX23/i.MX28 RTC"
> + depends on ARCH_MXS || COMPILE_TEST
> + select STMP_DEVICE
> + help
> + If you say yes here you will get support for the onboard
> + STMP3xxx/i.MX23/i.MX28 RTC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-stmp3xxx.
> +
> +config RTC_DRV_PCAP
> + tristate "PCAP RTC"
> + depends on EZX_PCAP
> + help
> + If you say Y here you will get support for the RTC found on
> + the PCAP2 ASIC used on some Motorola phones.
> +
> +config RTC_DRV_MC13XXX
> + depends on MFD_MC13XXX
> + tristate "Freescale MC13xxx RTC"
> + help
> + This enables support for the RTCs found on Freescale's PMICs
> + MC13783 and MC13892.
> +
> +config RTC_DRV_MPC5121
> + tristate "Freescale MPC5121 built-in RTC"
> + depends on PPC_MPC512x || PPC_MPC52xx
> + help
> + If you say yes here you will get support for the
> + built-in RTC on MPC5121 or on MPC5200.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-mpc5121.
> +
> +config RTC_DRV_JZ4740
> + tristate "Ingenic JZ4740 SoC"
> + depends on MIPS || COMPILE_TEST
> + help
> + If you say yes here you get support for the Ingenic JZ47xx SoCs RTC
> + controllers.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-jz4740.
> +
> +config RTC_DRV_LPC24XX
> + tristate "NXP RTC for LPC178x/18xx/408x/43xx"
> + depends on ARCH_LPC18XX || COMPILE_TEST
> + depends on OF && HAS_IOMEM
> + help
> + This enables support for the NXP RTC found which can be found on
> + NXP LPC178x/18xx/408x/43xx devices.
> +
> + If you have one of the devices above enable this driver to use
> + the hardware RTC. This driver can also be built as a module. If
> + so, the module will be called rtc-lpc24xx.
> +
> +config RTC_DRV_LPC32XX
> + depends on ARCH_LPC32XX || COMPILE_TEST
> + tristate "NXP LPC32XX RTC"
> + help
> + This enables support for the NXP RTC in the LPC32XX
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-lpc32xx.
> +
> +config RTC_DRV_PM8XXX
> + tristate "Qualcomm PMIC8XXX RTC"
> + depends on MFD_PM8XXX || MFD_SPMI_PMIC || COMPILE_TEST
> + help
> + If you say yes here you get support for the
> + Qualcomm PMIC8XXX RTC.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-pm8xxx.
> +
> +config RTC_DRV_TEGRA
> + tristate "NVIDIA Tegra Internal RTC driver"
> + depends on ARCH_TEGRA || COMPILE_TEST
> + help
> + If you say yes here you get support for the
> + Tegra 200 series internal RTC module.
> +
> + This drive can also be built as a module. If so, the module
> + will be called rtc-tegra.
> +
> +config RTC_DRV_PUV3
> + tristate "PKUnity v3 RTC support"
> + depends on ARCH_PUV3
> + help
> + This enables support for the RTC in the PKUnity-v3 SoCs.
> +
> + This drive can also be built as a module. If so, the module
> + will be called rtc-puv3.
> +
> +config RTC_DRV_LOONGSON1
> + tristate "loongson1 RTC support"
> + depends on MACH_LOONGSON32
> + help
> + This is a driver for the loongson1 on-chip Counter0 (Time-Of-Year
> + counter) to be used as a RTC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-ls1x.
> +
> +config RTC_DRV_MXC
> + tristate "Freescale MXC Real Time Clock"
> + depends on ARCH_MXC
> + help
> + If you say yes here you get support for the Freescale MXC
> + RTC module.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-mxc".
> +
> +config RTC_DRV_MXC_V2
> + tristate "Freescale MXC Real Time Clock for i.MX53"
> + depends on ARCH_MXC
> + help
> + If you say yes here you get support for the Freescale MXC
> + SRTC module in i.MX53 processor.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-mxc_v2".
> +
> +config RTC_DRV_SNVS
> + tristate "Freescale SNVS RTC support"
> + select REGMAP_MMIO
> + depends on HAS_IOMEM
> + depends on OF
> + help
> + If you say yes here you get support for the Freescale SNVS
> + Low Power (LP) RTC module.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-snvs".
> +
> +config RTC_DRV_IMX_SC
> + depends on IMX_SCU
> + depends on HAVE_ARM_SMCCC
> + tristate "NXP i.MX System Controller RTC support"
> + help
> + If you say yes here you get support for the NXP i.MX System
> + Controller RTC module.
> +
> +config RTC_DRV_SIRFSOC
> + tristate "SiRFSOC RTC"
> + depends on ARCH_SIRF
> + help
> + Say "yes" here to support the real time clock on SiRF SOC chips.
> + This driver can also be built as a module called rtc-sirfsoc.
> +
> +config RTC_DRV_ST_LPC
> + tristate "STMicroelectronics LPC RTC"
> + depends on ARCH_STI
> + depends on OF
> + help
> + Say Y here to include STMicroelectronics Low Power Controller
> + (LPC) based RTC support.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rtc-st-lpc.
> +
> +config RTC_DRV_MOXART
> + tristate "MOXA ART RTC"
> + depends on ARCH_MOXART || COMPILE_TEST
> + help
> + If you say yes here you get support for the MOXA ART
> + RTC module.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-moxart
> +
> +config RTC_DRV_MT6397
> + tristate "MediaTek PMIC based RTC"
> + depends on MFD_MT6397 || (COMPILE_TEST && IRQ_DOMAIN)
> + help
> + This selects the MediaTek(R) RTC driver. RTC is part of MediaTek
> + MT6397 PMIC. You should enable MT6397 PMIC MFD before select
> + MediaTek(R) RTC driver.
> +
> + If you want to use MediaTek(R) RTC interface, select Y or M here.
> +
> +config RTC_DRV_MT7622
> + tristate "MediaTek SoC based RTC"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + help
> + This enables support for the real time clock built in the MediaTek
> + SoCs.
> +
> + This drive can also be built as a module. If so, the module
> + will be called rtc-mt7622.
> +
> +config RTC_DRV_XGENE
> + tristate "APM X-Gene RTC"
> + depends on HAS_IOMEM
> + depends on ARCH_XGENE || COMPILE_TEST
> + help
> + If you say yes here you get support for the APM X-Gene SoC real time
> + clock.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-xgene".
> +
> +config RTC_DRV_PIC32
> + tristate "Microchip PIC32 RTC"
> + depends on MACH_PIC32
> + default y
> + help
> + If you say yes here you get support for the PIC32 RTC module.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-pic32
> +
> +config RTC_DRV_R7301
> + tristate "EPSON TOYOCOM RTC-7301SF/DG"
> + select REGMAP_MMIO
> + depends on OF && HAS_IOMEM
> + help
> + If you say yes here you get support for the EPSON TOYOCOM
> + RTC-7301SF/DG chips.
> +
> + This driver can also be built as a module. If so, the module
> + will be called rtc-r7301.
> +
> +config RTC_DRV_STM32
> + tristate "STM32 RTC"
> + select REGMAP_MMIO
> + depends on ARCH_STM32 || COMPILE_TEST
> + help
> + If you say yes here you get support for the STM32 On-Chip
> + Real Time Clock.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-stm32".
> +
> +config RTC_DRV_CPCAP
> + depends on MFD_CPCAP
> + tristate "Motorola CPCAP RTC"
> + help
> + Say y here for CPCAP rtc found on some Motorola phones
> + and tablets such as Droid 4.
> +
> +config RTC_DRV_RTD119X
> + bool "Realtek RTD129x RTC"
> + depends on ARCH_REALTEK || COMPILE_TEST
> + default ARCH_REALTEK
> + help
> + If you say yes here, you get support for the RTD1295 SoC
> + Real Time Clock.
> +
> +config RTC_DRV_ASPEED
> + tristate "ASPEED RTC"
> + depends on OF
> + depends on ARCH_ASPEED || COMPILE_TEST
> + help
> + If you say yes here you get support for the ASPEED BMC SoC real time
> + clocks.
> +
> + This driver can also be built as a module, if so, the module
> + will be called "rtc-aspeed".
> +
> +comment "HID Sensor RTC drivers"
> +
> +config RTC_DRV_HID_SENSOR_TIME
> + tristate "HID Sensor Time"
> + depends on USB_HID
> + depends on HID_SENSOR_HUB && IIO
> + select HID_SENSOR_IIO_COMMON
> + help
> + Say yes here to build support for the HID Sensors of type Time.
> + This drivers makes such sensors available as RTCs.
> +
> + If this driver is compiled as a module, it will be named
> + rtc-hid-sensor-time.
> +
> +config RTC_DRV_GOLDFISH
> + tristate "Goldfish Real Time Clock"
> + depends on OF && HAS_IOMEM
> + depends on GOLDFISH || COMPILE_TEST
> + help
> + Say yes to enable RTC driver for the Goldfish based virtual platform.
> +
> + Goldfish is a code name for the virtual platform developed by Google
> + for Android emulation.
> +
> +config RTC_DRV_WILCO_EC
> + tristate "Wilco EC RTC"
> + depends on WILCO_EC
> + default m
> + help
> + If you say yes here, you get read/write support for the Real Time
> + Clock on the Wilco Embedded Controller (Wilco is a kind of Chromebook)
> +
> + This can also be built as a module. If so, the module will
> + be named "rtc_wilco_ec".
> +
> +endif # RTC_CLASS
> diff --git a/target/linux/mvebu/files/drivers/rtc/Makefile b/target/linux/mvebu/files/drivers/rtc/Makefile
> new file mode 100644
> index 0000000000..22665f9d9e
> --- /dev/null
> +++ b/target/linux/mvebu/files/drivers/rtc/Makefile
> @@ -0,0 +1,189 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Makefile for RTC class/drivers.
> +#
> +
> +ccflags-$(CONFIG_RTC_DEBUG) := -DDEBUG
> +
> +obj-$(CONFIG_RTC_LIB) += lib.o
> +obj-$(CONFIG_RTC_HCTOSYS) += hctosys.o
> +obj-$(CONFIG_RTC_SYSTOHC) += systohc.o
> +obj-$(CONFIG_RTC_CLASS) += rtc-core.o
> +obj-$(CONFIG_RTC_MC146818_LIB) += rtc-mc146818-lib.o
> +rtc-core-y := class.o interface.o
> +
> +ifdef CONFIG_RTC_DRV_EFI
> +rtc-core-y += rtc-efi-platform.o
> +endif
> +
> +rtc-core-$(CONFIG_RTC_NVMEM) += nvmem.o
> +rtc-core-$(CONFIG_RTC_INTF_DEV) += dev.o
> +rtc-core-$(CONFIG_RTC_INTF_PROC) += proc.o
> +rtc-core-$(CONFIG_RTC_INTF_SYSFS) += sysfs.o
> +
> +# Keep the list ordered.
> +
> +obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
> +obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o
> +obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
> +obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o
> +obj-$(CONFIG_RTC_DRV_ABB5ZES3) += rtc-ab-b5ze-s3.o
> +obj-$(CONFIG_RTC_DRV_ABEOZ9) += rtc-ab-eoz9.o
> +obj-$(CONFIG_RTC_DRV_ABX80X) += rtc-abx80x.o
> +obj-$(CONFIG_RTC_DRV_AC100) += rtc-ac100.o
> +obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o
> +obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o
> +obj-$(CONFIG_RTC_DRV_ASM9260) += rtc-asm9260.o
> +obj-$(CONFIG_RTC_DRV_ASPEED) += rtc-aspeed.o
> +obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
> +obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o
> +obj-$(CONFIG_RTC_DRV_AU1XXX) += rtc-au1xxx.o
> +obj-$(CONFIG_RTC_DRV_BD70528) += rtc-bd70528.o
> +obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
> +obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
> +obj-$(CONFIG_RTC_DRV_BRCMSTB) += rtc-brcmstb-waketimer.o
> +obj-$(CONFIG_RTC_DRV_CADENCE) += rtc-cadence.o
> +obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
> +obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
> +obj-$(CONFIG_RTC_DRV_CPCAP) += rtc-cpcap.o
> +obj-$(CONFIG_RTC_DRV_CROS_EC) += rtc-cros-ec.o
> +obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o
> +obj-$(CONFIG_RTC_DRV_DA9055) += rtc-da9055.o
> +obj-$(CONFIG_RTC_DRV_DA9063) += rtc-da9063.o
> +obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
> +obj-$(CONFIG_RTC_DRV_DIGICOLOR) += rtc-digicolor.o
> +obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
> +obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
> +obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
> +obj-$(CONFIG_RTC_DRV_DS1302) += rtc-ds1302.o
> +obj-$(CONFIG_RTC_DRV_DS1305) += rtc-ds1305.o
> +obj-$(CONFIG_RTC_DRV_DS1307) += rtc-ds1307.o
> +obj-$(CONFIG_RTC_DRV_DS1343) += rtc-ds1343.o
> +obj-$(CONFIG_RTC_DRV_DS1347) += rtc-ds1347.o
> +obj-$(CONFIG_RTC_DRV_DS1374) += rtc-ds1374.o
> +obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds1390.o
> +obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o
> +obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o
> +obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
> +obj-$(CONFIG_RTC_DRV_DS1685_FAMILY) += rtc-ds1685.o
> +obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
> +obj-$(CONFIG_RTC_DRV_DS2404) += rtc-ds2404.o
> +obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o
> +obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o
> +obj-$(CONFIG_RTC_DRV_EM3027) += rtc-em3027.o
> +obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o
> +obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o
> +obj-$(CONFIG_RTC_DRV_FSL_FTM_ALARM) += rtc-fsl-ftm-alarm.o
> +obj-$(CONFIG_RTC_DRV_FTRTC010) += rtc-ftrtc010.o
> +obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o
> +obj-$(CONFIG_RTC_DRV_GOLDFISH) += rtc-goldfish.o
> +obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
> +obj-$(CONFIG_RTC_DRV_HYM8563) += rtc-hym8563.o
> +obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o
> +obj-$(CONFIG_RTC_DRV_IMX_SC) += rtc-imx-sc.o
> +obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
> +obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
> +obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o
> +obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o
> +obj-$(CONFIG_RTC_DRV_LOONGSON1) += rtc-ls1x.o
> +obj-$(CONFIG_RTC_DRV_LP8788) += rtc-lp8788.o
> +obj-$(CONFIG_RTC_DRV_LPC24XX) += rtc-lpc24xx.o
> +obj-$(CONFIG_RTC_DRV_LPC32XX) += rtc-lpc32xx.o
> +obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o
> +obj-$(CONFIG_RTC_DRV_M41T93) += rtc-m41t93.o
> +obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o
> +obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o
> +obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o
> +obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o
> +obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o
> +obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o
> +obj-$(CONFIG_RTC_DRV_MAX6916) += rtc-max6916.o
> +obj-$(CONFIG_RTC_DRV_MAX77686) += rtc-max77686.o
> +obj-$(CONFIG_RTC_DRV_MAX8907) += rtc-max8907.o
> +obj-$(CONFIG_RTC_DRV_MAX8925) += rtc-max8925.o
> +obj-$(CONFIG_RTC_DRV_MAX8997) += rtc-max8997.o
> +obj-$(CONFIG_RTC_DRV_MAX8998) += rtc-max8998.o
> +obj-$(CONFIG_RTC_DRV_MESON_VRTC)+= rtc-meson-vrtc.o
> +obj-$(CONFIG_RTC_DRV_MC13XXX) += rtc-mc13xxx.o
> +obj-$(CONFIG_RTC_DRV_MCP795) += rtc-mcp795.o
> +obj-$(CONFIG_RTC_DRV_MESON) += rtc-meson.o
> +obj-$(CONFIG_RTC_DRV_MOXART) += rtc-moxart.o
> +obj-$(CONFIG_RTC_DRV_MPC5121) += rtc-mpc5121.o
> +obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o
> +obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
> +obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o
> +obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o
> +obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o
> +obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o
> +obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o
> +obj-$(CONFIG_RTC_DRV_OPAL) += rtc-opal.o
> +obj-$(CONFIG_RTC_DRV_PALMAS) += rtc-palmas.o
> +obj-$(CONFIG_RTC_DRV_PCAP) += rtc-pcap.o
> +obj-$(CONFIG_RTC_DRV_PCF2123) += rtc-pcf2123.o
> +obj-$(CONFIG_RTC_DRV_PCF2127) += rtc-pcf2127.o
> +obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o
> +obj-$(CONFIG_RTC_DRV_PCF85063) += rtc-pcf85063.o
> +obj-$(CONFIG_RTC_DRV_PCF8523) += rtc-pcf8523.o
> +obj-$(CONFIG_RTC_DRV_PCF85363) += rtc-pcf85363.o
> +obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o
> +obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o
> +obj-$(CONFIG_RTC_DRV_PIC32) += rtc-pic32.o
> +obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o
> +obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
> +obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o
> +obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o
> +obj-$(CONFIG_RTC_DRV_PUV3) += rtc-puv3.o
> +obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o
> +obj-$(CONFIG_RTC_DRV_R7301) += rtc-r7301.o
> +obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o
> +obj-$(CONFIG_RTC_DRV_RC5T583) += rtc-rc5t583.o
> +obj-$(CONFIG_RTC_DRV_RK808) += rtc-rk808.o
> +obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c01.o
> +obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o
> +obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o
> +obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o
> +obj-$(CONFIG_RTC_DRV_RTD119X) += rtc-rtd119x.o
> +obj-$(CONFIG_RTC_DRV_RV3028) += rtc-rv3028.o
> +obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o
> +obj-$(CONFIG_RTC_DRV_RV8803) += rtc-rv8803.o
> +obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o
> +obj-$(CONFIG_RTC_DRV_RX6110) += rtc-rx6110.o
> +obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o
> +obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o
> +obj-$(CONFIG_RTC_DRV_RX8130) += rtc-rx8130.o
> +obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o
> +obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o
> +obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o
> +obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o
> +obj-$(CONFIG_RTC_DRV_SA1100) += rtc-sa1100.o
> +obj-$(CONFIG_RTC_DRV_SC27XX) += rtc-sc27xx.o
> +obj-$(CONFIG_RTC_DRV_SD3078) += rtc-sd3078.o
> +obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
> +obj-$(CONFIG_RTC_DRV_SIRFSOC) += rtc-sirfsoc.o
> +obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o
> +obj-$(CONFIG_RTC_DRV_SPEAR) += rtc-spear.o
> +obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
> +obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
> +obj-$(CONFIG_RTC_DRV_ST_LPC) += rtc-st-lpc.o
> +obj-$(CONFIG_RTC_DRV_STM32) += rtc-stm32.o
> +obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o
> +obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
> +obj-$(CONFIG_RTC_DRV_SUN6I) += rtc-sun6i.o
> +obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o
> +obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o
> +obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
> +obj-$(CONFIG_RTC_DRV_TPS6586X) += rtc-tps6586x.o
> +obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o
> +obj-$(CONFIG_RTC_DRV_TPS80031) += rtc-tps80031.o
> +obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o
> +obj-$(CONFIG_RTC_DRV_TX4939) += rtc-tx4939.o
> +obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o
> +obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o
> +obj-$(CONFIG_RTC_DRV_VRTC) += rtc-mrst.o
> +obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o
> +obj-$(CONFIG_RTC_DRV_WILCO_EC) += rtc-wilco-ec.o
> +obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o
> +obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o
> +obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
> +obj-$(CONFIG_RTC_DRV_XGENE) += rtc-xgene.o
> +obj-$(CONFIG_RTC_DRV_ZYNQMP) += rtc-zynqmp.o
> diff --git a/target/linux/mvebu/files/drivers/rtc/rtc-rx8130.c b/target/linux/mvebu/files/drivers/rtc/rtc-rx8130.c
> new file mode 100644
> index 0000000000..239744341e
> --- /dev/null
> +++ b/target/linux/mvebu/files/drivers/rtc/rtc-rx8130.c
> @@ -0,0 +1,807 @@
> +//======================================================================
> +// Driver for the Epson RTC module RX-8130 CE
> +//
> +// Copyright(C) SEIKO EPSON CORPORATION 2014. All rights reserved.
> +//
> +// Derived from RX-8025 driver:
> +// Copyright (C) 2009 Wolfgang Grandegger <wg at grandegger.com>
> +//
> +// Copyright (C) 2005 by Digi International Inc.
> +// All rights reserved.
> +//
> +// Modified by fengjh at rising.com.cn
> +// <http://lists.lm-sensors.org/mailman/listinfo/lm-sensors>
> +// 2006.11
> +//
> +// Code cleanup by Sergei Poselenov, <sposelenov at emcraft.com>
> +// Converted to new style by Wolfgang Grandegger <wg at grandegger.com>
> +// Alarm and periodic interrupt added by Dmitry Rakhchev <rda at emcraft.com>
> +//
> +//
> +// This driver software is distributed as is, without any warranty of any kind,
> +// either express or implied as further specified in the GNU Public License. This
> +// software may be used and distributed according to the terms of the GNU Public
> +// License, version 2 as published by the Free Software Foundation.
> +// See the file COPYING in the main directory of this archive for more details.
> +//
> +// You should have received a copy of the GNU General Public License along with
> +// this program. If not, see <http://www.gnu.org/licenses/>.
> +//======================================================================
> +
> +#if 1
> +#define DEBUG
> +#include <linux/device.h>
> +#undef DEBUG
> +#endif
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/init.h>
> +#include <linux/bcd.h>
> +#include <linux/i2c.h>
> +#include <linux/list.h>
> +#include <linux/rtc.h>
> +#include <linux/of_gpio.h>
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/interrupt.h>
> +#include <linux/input.h>
> +
> +
> +// RX-8130 Register definitions
> +#define RX8130_REG_SEC 0x10
> +#define RX8130_REG_MIN 0x11
> +#define RX8130_REG_HOUR 0x12
> +#define RX8130_REG_WDAY 0x13
> +#define RX8130_REG_MDAY 0x14
> +#define RX8130_REG_MONTH 0x15
> +#define RX8130_REG_YEAR 0x16
> +
> +#define RX8130_REG_ALMIN 0x17
> +#define RX8130_REG_ALHOUR 0x18
> +#define RX8130_REG_ALWDAY 0x19
> +#define RX8130_REG_TCOUNT0 0x1A
> +#define RX8130_REG_TCOUNT1 0x1B
> +#define RX8130_REG_EXT 0x1C
> +#define RX8130_REG_FLAG 0x1D
> +#define RX8130_REG_CTRL0 0x1E
> +#define RX8130_REG_CTRL1 0x1F
> +
> +#define RX8130_REG_END 0x23
> +
> +// Extension Register (1Ch) bit positions
> +#define RX8130_BIT_EXT_TSEL (7 << 0)
> +#define RX8130_BIT_EXT_WADA (1 << 3)
> +#define RX8130_BIT_EXT_TE (1 << 4)
> +#define RX8130_BIT_EXT_USEL (1 << 5)
> +#define RX8130_BIT_EXT_FSEL (3 << 6)
> +
> +// Flag Register (1Dh) bit positions
> +#define RX8130_BIT_FLAG_VLF (1 << 1)
> +#define RX8130_BIT_FLAG_AF (1 << 3)
> +#define RX8130_BIT_FLAG_TF (1 << 4)
> +#define RX8130_BIT_FLAG_UF (1 << 5)
> +
> +// Control 0 Register (1Еh) bit positions
> +#define RX8130_BIT_CTRL_TSTP (1 << 2)
> +#define RX8130_BIT_CTRL_AIE (1 << 3)
> +#define RX8130_BIT_CTRL_TIE (1 << 4)
> +#define RX8130_BIT_CTRL_UIE (1 << 5)
> +#define RX8130_BIT_CTRL_STOP (1 << 6)
> +#define RX8130_BIT_CTRL_TEST (1 << 7)
> +
> +
> +static const struct i2c_device_id rx8130_id[] = {
> + { "rx8130", 0 },
> + { }
> +};
> +MODULE_DEVICE_TABLE(i2c, rx8130_id);
> +
> +struct rx8130_data {
> + struct i2c_client *client;
> + struct rtc_device *rtc;
> + struct work_struct work;
> + u8 ctrlreg;
> + unsigned exiting:1;
> +};
> +
> +typedef struct {
> + u8 number;
> + u8 value;
> +}reg_data;
> +
> +#define SE_RTC_REG_READ _IOWR('p', 0x20, reg_data)
> +#define SE_RTC_REG_WRITE _IOW('p', 0x21, reg_data)
> +
> +//----------------------------------------------------------------------
> +// rx8130_read_reg()
> +// reads a rx8130 register (see Register defines)
> +// See also rx8130_read_regs() to read multiple registers.
> +//
> +//----------------------------------------------------------------------
> +static int rx8130_read_reg(struct i2c_client *client, int number, u8 *value)
> +{
> + int ret = i2c_smbus_read_byte_data(client, number) ;
> +
> + //check for error
> + if (ret < 0) {
> + dev_err(&client->dev, "Unable to read register #%d\n", number);
> + return ret;
> + }
> +
> + *value = ret;
> + return 0;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_read_regs()
> +// reads a specified number of rx8130 registers (see Register defines)
> +// See also rx8130_read_reg() to read single register.
> +//
> +//----------------------------------------------------------------------
> +static int rx8130_read_regs(struct i2c_client *client, int number, u8 length, u8 *values)
> +{
> + int ret = i2c_smbus_read_i2c_block_data(client, number, length, values);
> +
> + //check for length error
> + if (ret != length) {
> + dev_err(&client->dev, "Unable to read registers #%d..#%d\n", number, number + length - 1);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_write_reg()
> +// writes a rx8130 register (see Register defines)
> +// See also rx8130_write_regs() to write multiple registers.
> +//
> +//----------------------------------------------------------------------
> +static int rx8130_write_reg(struct i2c_client *client, int number, u8 value)
> +{
> + int ret = i2c_smbus_write_byte_data(client, number, value);
> +
> + //check for error
> + if (ret)
> + dev_err(&client->dev, "Unable to write register #%d\n", number);
> +
> + return ret;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_write_regs()
> +// writes a specified number of rx8130 registers (see Register defines)
> +// See also rx8130_write_reg() to write a single register.
> +//
> +//----------------------------------------------------------------------
> +static int rx8130_write_regs(struct i2c_client *client, int number, u8 length, u8 *values)
> +{
> + int ret = i2c_smbus_write_i2c_block_data(client, number, length, values);
> +
> + //check for error
> + if (ret)
> + dev_err(&client->dev, "Unable to write registers #%d..#%d\n", number, number + length - 1);
> +
> + return ret;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_irq()
> +// irq handler
> +//
> +//----------------------------------------------------------------------
> +static irqreturn_t rx8130_irq(int irq, void *dev_id)
> +{
> + struct i2c_client *client = dev_id;
> + struct rx8130_data *rx8130 = i2c_get_clientdata(client);
> +
> + disable_irq_nosync(irq);
> + schedule_work(&rx8130->work);
> +
> +
> + return IRQ_HANDLED;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_work()
> +//
> +//----------------------------------------------------------------------
> +static void rx8130_work(struct work_struct *work)
> +{
> + struct rx8130_data *rx8130 = container_of(work, struct rx8130_data, work);
> + struct i2c_client *client = rx8130->client;
> + struct mutex *lock = &rx8130->rtc->ops_lock;
> + u8 status;
> +
> + mutex_lock(lock);
> +
> + if (rx8130_read_reg(client, RX8130_REG_FLAG, &status))
> + goto out;
> +
> + // check VLF
> + if ((status & RX8130_BIT_FLAG_VLF))
> + dev_warn(&client->dev, "Frequency stop was detected, probably due to a supply voltage drop\n");
> +
> + dev_dbg(&client->dev, "%s: RX8130_REG_FLAG: %xh\n", __func__, status);
> +
> + // periodic "fixed-cycle" timer
> + if (status & RX8130_BIT_FLAG_TF) {
> + status &= ~RX8130_BIT_FLAG_TF;
> + local_irq_disable();
> + rtc_update_irq(rx8130->rtc, 1, RTC_PF | RTC_IRQF);
> + local_irq_enable();
> + }
> +
> + // alarm function
> + if (status & RX8130_BIT_FLAG_AF) {
> + status &= ~RX8130_BIT_FLAG_AF;
> + local_irq_disable();
> + rtc_update_irq(rx8130->rtc, 1, RTC_AF | RTC_IRQF);
> + local_irq_enable();
> + }
> +
> + // time update function
> + if (status & RX8130_BIT_FLAG_UF) {
> + status &= ~RX8130_BIT_FLAG_UF;
> + local_irq_disable();
> + rtc_update_irq(rx8130->rtc, 1, RTC_UF | RTC_IRQF);
> + local_irq_enable();
> + }
> +
> + // acknowledge IRQ
> + rx8130_write_reg(client, RX8130_REG_FLAG, status); //clear flags
> +
> +out:
> + if (!rx8130->exiting)
> + enable_irq(client->irq);
> +
> + mutex_unlock(lock);
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_get_time()
> +// gets the current time from the rx8130 registers
> +//
> +//----------------------------------------------------------------------
> +static int rx8130_get_time(struct device *dev, struct rtc_time *dt)
> +{
> + struct rx8130_data *rx8130 = dev_get_drvdata(dev);
> + u8 date[7];
> + int err;
> +
> + err = rx8130_read_regs(rx8130->client, RX8130_REG_SEC, 7, date);
> + if (err)
> + return err;
> +
> + dev_dbg(dev, "%s: read 0x%02x 0x%02x "
> + "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", __func__,
> + date[0], date[1], date[2], date[3], date[4], date[5], date[6]);
> +
> + //Note: need to subtract 0x10 for index as register offset starts at 0x10
> + dt->tm_sec = bcd2bin(date[RX8130_REG_SEC -0x10] & 0x7f);
> + dt->tm_min = bcd2bin(date[RX8130_REG_MIN -0x10] & 0x7f);
> + dt->tm_hour = bcd2bin(date[RX8130_REG_HOUR -0x10] & 0x3f); //only 24-hour clock
> + dt->tm_mday = bcd2bin(date[RX8130_REG_MDAY -0x10] & 0x3f);
> + dt->tm_mon = bcd2bin(date[RX8130_REG_MONTH-0x10] & 0x1f) - 1;
> + dt->tm_year = bcd2bin(date[RX8130_REG_YEAR -0x10]);
> + dt->tm_wday = bcd2bin(date[RX8130_REG_WDAY -0x10] & 0x7f);
> +
> + if (dt->tm_year < 70)
> + dt->tm_year += 100;
> +
> + dev_dbg(dev, "%s: date %ds %dm %dh %dmd %dm %dy\n", __func__,
> + dt->tm_sec, dt->tm_min, dt->tm_hour,
> + dt->tm_mday, dt->tm_mon, dt->tm_year);
> +
> + return rtc_valid_tm(dt);
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_set_time()
> +// Sets the current time in the rx8130 registers
> +//
> +// Note: If STOP is not set/cleared, the clock will start when the seconds
> +// register is written
> +//
> +//----------------------------------------------------------------------
> +static int rx8130_set_time(struct device *dev, struct rtc_time *dt)
> +{
> + struct rx8130_data *rx8130 = dev_get_drvdata(dev);
> + u8 date[7];
> + u8 ctrl;
> + int ret;
> +
> + //set STOP bit before changing clock/calendar
> + rx8130_read_reg(rx8130->client, RX8130_REG_CTRL0, &ctrl);
> + rx8130->ctrlreg = ctrl | RX8130_BIT_CTRL_STOP;
> + rx8130_write_reg(rx8130->client, RX8130_REG_CTRL0, rx8130->ctrlreg);
> +
> + dev_dbg(dev, "%s: date %ds %dm %dh %dmd %dm %dy\n", __func__,
> + dt->tm_sec, dt->tm_min, dt->tm_hour,
> + dt->tm_mday, dt->tm_mon, dt->tm_year);
> +
> + //Note: need to subtract 0x10 for index as register offset starts at 0x10
> + date[RX8130_REG_SEC-0x10] = bin2bcd(dt->tm_sec);
> + date[RX8130_REG_MIN-0x10] = bin2bcd(dt->tm_min);
> + date[RX8130_REG_HOUR-0x10] = bin2bcd(dt->tm_hour); //only 24hr time
> +
> + date[RX8130_REG_MDAY-0x10] = bin2bcd(dt->tm_mday);
> + date[RX8130_REG_MONTH-0x10] = bin2bcd(dt->tm_mon + 1);
> + date[RX8130_REG_YEAR-0x10] = bin2bcd(dt->tm_year % 100);
> + date[RX8130_REG_WDAY-0x10] = bin2bcd(dt->tm_wday);
> +
> + dev_dbg(dev, "%s: write 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
> + __func__, date[0], date[1], date[2], date[3], date[4], date[5], date[6]);
> +
> + ret = rx8130_write_regs(rx8130->client, RX8130_REG_SEC, 7, date);
> +
> + //clear STOP bit after changing clock/calendar
> + rx8130_read_reg(rx8130->client, RX8130_REG_CTRL0, &ctrl);
> + rx8130->ctrlreg = ctrl & ~RX8130_BIT_CTRL_STOP;
> + rx8130_write_reg(rx8130->client, RX8130_REG_CTRL0, rx8130->ctrlreg);
> +
> + return ret;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_init_client()
> +// initializes the rx8130
> +//
> +//----------------------------------------------------------------------
> +static int rx8130_init_client(struct i2c_client *client, int *need_reset)
> +{
> + struct rx8130_data *rx8130 = i2c_get_clientdata(client);
> + u8 ctrl[3];
> + int need_clear = 0;
> + int err;
> +
> + //get current extension, flag, control register values
> + dev_dbg(&client->dev, "Trying to read RX8130_REG_EXT\n");
> + err = rx8130_read_regs(rx8130->client, RX8130_REG_EXT, 3, ctrl);
> + if (err)
> + goto out;
> +
> + //set extension register, TE to 0, FSEL1-0 and TSEL2-0 for desired frequency
> + ctrl[0] &= ~RX8130_BIT_EXT_TE; //set TE to 0
> + ctrl[0] &= ~RX8130_BIT_EXT_FSEL; //set to 0 (off) for this case
> + ctrl[0] |= 0x02; //set TSEL for 1Hz
> + err = rx8130_write_reg(client, RX8130_REG_EXT, ctrl[0]);
> + if (err)
> + goto out;
> +
> + //clear "test bit"
> + rx8130->ctrlreg = (ctrl[2] & ~RX8130_BIT_CTRL_TEST);
> +
> + //check for VLF Flag (set at power-on)
> + if ((ctrl[1] & RX8130_BIT_FLAG_VLF)) {
> + dev_warn(&client->dev, "Frequency stop was detected, probably due to a supply voltage drop\n");
> + *need_reset = 1;
> + }
> +
> + //check for Alarm Flag
> + if (ctrl[1] & RX8130_BIT_FLAG_AF) {
> + dev_warn(&client->dev, "Alarm was detected\n");
> + need_clear = 1;
> + }
> +
> + //check for Periodic Timer Flag
> + if (ctrl[1] & RX8130_BIT_FLAG_TF) {
> + dev_warn(&client->dev, "Periodic timer was detected\n");
> + need_clear = 1;
> + }
> +
> + //check for Update Timer Flag
> + if (ctrl[1] & RX8130_BIT_FLAG_UF) {
> + dev_warn(&client->dev, "Update timer was detected\n");
> + need_clear = 1;
> + }
> +
> + //reset or clear needed?
> + if (*need_reset || need_clear) {
> + //clear flag register
> + err = rx8130_write_reg(client, RX8130_REG_FLAG, 0x00);
> + if (err)
> + goto out;
> +
> + //clear ctrl register
> + err = rx8130_write_reg(client, RX8130_REG_CTRL0, 0x00);
> + if (err)
> + goto out;
> + }
> +out:
> + return err;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_read_alarm()
> +// reads current Alarm
> +//----------------------------------------------------------------------
> +static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
> +{
> + struct rx8130_data *rx8130 = dev_get_drvdata(dev);
> + struct i2c_client *client = rx8130->client;
> + u8 alarmvals[3]; //minute, hour, week/day values
> + u8 ctrl[3]; //extension, flag, control values
> + int err;
> +
> + if (client->irq <= 0)
> + return -EINVAL;
> +
> + //get current minute, hour, week/day alarm values
> + err = rx8130_read_regs(client, RX8130_REG_ALMIN, 3, alarmvals);
> + if (err)
> + return err;
> + dev_dbg(dev, "%s: minutes:0x%02x hours:0x%02x week/day:0x%02x\n",
> + __func__, alarmvals[0], alarmvals[1], alarmvals[2]);
> +
> +
> + //get current extension, flag, control register values
> + err = rx8130_read_regs(client, RX8130_REG_EXT, 3, ctrl);
> + if (err)
> + return err;
> + dev_dbg(dev, "%s: extension:0x%02x flag:0x%02x control:0x%02x \n",
> + __func__, ctrl[0], ctrl[1], ctrl[2]);
> +
> + // Hardware alarm precision is 1 minute
> + t->time.tm_sec = 0;
> + t->time.tm_min = bcd2bin(alarmvals[0] & 0x7f); //0x7f filters AE bit currently
> + t->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f); //0x3f filters AE bit currently, also 24hr only
> +
> + t->time.tm_wday = -1;
> + t->time.tm_mday = -1;
> + t->time.tm_mon = -1;
> + t->time.tm_year = -1;
> +
> + dev_dbg(dev, "%s: date: %ds %dm %dh %dmd %dm %dy\n",
> + __func__,
> + t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
> + t->time.tm_mday, t->time.tm_mon, t->time.tm_year);
> +
> + t->enabled = !!(rx8130->ctrlreg & RX8130_BIT_CTRL_AIE); //check if interrupt is enabled
> + t->pending = (ctrl[1] & RX8130_BIT_FLAG_AF) && t->enabled; //check if flag is triggered
> +
> + return err;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_set_alarm()
> +// sets Alarm
> +//----------------------------------------------------------------------
> +static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct rx8130_data *rx8130 = dev_get_drvdata(dev);
> + u8 alarmvals[3]; //minute, hour, day
> + u8 extreg; //extension register
> + u8 flagreg; //flag register
> + int err;
> +
> + if (client->irq <= 0)
> + return -EINVAL;
> +
> + //get current extension register
> + err = rx8130_read_reg(client, RX8130_REG_EXT, &extreg);
> + if (err <0)
> + return err;
> +
> + //get current flag register
> + err = rx8130_read_reg(client, RX8130_REG_FLAG, &flagreg);
> + if (err <0)
> + return err;
> +
> + // Hardware alarm precision is 1 minute
> + alarmvals[0] = bin2bcd(t->time.tm_min);
> + alarmvals[1] = bin2bcd(t->time.tm_hour);
> + alarmvals[2] = bin2bcd(t->time.tm_mday);
> + dev_dbg(dev, "%s: write 0x%02x 0x%02x 0x%02x\n", __func__, alarmvals[0], alarmvals[1], alarmvals[2]);
> +
> + //check interrupt enable and disable
> + if (rx8130->ctrlreg & (RX8130_BIT_CTRL_AIE | RX8130_BIT_CTRL_UIE)) {
> + rx8130->ctrlreg &= ~(RX8130_BIT_CTRL_AIE | RX8130_BIT_CTRL_UIE);
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_CTRL0, rx8130->ctrlreg);
> + if (err)
> + return err;
> + }
> +
> + //write the new minute and hour values
> + //Note:assume minute and hour values will be enabled. Bit 7 of each of the
> + // minute, hour, week/day register can be set which will "disable" the
> + // register from triggering an alarm. See the RX8130 spec for more information
> + err = rx8130_write_regs(rx8130->client, RX8130_REG_ALMIN, 2, alarmvals);
> + if (err)
> + return err;
> +
> + //set Week/Day bit
> + // Week setting is typically not used, so we will assume "day" setting
> + extreg |= RX8130_BIT_EXT_WADA; //set to "day of month"
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_EXT, extreg);
> + if (err)
> + return err;
> +
> + //set Day of Month register
> + if (alarmvals[2] == 0) {
> + alarmvals[2] |= 0x80; //turn on AE bit to ignore day of month (no zero day)
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_ALWDAY, alarmvals[2]);
> + }
> + else {
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_ALWDAY, alarmvals[2]);
> + }
> + if (err)
> + return err;
> +
> + //clear Alarm Flag
> + flagreg &= ~(RX8130_BIT_FLAG_AF | RX8130_BIT_FLAG_UF);
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_FLAG, flagreg);
> + if (err)
> + return err;
> +
> + //re-enable interrupt if required
> + if (t->enabled) {
> +
> + if ( rx8130->rtc->uie_rtctimer.enabled )
> + rx8130->ctrlreg |= RX8130_BIT_CTRL_UIE; //set update interrupt enable
> + if ( rx8130->rtc->aie_timer.enabled )
> + rx8130->ctrlreg |= (RX8130_BIT_CTRL_AIE | RX8130_BIT_CTRL_UIE); //set alarm interrupt enable
> +
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_CTRL0, rx8130->ctrlreg);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_alarm_irq_enable()
> +// sets enables Alarm IRQ
> +//----------------------------------------------------------------------
> +static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct rx8130_data *rx8130 = dev_get_drvdata(dev);
> + u8 flagreg;
> + u8 ctrl;
> + int err;
> +
> + //get the current ctrl settings
> + ctrl = rx8130->ctrlreg;
> +
> + if (enabled)
> + {
> + if ( rx8130->rtc->uie_rtctimer.enabled )
> + ctrl |= RX8130_BIT_CTRL_UIE; //set update interrupt enable
> + if ( rx8130->rtc->aie_timer.enabled )
> + ctrl |= (RX8130_BIT_CTRL_AIE | RX8130_BIT_CTRL_UIE); //set alarm interrupt enable
> + }
> + else
> + {
> + if ( ! rx8130->rtc->uie_rtctimer.enabled )
> + ctrl &= ~RX8130_BIT_CTRL_UIE; //clear update interrupt enable
> + if ( ! rx8130->rtc->aie_timer.enabled )
> + {
> + if ( rx8130->rtc->uie_rtctimer.enabled )
> + ctrl &= ~RX8130_BIT_CTRL_AIE;
> + else
> + ctrl &= ~(RX8130_BIT_CTRL_AIE | RX8130_BIT_CTRL_UIE); //clear alarm interrupt enable
> + }
> + }
> +
> + //clear alarm flag
> + err = rx8130_read_reg(client, RX8130_REG_FLAG, &flagreg);
> + if (err <0)
> + return err;
> + flagreg &= ~RX8130_BIT_FLAG_AF;
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_FLAG, flagreg);
> + if (err)
> + return err;
> +
> + //update the Control register if the setting changed
> + if (ctrl != rx8130->ctrlreg) {
> + rx8130->ctrlreg = ctrl;
> + err = rx8130_write_reg(rx8130->client, RX8130_REG_CTRL0, rx8130->ctrlreg);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +//---------------------------------------------------------------------------
> +// rx8130_ioctl()
> +//
> +//---------------------------------------------------------------------------
> +static int rx8130_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + //struct rx8130_data *rx8130 = dev_get_drvdata(dev);
> + //struct mutex *lock = &rx8130->rtc->ops_lock;
> + int ret = 0;
> + int tmp;
> + void __user *argp = (void __user *)arg;
> + reg_data reg;
> +
> + dev_dbg(dev, "%s: cmd=%x\n", __func__, cmd);
> +
> + switch (cmd) {
> + case SE_RTC_REG_READ:
> + if (copy_from_user(®, argp, sizeof(reg)))
> + return -EFAULT;
> + if ( reg.number < RX8130_REG_SEC || reg.number > RX8130_REG_END )
> + return -EFAULT;
> + //mutex_lock(lock);
> + ret = rx8130_read_reg(client, reg.number, ®.value);
> + //mutex_unlock(lock);
> + if (! ret )
> + return copy_to_user(argp, ®, sizeof(reg)) ? -EFAULT : 0;
> + break;
> +
> + case SE_RTC_REG_WRITE:
> + if (copy_from_user(®, argp, sizeof(reg)))
> + return -EFAULT;
> + if ( reg.number < RX8130_REG_SEC || reg.number > RX8130_REG_END )
> + return -EFAULT;
> + //mutex_lock(lock);
> + ret = rx8130_write_reg(client, reg.number, reg.value);
> + //mutex_unlock(lock);
> + break;
> +
> + case RTC_VL_READ:
> + //mutex_lock(lock);
> + ret = rx8130_read_reg(client, RX8130_REG_FLAG, ®.value);
> + //mutex_unlock(lock);
> + if (! ret)
> + {
> + tmp = !!(reg.value & RX8130_BIT_FLAG_VLF);
> + return copy_to_user(argp, &tmp, sizeof(tmp)) ? -EFAULT : 0;
> + }
> + break;
> +
> + case RTC_VL_CLR:
> + //mutex_lock(lock);
> + ret = rx8130_read_reg(client, RX8130_REG_FLAG, ®.value);
> + if (! ret)
> + {
> + reg.value &= ~RX8130_BIT_FLAG_VLF;
> + ret = rx8130_write_reg(client, RX8130_REG_FLAG, reg.value);
> + }
> + //mutex_unlock(lock);
> + break;
> +
> + default:
> + return -ENOIOCTLCMD;
> + }
> +
> + return ret;
> +}
> +
> +static struct rtc_class_ops rx8130_rtc_ops = {
> + .read_time = rx8130_get_time,
> + .set_time = rx8130_set_time,
> + .read_alarm = rx8130_read_alarm,
> + .set_alarm = rx8130_set_alarm,
> + .alarm_irq_enable = rx8130_alarm_irq_enable,
> + .ioctl = rx8130_ioctl,
> +};
> +
> +//----------------------------------------------------------------------
> +// rx8130_probe()
> +// probe routine for the rx8130 driver
> +//
> +// Todo: - maybe change kzalloc to use devm_kzalloc
> +// -
> +//----------------------------------------------------------------------
> +static int rx8130_probe(struct i2c_client *client, const struct i2c_device_id *id)
> +{
> + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
> + struct rx8130_data *rx8130;
> + int err, need_reset = 0;
> +
> + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) {
> + dev_err(&adapter->dev, "doesn't support required functionality\n");
> + err = -EIO;
> + goto errout;
> + }
> +
> + rx8130 = kzalloc(sizeof(*rx8130), GFP_KERNEL);
> + if (!rx8130) {
> + dev_err(&adapter->dev, "failed to alloc memory\n");
> + err = -ENOMEM;
> + goto errout;
> + }
> +
> + rx8130->client = client;
> + i2c_set_clientdata(client, rx8130);
> + INIT_WORK(&rx8130->work, rx8130_work);
> +
> + err = rx8130_init_client(client, &need_reset);
> + if (err)
> + goto errout_free;
> +
> + if (need_reset) {
> + struct rtc_time tm;
> + dev_info(&client->dev, "bad conditions detected, resetting date\n");
> + rtc_time64_to_tm(0, &tm); // set to 1970/1/1
> + rx8130_set_time(&client->dev, &tm);
> + }
> +
> + rx8130->rtc = devm_rtc_device_register(&client->dev, client->name, &rx8130_rtc_ops, THIS_MODULE);
> +
> + if (IS_ERR(rx8130->rtc)) {
> + err = PTR_ERR(rx8130->rtc);
> + dev_err(&client->dev, "unable to register the class device\n");
> + goto errout_free;
> + }
> +
> + if (client->irq > 0) {
> + dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
> + err = devm_request_threaded_irq(&client->dev,client->irq, NULL, rx8130_irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT,"rx8130", client);
> +
> + if (err) {
> + dev_err(&client->dev, "unable to request IRQ\n");
> + goto errout_reg;
> + }
> + }
> +
> +
> + rx8130->rtc->irq_freq = 1;
> + rx8130->rtc->max_user_freq = 1;
> +
> + return 0;
> +
> +errout_reg:
> +// rtc_device_unregister(rx8130->rtc);
> +
> +errout_free:
> + kfree(rx8130);
> +
> +errout:
> + dev_err(&adapter->dev, "probing for rx8130 failed\n");
> + return err;
> +}
> +
> +//----------------------------------------------------------------------
> +// rx8130_remove()
> +// remove routine for the rx8130 driver
> +//
> +// Todo: - maybe change kzalloc to devm_kzalloc
> +// -
> +//----------------------------------------------------------------------
> +static int rx8130_remove(struct i2c_client *client)
> +{
> + struct rx8130_data *rx8130 = i2c_get_clientdata(client);
> + struct mutex *lock = &rx8130->rtc->ops_lock;
> +
> + if (client->irq > 0) {
> + mutex_lock(lock);
> + rx8130->exiting = 1;
> + mutex_unlock(lock);
> +
> + free_irq(client->irq, client);
> + cancel_work_sync(&rx8130->work);
> + }
> +
> +// rtc_device_unregister(rx8130->rtc);
> +
> + kfree(rx8130);
> + return 0;
> +}
> +
> +static struct i2c_driver rx8130_driver = {
> + .driver = {
> + .name = "rtc-rx8130",
> + .owner = THIS_MODULE,
> + },
> + .probe = rx8130_probe,
> + .remove = rx8130_remove,
> + .id_table = rx8130_id,
> +};
> +
> +module_i2c_driver(rx8130_driver);
> +
> +MODULE_AUTHOR("Val Krutov <vkrutov at eea.epson.com>");
> +MODULE_DESCRIPTION("RX8130CE RTC driver");
> +MODULE_LICENSE("GPL");
> diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
> index 1440c07a0b..0008908b77 100644
> --- a/target/linux/mvebu/image/cortexa72.mk
> +++ b/target/linux/mvebu/image/cortexa72.mk
> @@ -43,3 +43,23 @@ define Device/marvell_macchiatobin-singleshot
> SUPPORTED_DEVICES := marvell,armada8040-mcbin-singleshot
> endef
> TARGET_DEVICES += marvell_macchiatobin-singleshot
> +
> +
> +define Device/marvell_puzzle-m901-cn9131-db
> + $(call Device/Default-arm64)
> + DEVICE_VENDOR := iEi
> + DEVICE_MODEL := Puzzle-M901
> + DEVICE_DTS := puzzle-m901-cn9131-db
> + IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
> +endef
> +TARGET_DEVICES += marvell_puzzle-m901-cn9131-db
> +
> +define Device/marvell_puzzle-m902-cn9132-db
> + $(call Device/Default-arm64)
> + DEVICE_VENDOR := iEi
> + DEVICE_MODEL := Puzzle-M902
> + DEVICE_DTS := puzzle-m902-cn9132-db
> + IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
> +endef
> +TARGET_DEVICES += marvell_puzzle-m902-cn9132-db
> +
> --
> 2.17.1
>
>
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