[PATCH] ramips: mt7621: remove redundant lpj re-calibration
Ilya Lipnitskiy
ilya.lipnitskiy at gmail.com
Sun Mar 7 22:38:31 GMT 2021
When the patch was originally introduced [0], it claimed that on mt7621,
CPU core 1 came up with a bad BogoMIPS value because the clock needed
time to stabilize. That is not the case today, at least on my Ubiquity
EdgeRouter X device. As evident from messages below, the LPJ value is
already correct after the original delay loop calibration.
Original calibration:
[ 0.033728] Calibrating delay loop... 583.68 BogoMIPS (lpj=1167360)
Redundant re-calibration (this patch removes it):
[ 0.788770] 4 CPUs re-calibrate udelay(lpj = 1167360)
So, remove the re-calibration patch to avoid extra busy looping to come
up with the exact same lpj value.
This patch also disables CONFIG_GENERIC_CLOCKEVENTS_BROADCAST as it does
not seem necessary for mt7621 - ER-X boots and functions correctly
without that symbol and no other ramips targets enable it.
This change is only for Linux 5.10, it does not affect Linux 5.4 builds.
Lastly, refresh existing patches to account for the removal of the
re-calibration logic.
[0]: 6acb53c52 ("ralink: fix rcu_sched stalls on mt7621")
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy at gmail.com>
Cc: John Crispin <john at phrozen.org>
---
target/linux/ramips/mt7621/config-5.10 | 1 -
.../patches-5.10/321-mt7621-timer.patch | 87 -------------------
.../322-mt7621-fix-cpu-clk-add-clkdev.patch | 10 +--
.../323-mt7621-memory-detect.patch | 10 +--
4 files changed, 10 insertions(+), 98 deletions(-)
delete mode 100644 target/linux/ramips/patches-5.10/321-mt7621-timer.patch
diff --git a/target/linux/ramips/mt7621/config-5.10 b/target/linux/ramips/mt7621/config-5.10
index 430ea9513c..1f319da5aa 100644
--- a/target/linux/ramips/mt7621/config-5.10
+++ b/target/linux/ramips/mt7621/config-5.10
@@ -61,7 +61,6 @@ CONFIG_FIXED_PHY=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_GETTIMEOFDAY=y
diff --git a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch b/target/linux/ramips/patches-5.10/321-mt7621-timer.patch
deleted file mode 100644
index 91e14ad63b..0000000000
--- a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch
+++ /dev/null
@@ -1,87 +0,0 @@
---- a/arch/mips/ralink/mt7621.c
-+++ b/arch/mips/ralink/mt7621.c
-@@ -9,6 +9,7 @@
- #include <linux/init.h>
- #include <linux/slab.h>
- #include <linux/sys_soc.h>
-+#include <linux/jiffies.h>
-
- #include <asm/mipsregs.h>
- #include <asm/smp-ops.h>
-@@ -16,6 +17,7 @@
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/mt7621.h>
- #include <asm/mips-boards/launch.h>
-+#include <asm/delay.h>
-
- #include <pinmux.h>
-
-@@ -161,6 +163,58 @@ bool plat_cpu_core_present(int core)
- return true;
- }
-
-+#define LPS_PREC 8
-+/*
-+* Re-calibration lpj(loop-per-jiffy).
-+* (derived from kernel/calibrate.c)
-+*/
-+static int udelay_recal(void)
-+{
-+ unsigned int i, lpj = 0;
-+ unsigned long ticks, loopbit;
-+ int lps_precision = LPS_PREC;
-+
-+ lpj = (1<<12);
-+
-+ while ((lpj <<= 1) != 0) {
-+ /* wait for "start of" clock tick */
-+ ticks = jiffies;
-+ while (ticks == jiffies)
-+ /* nothing */;
-+
-+ /* Go .. */
-+ ticks = jiffies;
-+ __delay(lpj);
-+ ticks = jiffies - ticks;
-+ if (ticks)
-+ break;
-+ }
-+
-+ /*
-+ * Do a binary approximation to get lpj set to
-+ * equal one clock (up to lps_precision bits)
-+ */
-+ lpj >>= 1;
-+ loopbit = lpj;
-+ while (lps_precision-- && (loopbit >>= 1)) {
-+ lpj |= loopbit;
-+ ticks = jiffies;
-+ while (ticks == jiffies)
-+ /* nothing */;
-+ ticks = jiffies;
-+ __delay(lpj);
-+ if (jiffies != ticks) /* longer than 1 tick */
-+ lpj &= ~loopbit;
-+ }
-+ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
-+
-+ for(i=0; i< NR_CPUS; i++)
-+ cpu_data[i].udelay_val = lpj;
-+
-+ return 0;
-+}
-+device_initcall(udelay_recal);
-+
- void prom_soc_init(struct ralink_soc_info *soc_info)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -63,6 +63,7 @@ choice
- select HAVE_PCI if PCI_MT7621
- select SOC_BUS
- select WEAK_REORDERING_BEYOND_LLSC
-+ select GENERIC_CLOCKEVENTS_BROADCAST
- endchoice
-
- choice
diff --git a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
index 723c628790..be5fee54b2 100644
--- a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
+++ b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
@@ -36,10 +36,10 @@
#define MT7621_DDR2_SIZE_MAX 256
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
-@@ -10,6 +10,10 @@
+@@ -9,6 +9,10 @@
+ #include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
- #include <linux/jiffies.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
@@ -47,15 +47,15 @@
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
-@@ -18,6 +22,7 @@
+@@ -16,6 +20,7 @@
+ #include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7621.h>
#include <asm/mips-boards/launch.h>
- #include <asm/delay.h>
+#include <asm/time.h>
#include <pinmux.h>
-@@ -108,11 +113,89 @@ static struct rt2880_pmx_group mt7621_pi
+@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
{ 0 }
};
diff --git a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
index 07c7588661..9f80d02638 100644
--- a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
+++ b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
@@ -44,10 +44,10 @@ Signed-off-by: Chuanhong Guo <gch981213 at gmail.com>
#define MT7621_CHIP_NAME1 0x20203132
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
-@@ -10,11 +10,13 @@
+@@ -9,11 +9,13 @@
+ #include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
- #include <linux/jiffies.h>
+#include <linux/memblock.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
@@ -58,7 +58,7 @@ Signed-off-by: Chuanhong Guo <gch981213 at gmail.com>
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
#include <asm/mips-cps.h>
-@@ -57,6 +59,8 @@
+@@ -55,6 +57,8 @@
#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
#define MT7621_GPIO_MODE_SDHCI_GPIO 1
@@ -67,7 +67,7 @@ Signed-off-by: Chuanhong Guo <gch981213 at gmail.com>
static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
static struct rt2880_pmx_func uart3_grp[] = {
-@@ -141,6 +145,26 @@ static struct clk *__init mt7621_add_sys
+@@ -139,6 +143,26 @@ static struct clk *__init mt7621_add_sys
return clk;
}
@@ -94,7 +94,7 @@ Signed-off-by: Chuanhong Guo <gch981213 at gmail.com>
void __init ralink_clk_init(void)
{
u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
-@@ -346,10 +370,7 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -292,10 +316,7 @@ void prom_soc_init(struct ralink_soc_inf
(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
(rev & CHIP_REV_ECO_MASK));
--
2.30.1
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