[OpenWrt-Devel] [PATCH 1/2] mvebu: cortexa9: correct cpu subtype

Tomasz Maciej Nowak tomek_n at o2.pl
Wed Mar 18 14:04:12 EDT 2020

Armada 370  processors have only 16 double-precision registers. The
change introduced by 8dcc1087602e ("toolchain: ARM: Fix toolchain
compilation for gcc 8.x") switched accidentally the toolchain for mvebu
cortexa9 subtarget to cpu type with 32 double-precision registers. This
stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu
is specified. That change resulted in unusable image, in which kernel
will kill userspace as soon as it causing "Illegal instruction".

Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272
Fixes: 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for
gcc 8.x")
Signed-off-by: Tomasz Maciej Nowak <tomek_n at o2.pl>
 target/linux/mvebu/cortexa9/target.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/linux/mvebu/cortexa9/target.mk b/target/linux/mvebu/cortexa9/target.mk
index 2a75599bc9a3..cdd4d86e4936 100644
--- a/target/linux/mvebu/cortexa9/target.mk
+++ b/target/linux/mvebu/cortexa9/target.mk
@@ -10,5 +10,5 @@ include $(TOPDIR)/rules.mk
 BOARDNAME:=Marvell Armada 37x/38x/XP
 KERNELNAME:=zImage dtbs

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