[OpenWrt-Devel] [PATCH] ath79: switch to kernel 5.4
hauke at hauke-m.de
Thu Jul 2 19:04:55 EDT 2020
On 7/1/20 5:36 PM, Petr Štetiar wrote:
> Hauke Mehrtens <hauke at hauke-m.de> [2020-06-29 00:29:22]:
>> This is set in the configure_status() function:
>> But I think this is not working correctly under some unknown conditions.
>> I printed the read_c0_status() in the do_dsp() function and when this
>> exception occurs the DSPEn bit is *not* set.
> maybe it's due to the following:
> if (cpu_has_dsp)
> status_set |= ST0_MX;
>> Does someone see a bug in the broken version?
>> In this line:
>> 4c: 40826000 mtc0 v0,c0_status
>> in v0 the following bits should be set:
> Seems to be alright:
>> #define ST0_MX 0x01000000
> 2c: 3c040100 lui a0,0x100 << 16 = 0x01000000
>> #define ST0_CU0 0x10000000
> 8: 3c051000 lui a1,0x1000 << 16 = 0x10000000
> I think, that the problem is here, as the ST0_MX bit is set conditionally:
> 20: 30630010 andi v1,v1,0x10
> 24: 10600003 beqz v1,34 <configure_status+0x34>
> if (cpu_data.ases & 0x10) // 0x10 = MIPS_ASE_DSP
> #define MIPS_ASE_DSP 0x00000010
> #define cpu_has_dsp __ase(MIPS_ASE_DSP)
> #define __ase(ase) (cpu_data.ases & (ase))
> and then status_set doesn't have ST0_MX bit set? Just printk the status_set.
> -- ynezz
There is a hazard between a mtc0 in the configure_status() and the mfc0
in the configure_exception_vector() function which is not cleared and
causing this problem. The ST0_MX bit is set, but later we read back the
old value and set the old value again.
This hazard is documented in the "MIPS32® 74K™ Processor Core
FamilySoftware User’s Manual" and "MIPS® Architecture Base: 32-bit
Privileged Resource Architecture Technical Reference Manual"
I send a patch which should fix this problem.
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