[OpenWrt-Devel] [PATCH] ramips: gsw_mt7621: disable PORT 5 MAC RX/TX flow control by default

Petr Štetiar ynezz at true.cz
Tue Feb 11 14:50:22 EST 2020

René van Dorst via openwrt-devel <openwrt-devel at lists.openwrt.org> [2020-02-11 15:59:52]:

[adding Kristian to the Cc: loop]

> > Looking at the current upstream driver implementation, it seems like the
> > TX/RX flow control is enabled only if the flow control pause option is
> > resolved from the device/link partner advertisements (or otherwise set).
> > 
> With upstream you mean mainline 5.5 kernel?

Yes, 5.6-rc1

> In the DTS the CPU port is defined as a fixed-link with pause enabled.
> So the pause bits are always resolved/set.

I see[1] port at 6 with fixed-link, without pause property.

> The hardware can't send the frames fast enough because of the PAUSE frames,
> maybe to a slower device? The CPU is filling the tx ring faster then the
> hardware sending it and eventually CPU overtakes the DMA head. Which causes an
> issue/race/deadlock.

Probably, I didn't tried to reproduce it or planning to do so.

> > Disabling the flow control on PORT 5 MAC seems to fix this issues as the
> > pause frames are then filtered out. While at it, I'm removing the if
> > condition completely as suggested, since this code is run only on mt7621
> > SoC, so there is no need to check for the silicon revisions.
> > 
> Port 6 is connected to the first GMAC of the SOC, not port 5.
> So it should be PORT 6 in your description also 

Ok, I took that "PMCR_P5/PORT 5 MAC Control Register" from
MT7621_ProgrammingGuide_GSW_v01.pdf. Couldnt find anything about P6, it's
quite confusing.

1. https://elixir.bootlin.com/linux/v5.6-rc1/source/drivers/staging/mt7621-dts/mt7621.dtsi#L489

-- ynezz

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