[OpenWrt-Devel] [lantiq] general help on AR10 platform
Hauke Mehrtens
hauke at hauke-m.de
Mon Sep 2 14:41:29 EDT 2019
On 9/2/19 5:38 AM, Enrico Mioso wrote:
> Hello guys,
> Hello Hauke,
>
> Sorry for the amount of mails.
Did you had a look at this vendor device tree file:
https://gitlab.com/gplmirror/telekom-speedport-w925v/blob/master/w925_1.5.001.7_opensource/extern/lantiq-bsp/ugw711-grx550/UGW-7.1.1-SW-CD/Sources/UGW-7.1.1/ugw/target/linux/lantiq/dts/xRX330.dtsi
The arch code is added by these patches on top of kernel 3.10.X:
https://gitlab.com/gplmirror/telekom-speedport-w925v/tree/master/w925_1.5.001.7_opensource/extern/lantiq-bsp/ugw711-grx550/UGW-7.1.1-SW-CD/Sources/UGW-7.1.1/ugw/target/linux/lantiq/patches-3.10
The AR10 is probably partly working wih these kernel patches.
> So in I patched the kernel to be more specific on PMU error messages,
> since it seems something is fundamentally wrong here:
> the system panics like
>
> [ 0.000000] SoC: xRX300 rev 1.2
> [ 0.000000] bootconsole [early0] enabled
Do you use the compatible string lantiq,ar10 for the device?
> [ 0.000000] CPU0 revision is: 00019556 (MIPS 34Kc)
> [ 0.000000] MIPS: machine is AVM FRITZ!Box 3272
> [ 0.000000] Determined physical RAM map:
> [ 0.000000] memory: 08000000 @ 00000000 (usable)
> [ 0.000000] Initrd not found or empty - disabling initrd
> [ 0.000000] Detected 1 available secondary CPU(s)
> [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32
> bytes.
> [ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases,
> linesize 32 bytes
> [ 0.000000] Zone ranges:
> [ 0.000000] Normal [mem 0x0000000000000000-0x0000000007ffffff]
> [ 0.000000] Movable zone start for each node
> [ 0.000000] Early memory node ranges
> [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000007ffffff]
> [ 0.000000] Initmem setup node 0 [mem
> 0x0000000000000000-0x0000000007ffffff]
> [ 0.000000] random: get_random_bytes called from
> start_kernel+0x98/0x4dc with crng_init=0
> [ 0.000000] percpu: Embedded 14 pages/cpu s26256 r8192 d22896 u57344
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480
> [ 0.000000] Kernel command line: [ 0.000000] Dentry cache hash
> table entries: 16384 (order: 4, 65536 bytes)
> [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
> [ 0.000000] Writing ErrCtl register=00050000
> [ 0.000000] Readback ErrCtl register=00050000
> [ 0.000000] Memory: 119048K/131072K available (5210K kernel code,
> 241K rwdata, 1524K rodata, 3376K init, 232K bss, 12024K reserved, 0K
> cma-reserved)
> [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> [ 0.000000] rcu: Hierarchical RCU implementation.
> [ 0.000000] NR_IRQS: 256
> [ 0.000000] deactivating PMU module 0 (clock gate) failed!
> [ 0.000000] deactivating PMU module 0 (clock gate) failed!
> [ 0.000000] deactivating PMU module 0 (clock gate) failed!
> [ 0.000000] deactivating PMU module 0 (clock gate) failed!
> [ 0.000000] deactivating PMU module 0 (clock gate) failed!
> [ 0.000000] deactivating PMU module 0 (clock gate) failed!
Did you add the PUM like this:
pmu0: pmu at 102000 {
compatible = "lantiq,pmu-xway";
reg = <0x102000 0x1000>;
};
Please share your device tree and the other changes you did.
> [ 0.000000] CPU Clock: 333MHz
> [ 0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 11467562725 ns
> [ 0.000018] sched_clock: 32 bits at 166MHz, resolution 6ns, wraps
> every 12884901885ns
> [ 0.012011] Calibrating delay loop... 221.18 BogoMIPS (lpj=442368)
> [ 0.061193] pid_max: default: 32768 minimum: 301
> [ 0.068648] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [ 0.078418] Mountpoint-cache hash table entries: 1024 (order: 0, 4096
> bytes)
> [ 0.094717] rcu: Hierarchical SRCU implementation.
> [ 0.107625] smp: Bringing up secondary CPUs ...
> [ 0.116227] Primary instruction cache 32kB, VIPT, 4-way, linesize 32
> bytes.
> [ 0.116249] Primary data cache 32kB, 4-way, VIPT, cache aliases,
> linesize 32 bytes
> [ 0.116461] CPU1 revision is: 00019556 (MIPS 34Kc)
> [ 0.154663] Synchronize counters for CPU 1: done.
> [ 0.191216] smp: Brought up 1 node, 2 CPUs
> [ 0.202371] clocksource: jiffies: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 7645041785100000 ns
> [ 0.216869] futex hash table entries: 512 (order: 2, 16384 bytes)
> [ 0.226527] pinctrl core: initialized pinctrl subsystem
> [ 0.237723] NET: Registered protocol family 16
> [ 0.265485] dcdc-xrx200 1f106a00.dcdc: Core Voltage : 2040 mV
> [ 0.284748] pinctrl-xway 1e100b10.pinmux: Init done
> [ 0.393384] Kernel panic - not syncing: activating PMU module 0
> (clock gate) failed!
> [ 0.404809] Rebooting in 1 seconds..
> [ 2.865738] Reboot failed -- System halted
>
> Secondly, I am encountering some issues in
> int __init lq_gptu_init(void)
> ... infact vendor firmware is not using
> as I get a data abort at line 798 which reads:
> timer_dev.number_of_timers = GPTU_ID_CFG * 2;
>
> and looking at the vendor firmware, they do something like
> timer_dev.number_of_timers = 3 * 2;
>
> Where may I check for wrong things?
> Thanks!!
>
> Enrico
>
> From 23bc8dd1d48bf7588f3aca1bf90c3999c0d05bcd Mon Sep 17 00:00:00 2001
> From: Enrico Mioso <mrkiko.rs at gmail.com>
> Date: Mon, 2 Sep 2019 05:04:19 +0200
> Subject: [PATCH] lantiq: XWAY: report PMU module for which
> activation/deactivation failed
>
> Helps in diagnosing issues when porting new devices.
>
> Signed-off-by: Enrico Mioso <mrkiko.rs at gmail.com>
> ---
> arch/mips/lantiq/xway/sysctrl.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/mips/lantiq/xway/sysctrl.c
> b/arch/mips/lantiq/xway/sysctrl.c
> index c7f6dee..b30fdcc 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -165,7 +165,7 @@ void ltq_pmu_enable(unsigned int module)
> spin_unlock(&g_pmu_lock);
>
> if (!retry)
> - panic("activating PMU module failed!");
> + panic("activating PMU module %u failed!",module);
> }
> EXPORT_SYMBOL(ltq_pmu_enable);
>
> @@ -180,7 +180,7 @@ void ltq_pmu_disable(unsigned int module)
> spin_unlock(&g_pmu_lock);
>
> if (!retry)
> - pr_warn("deactivating PMU module failed!");
> + pr_warn("deactivating PMU module %u failed!",module);
> }
> EXPORT_SYMBOL(ltq_pmu_disable);
>
> @@ -218,7 +218,7 @@ static int pmu_enable(struct clk *clk)
> }
>
> if (!retry)
> - panic("activating PMU module failed!");
> + panic("activating PMU module %u (clock gate)
> failed!",clk->module);
>
> return 0;
> }
> @@ -243,7 +243,7 @@ static void pmu_disable(struct clk *clk)
> }
>
> if (!retry)
> - pr_warn("deactivating PMU module failed!");
> + pr_warn("deactivating PMU module %u (clock gate)
> failed!",clk->module);
> }
>
> static void usb_set_clock(void)
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