[OpenWrt-Devel] [PATCH] Support for Edimax EW-7476RPC / EW-7478AC

[Birger Koblitz]

Hi Daniel,

On 27.05.19 18:43, Daniel Golle wrote:
> On Mon, May 27, 2019 at 06:35:30PM +0200, Daniel Golle wrote:
>> Hi Birger,
>>
>> thanks for submitting your work. In order to support the external
>> switch, existing generic features should be used in order to
>> implement the phy-reset via GPIO#39.
>> See my comments in the code (I commented the first device only, same
>> applies to the 2nd device as well).
>>
>> On Mon, May 27, 2019 at 05:55:24PM +0200, Birger Koblitz wrote:
>>> ramips: add Netgear EW-7476RPC
This is a typo (or better cut-and-paste which went wrong). The device is
from Edimax.
>>> SoC:   MediaTek MT7620a @ 580MHz
>>> RAM:   64M (Winbond W9751G6KB-25)
>>> FLASH: 8MB (Macronix)
>>> WiFi:  SoC-integrated: MediaTek MT76620a bgn
>> Typo, I supposed. MT7620a (or RT6352 to name the embedded WiFi IP)
Yep.
>>
>>> WiFi:  MediaTek MT7612EN nac
>>> GBE:   RTL8211E
>> Please mention how many phyical ports the device got and if all of
>> them support GbE.
> Sorry, that was stupid of me. I just realized we are talking about a
> wall-wart:
> https://fccid.io/NDD9574761501/Internal-Photos/Internal-Photos-2706172
>
> So it's a simple PHY with 1x GbE obviously ;)

So:

GbE:    1x (RTL8211E)

?

>
>>> +
>>> +&pinctrl {
>>> +       state_default: pinctrl0 {
>>> +               gpio {
>>> +            // might need pin 39: ;
>>> +                       ralink,group = "i2c", "uartf", "nd_sd",
>>> "rgmii2", "spi refclk";
>>> +                       ralink,function = "gpio";
>>> +               };
>>> +       };
>>> +};
>> A pinctrl group for the switch reset would be appropriate:
>> GPIO 39 is p4led_an, hence add:
>> 	phy_reset_pins: phy-reset {
>> 		gpio {
>> 			ralink,group = "p4led_an";
>> 			ralink,function = "gpio";
>> 		};
>> 	};
Ok.
>>> +
>>> +
>>> +&ethernet {
>>> +
>>> +    status = "okay";
>>> +       mtd-mac-address = <&factory 0x4>;
>>> +       pinctrl-names = "default";
>>> +       pinctrl-0 = <&rgmii1_pins &mdio_pins>;
>> Now use it here
>> 	pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
OK.
>>> +       mediatek,portmap = "l";
>>> +    mediatek,mdio-mode = <1>;
>>> +   
>>> +       port at 5 {
>>> +               status = "okay";
>>> +               mediatek,fixed-link = <1000 1 1 1>;
>>> +               phy-mode = "rgmii";
>> And why not use something like
>> 	phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
>> here and make sure it's taken care of, because this is imho where it
>> would belong.
>>
OK, but how do I take care of the phy-reset. Is it OK how it is done
directly in the gsw_mt7620.c driver code? Or is there a framework for
this, already? And if there is such a framework, then how do I make sure
the reset is made at the right point in time during the switch's
initialization?

>>
>>> diff --git
>>> a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
>>> b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
>>> index 5fc5080aaf..305ce18037 100644
>>> ---
>>> a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
>>> +++
>>> b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
>>> @@ -84,6 +84,32 @@ static int mt7620_mdio_mode(struct device_node *eth_node)
>>>         return ret;
>>>  }
>>>  
>>> +void reset_realtek_phy(void){
>>> +#define RALINK_GPIO_DIR        0xB0000600+0x4C
>>> +#define RALINK_GPIO_DATA       0xB0000600+0x48
>>> +#define RALINK_RESETPHY_GPIO       (39-24)
>>> +    u32 gpiodir;
>>> +    u32 piodata;
>>> +    u32 reset_pin= RALINK_RESETPHY_GPIO;
>>> +   
>>> +    pr_info("gsw: Resetting RTL8211e using gpio 39\n");
>>> +    gpiodir =  le32_to_cpu(*(volatile u32 *)(RALINK_GPIO_DIR));
>>> +    /*set gpio1 to output*/
>>> +    gpiodir |= (1<<reset_pin);
>>> +    *(volatile u32 *)(RALINK_GPIO_DIR) = cpu_to_le32(gpiodir);
>>> +
>>> +    piodata = le32_to_cpu(*(volatile u32 *)(RALINK_GPIO_DATA));
>>> +    /*set to low(0)*/
>>> +    piodata &= ~(1L << reset_pin);
>>> +    *(volatile u32 *)(RALINK_GPIO_DATA) = cpu_to_le32(piodata);
>>> +    /*delay 30ms*/
>>> +    mdelay(30);
>>> +    /*set to high(1)*/
>>> +    piodata |= (1L << reset_pin);
>>> +    *(volatile u32 *)(RALINK_GPIO_DATA) = cpu_to_le32(piodata);
>>> +}
>>> +
>>> +
>>>  static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
>>>  {
>>>         u32 i;
>>> @@ -220,6 +246,7 @@ int mtk_gsw_init(struct fe_priv *priv)
>>>         struct device_node *np = priv->switch_np;
>>>         struct platform_device *pdev = of_find_device_by_node(np);
>>>         struct mt7620_gsw *gsw;
>>> +    const char *rtl8211e_reset = NULL;
>>>  
>>>         if (!pdev)
>>>                 return -ENODEV;
>>> @@ -231,6 +258,9 @@ int mtk_gsw_init(struct fe_priv *priv)
>>>         priv->soc->swpriv = gsw;
>>>  
>>>         mt7620_hw_init(gsw, mt7620_mdio_mode(priv->dev->of_node));
>>> +    of_property_read_string(np, "mediatek,rtl8211e-reset",
>>> &rtl8211e_reset);
>>> +    if (rtl8211e_reset && !strcmp(rtl8211e_reset, "yes"))
>>> +        reset_realtek_phy();
>>>  
>>>         if (gsw->irq) {
>>>                 request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
>>>
>>> _______________________________________________
>>> openwrt-devel mailing list
>>> openwrt-devel at lists.openwrt.org
>>> https://lists.openwrt.org/mailman/listinfo/openwrt-devel
>>>

Birger


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