[OpenWrt-Devel] [PATCH RFC 0/5] ath79: add micro non-physical true RNG based on timing jitter

Stephan Mueller smueller at chronox.de
Mon May 27 09:02:22 EDT 2019


Am Montag, 27. Mai 2019, 15:00:23 CEST schrieb Petr Štetiar:

Hi Petr,

> Etienne Champetier <champetier.etienne at gmail.com> [2019-05-25 12:43:25]:
> > Just to be clear i'm 100% in favor of your effort to have random pool init
> > done fast on all devices, and your solution, based on Stephan awsome work,
> > seems really good I just want to be sure we don't make some devices worse
> > /
> > are not missing something
> 
> FYI, I've just added more devices to the testing before submitting the next
> round of patches, and got following on the MT7620A based device:
> 
>  root at OpenWrt:/# cat /proc/cpuinfo
>  system type             : MediaTek MT7620A ver:2 eco:6
>  machine                 : BDCOM WAP2100-SK
>  processor               : 0
>  cpu model               : MIPS 24KEc V5.0
> 
>  root at OpenWrt:/# cat
> /sys/devices/system/clocksource/clocksource0/available_clocksource systick
> MIPS
> 
>  root at OpenWrt:/# /sbin/urngd
>  jent-rng init failed, err: 2
> 
> Where that error 2 is ECOARSETIME. It makes me wonder if there's something
> which could be tweaked on kernel side in order to provide better environment
> for jent-rng on this quite still popular SoC.

The Jitter RNG is dependent on the existence of a high-resolution timer. The 
mentioned system does not seem to have one.

Check /sys/devices/system/clocksource/clocksource0/current_clocksource and /
sys/devices/system/clocksource/clocksource0/available_clocksource


Ciao
Stephan



_______________________________________________
openwrt-devel mailing list
openwrt-devel at lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel


More information about the openwrt-devel mailing list