[OpenWrt-Devel] Understanding Ethernet Architecture (I/O --> MDIO --> MII vs I/O --> MAC) for mt7620 (OpenWRT)

Mathew McBride matt at traverse.com.au
Sat Jun 15 02:10:08 EDT 2019

Hi Daniel,
MDIO is a low-speed management bus to talk between the CPU and the Ethernet PHY's, it's best thought of as "I2C for Ethernet PHYs" (the concepts between the two are similar). 
Like I2C there can be multiple devices on the MDIO bus so each PHY needs an address, and in cases where multiple MACs and MDIO controllers exist on a system you don't necessarily have to use one MDIO controller for a particular MAC.

This is only for reporting things like the current link speed and setting some PHY registers (like what LEDs to drive and if you want to force 10/100/1000 instead of autoneg) - if you have a connection whose electrical characteristics never change (e.g between a SoC<->Switch/xDSL/WiFi/Cable PHY on the same board) then there might be _no_ MDIO communication between them.
(In these cases one might have to force certain link parameters in the MAC registers, the 'fixed-link' driver in the kernel can be used to do this)

The actual Ethernet traffic is passed over the R(G)MII/SGMII/etc. which is point to point (not a "bus") between the MAC and the link-partner.
Note that if you have a Ethernet switch (either as a separate chip or buit-in to the SoC), your "link-partner" is the switch fabric, not any ports downstream.
So if you manipulate the MAC registers for the SoC<->Switch you are only manipulating the connection between the two.

I can't comment on the MT7620 specifically, but its quite likely there is no MDIO between the CPU MAC and the switch, and that the switch is configured "out-of-band" by another method - and this would include any ethernet PHYs that are part of the switch.

Hope this helps,

-----Original Message-----
From: openwrt-devel <openwrt-devel-bounces at lists.openwrt.org> On Behalf Of Daniel Santos
Sent: Saturday, 15 June 2019 8:53 AM
To: Daniel Golle <daniel at makrotopia.org>; Felix Fietkau <nbd at nbd.name>; openwrt-devel <openwrt-devel at lists.openwrt.org>; John Crispin <blogic at openwrt.org>; Michael Lee <igvtee at gmail.com>; netdev at vger.kernel.org
Subject: [OpenWrt-Devel] Understanding Ethernet Architecture (I/O --> MDIO --> MII vs I/O --> MAC) for mt7620 (OpenWRT)


I'm still fairly new to Ethernet drivers and there are a lot of interesting pieces.  What I need help with is understanding MDIO --> (R)MII vs direct I/O to the MAC (e.g., via ioread32, iowrite32).  Why is there not always a struct mii_bus to talk to this hardware?  Is it because the PHY and/or MAC hardware sometimes attached via an MDIO device and sometimes directly to the I/O bus?  Or does some type of "indirect access" need to be enabled for that to work?

I might be trying to do something that's unnecessary however, I'm not sure yet.  I need to add functionality to change a port's auto-negotiate, duplex, etc.  I'm adding it to the swconfig first and then will look at adding it for DSA afterwards.  When I run "swconfig dev switch0 port 0 show", the current mt7530 / mt7620 driver is querying the MAC status register (at base + 0x3008 + 0x100 * port, described on pages 323-324 of the MT7620 Programming Guide), so I implemented the "set" functionality by modifying the MAC's control register (offset
0x3000 on page 321), but it doesn't seem to change anything.  So I figured maybe I need to modify the MII interface's control register for the port (page 350), but upon debugging I can see that the struct mii_bus *bus member is NULL.

So should I be able to change it via the MAC's control register and something else is wrong?  Why is there no struct mii_bus?  Can I talk to the MII hardware in some other way?



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