[PATCH] mt7621: test mtk_hw_init() hunk

[=3D?UTF-8?q?Bj=3DC3=3DB8rn=3D20Mork?=3D]

Signed-off-by: Bj=C3=B8rn Mork <bjorn at mork.no>
---
 .../202-Adding-MT7621-DSA-support.patch            | 36 ------------------=
----
 target/linux/ramips/patches-4.14/205-mtk-eth.patch | 34 ------------------=
--
 2 files changed, 70 deletions(-)

diff --git a/target/linux/ramips/patches-4.14/202-Adding-MT7621-DSA-support=
.patch b/target/linux/ramips/patches-4.14/202-Adding-MT7621-DSA-support.pat=
ch
index f1cfa07e7415..b01c03610970 100644
--- a/target/linux/ramips/patches-4.14/202-Adding-MT7621-DSA-support.patch
+++ b/target/linux/ramips/patches-4.14/202-Adding-MT7621-DSA-support.patch
@@ -198,42 +198,6 @@ Index: linux-4.14.61/drivers/net/ethernet/mediatek/mtk=
_eth_soc.c
  	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
  	mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
  }
-@@ -1953,6 +1989,27 @@ static int mtk_hw_init(struct mtk_eth *e
- 	}
- 	regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
-=20
-+#ifdef CONFIG_SOC_MT7621
-+
-+#define SYSC_PAD_RGMII2_MDIO	0x58
-+#define SYSC_GPIO_MODE	0x60
-+#define SYSC_REG_CFG1	0x14
-+	printk("MT7621: GE2: Pininit\n");
-+
-+	/* reduce RGMII1 PAD driving strength */
-+	regmap_read(eth->ethsys, SYSC_PAD_RGMII2_MDIO, &val);
-+	// MDIO
-+	val &=3D ~(3 << 4);
-+	// RGMII2, 12mA
-+	val &=3D ~(3 <<20);=20
-+	val |=3D (2 << 20);=20
-+	regmap_write(eth->ethsys, SYSC_PAD_RGMII2_MDIO, val);
-+
-+	/* gpio mux - RGMII1&RGMII2=3DNormal mode, set GMAC1,2 RGMII mode  */
-+	regmap_read(eth->ethsys, SYSC_GPIO_MODE, &val);
-+	val &=3D ~(BIT(14) | BIT(15) | 3 << 12 | 3 << 14);
-+	regmap_write(eth->ethsys, SYSC_GPIO_MODE, val);
-+#else
- 	if (eth->pctl) {
- 		/* Set GE2 driving and slew rate */
- 		regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
-@@ -1963,6 +2020,7 @@ static int mtk_hw_init(struct mtk_eth *e
- 		/* set GE2 TUNE */
- 		regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
- 	}
-+#endif
-=20
- 	/* Set linkdown as the default for each GMAC. Its own MCR would be set
- 	 * up with the more appropriate value when mtk_phy_link_adjust call is
 @@ -2548,13 +2606,15 @@ static int mtk_probe(struct platform_dev
  		}
  	}
diff --git a/target/linux/ramips/patches-4.14/205-mtk-eth.patch b/target/li=
nux/ramips/patches-4.14/205-mtk-eth.patch
index 19072a5d8b28..dccc23c4e7be 100644
--- a/target/linux/ramips/patches-4.14/205-mtk-eth.patch
+++ b/target/linux/ramips/patches-4.14/205-mtk-eth.patch
@@ -37,40 +37,6 @@ Index: linux-4.14.61/drivers/net/ethernet/mediatek/mtk_e=
th_soc.c
  		val &=3D ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
  		val |=3D SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
  	}
-@@ -1998,17 +2002,26 @@ static int mtk_hw_init(struct mtk_eth *e
-=20
- 	/* reduce RGMII1 PAD driving strength */
- 	regmap_read(eth->ethsys, SYSC_PAD_RGMII2_MDIO, &val);
--	// MDIO
-+	// MDIO driving 2mA
- 	val &=3D ~(3 << 4);
--	// RGMII2, 12mA
--	val &=3D ~(3 <<20);=20
--	val |=3D (2 << 20);=20
--	regmap_write(eth->ethsys, SYSC_PAD_RGMII2_MDIO, val);
-=20
--	/* gpio mux - RGMII1&RGMII2=3DNormal mode, set GMAC1,2 RGMII mode  */
-+	if (eth->mac[1]) {
-+		// When 2nd MAC is enabled set pin strength.
-+		// RGMII2, 12mA
-+		val &=3D ~(3 <<20);
-+		val |=3D (2 << 20);
-+		regmap_write(eth->ethsys, SYSC_PAD_RGMII2_MDIO, val);
-+	};
-+
-+	/* set GMAC1,2 RGMII mode  */
- 	regmap_read(eth->ethsys, SYSC_GPIO_MODE, &val);
--	val &=3D ~(BIT(14) | BIT(15) | 3 << 12 | 3 << 14);
-+	val &=3D ~(3<<12); // MDIO_MODE =3D MDIO
-+		val &=3D ~(BIT(15) | BIT(14)); // RGMIIx GPIO MODE =3D RGMIIx
-+	if (!eth->mac[1])
-+		val |=3D BIT(15);
- 	regmap_write(eth->ethsys, SYSC_GPIO_MODE, val);
-+
-+
- #else
- 	if (eth->pctl) {
- 		/* Set GE2 driving and slew rate */
 @@ -2055,7 +2068,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
--=20
2.11.0


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