[OpenWrt-Devel] OpenWrt on RISC-V

Zoltan HERPAI wigyori at uid0.hu
Fri Nov 2 22:50:31 EDT 2018

Hi all,

I'm happy to announce a port of RISC-V for OpenWrt. For those who 
haven't heard about it, RISC-V is a new CPU architecture coming from 
Berkeley, and is a free, open, extensible ISA, maintained by a 
non-profit foundation, included in the Linux kernel since 4.15.

Current status is:
- based on 4.19 - pull requests and patches for trunk will be sent once 
support for 4.19 is merged into mainline and core package changes are 
worked out. Until then, the port is in a staging tree [1]
- mainline musl support is expected for musl 1.21, patches are included 
in the tree [2] for the current 1.20 for testing
- currently builds with glibc as default
- OpenWrt packages are built regularly on an external buildbot
- documentation is added to the wiki [3]

Currently you have three ways to run RISC-V:
- Virtex7-based FPGA implementation of the core (most expensive)
- HiFive Unleashed (official Linux devboard, less expensive) [4]
- QEMU (free, support for riscv merged into qemu-2.12) [5]

The target supports the last two. There are further development boards 
expected in the next few months. For further reading on the architecture 
and its state, please refer to this site [6].

The staging tree includes various fixes for the core package changes 
appeared with 4.19. Given the state of 4.19 currently, please consider 
this an experimental port - you won't be able to run quake on it yet, 
sorry. [7]

[3] https://openwrt.org/docs/techref/hardware/soc/soc.sifive
[4] https://openwrt.org/toh/hifive/unleashed
[6] https://riscv.org/
[7] https://archive.fosdem.org/2018/schedule/event/riscv/

Zoltan Herpai

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