[OpenWrt-Devel] [1/4, RFCv2] net: phy: realtek: Support RTL8366RB variant

Linus Walleij linus.walleij at linaro.org
Tue May 29 16:01:14 EDT 2018

On Tue, May 29, 2018 at 8:51 PM, Heiner Kallweit <hkallweit1 at gmail.com> wrote:

>> +#define RTL8366RB_POWER_SAVE 0x21

> Typically PHY register addresses are 5 bits wide, is 0x21 correct
> and I miss something?

If it is correct I don't know, but it appears in the vendor

/*Power Saving*/
#define RTL8368S_POWER_SAVING_PAGE                              0
#define RTL8368S_POWER_SAVING_REG                                       21
#define RTL8368S_POWER_SAVING_BIT_MSK                   0x1000


        phySmiAddr = 0x8000 | (1<<(phyNo +RTL8368S_PHY_NO_OFFSET)) |


        retVal = rtl8368s_setAsicReg(phySmiAddr, 0);
        if (retVal !=  SUCCESS)
                return retVal;

The PHYs are accessed here in memory area 0x8000.

Fixed the rest, thanks!

Linus Walleij

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