[OpenWrt-Devel] [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver
linus.walleij at linaro.org
Tue May 29 14:41:49 EDT 2018
On Tue, May 29, 2018 at 2:24 PM, Andrew Lunn <andrew at lunn.ch> wrote:
> Did you look at the switch end? I found a datasheet for the
> 8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII
Unfortunately this datasheet is not applicable to RTL8366RB.
RTL documentation and model numbers are a complete mess
around the time when this chip came out, unfortunately... I even
started to implement using that datasheet and had to toss a bunch
of stuff away.
There might not even be a proper datasheet for RTL8366RB,
I'm afraid. The best we have is different (3 different AFAICT)
vendor code drops. Here is one drop over at DD-WRT:
As you can see, the RTL8366RB vendor driver consists of
a hacked version of their RTL8368S driver, so apparently those
two ASICs are similar, they even kept the same filenames.
For example the register defintions:
> With RGMII delays, you have 3 'choices'.
> 1) The hardware design includes the delay, by zig-zagging the clock
> line to make it longer.
> 2) The 'MAC' side does the delay.
> 3) The 'PHY' side does the delay.
> I normally recommend the PHY side doing it, because that's what most
> board do. Gives us some consistency. But it does not really
> matter. Just make sure one side, and only once side is inserting the
Makes sense! But I haven't found anything applicable in the
There are some jam tables with magic values written all over
the place that have no documentation, I fear this is one of the
settings poked around with there.
However, even if this router did not come with any code for
the RTL8366RB driver, I disassembled the binary to verify
that they use the same magic jam table, so the ASIC is
initialized in the same way.
openwrt-devel mailing list
openwrt-devel at lists.openwrt.org
More information about the openwrt-devel