[OpenWrt-Devel] [PATCH 1/4 v5] PCI: add DT bindings for Faraday Technology PCI Host Bridge

Linus Walleij linus.walleij at linaro.org
Fri Mar 24 05:54:14 EDT 2017

On Sun, Mar 12, 2017 at 11:23 PM, Linus Walleij
<linus.walleij at linaro.org> wrote:

> This adds device tree bindings for the Faraday technology PCI
> Host Bridge. This IP is found in the Storlink/Storm/Cortina
> Gemini SoC platform.
> Cc: Janos Laube <janos.dev at gmail.com>
> Cc: Paulius Zaleckas <paulius.zaleckas at gmail.com>
> Cc: Hans Ulli Kroll <ulli.kroll at googlemail.com>
> Cc: Florian Fainelli <f.fainelli at gmail.com>
> Cc: devicetree at vger.kernel.org
> Cc: Feng-Hsin Chiang <john453 at faraday-tech.com>
> Cc: Greentime Hu <green.hu at gmail.com>
> Acked-by: Rob Herring <robh at kernel.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> ChangeLog v4->v5:
> - No changes, just resend as everything else is rebased onto
>   v4.11-rc1.

Bjorn do you have any further comments or can we queue patch
1+2 of this series?

I want to submit the DTS patches to the ARM SoC tree, so I need
to be sure the bindings+driver are merge material first.

Linus Walleij
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