[OpenWrt-Devel] [PATCH 2/2] ls1043ardb-64b: add 4.1 kernel patches

yutang.jiang at nxp.com yutang.jiang at nxp.com
Wed Jul 13 13:56:10 EDT 2016


From: Yutang Jiang <yutang.jiang at nxp.com>

Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
---
 ...ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch |  558 +
 ...LS2080A-compilation-under-ARCH_LAYERSCAPE.patch |   31 +
 ...-dts-ls1043a-add-LS1043ARDB-board-support.patch |  156 +
 ...e-ARCH_LAYERSCAPE-for-Layerscape-SoC-fami.patch |   49 +
 ...-Move-chip-specific-knowledge-into-driver.patch | 1579 +
 .../0006-clk-qoriq-Add-ls2080a-support.patch       |  181 +
 .../0007-clk-qoriq-Add-ls1043a-support.patch       |   80 +
 .../0008-clk-qoriq-fix-memory-leak.patch           |   36 +
 ...ls1043a-add-fman-bman-qman-ethernet-nodes.patch |  754 +
 .../0010-dts-ls1043ardb-add-mdio-phy-nodes.patch   |   86 +
 ...d-ARM-specific-fucntions-required-for-ehc.patch |   86 +
 ...fsl-add-a-sanity-check-for-complete-handl.patch |   36 +
 ...-remove-dependency-FSL_SOC-for-ehci-fsl-d.patch |   30 +
 ...043a-Add-configure-gfladj-property-to-USB.patch |   38 +
 ...c-fsl-Move-fsl_guts.h-out-of-arch-powerpc.patch |  637 +
 ...river-memory-Removal-of-deprecated-NO_IRQ.patch |   29 +
 ...fsl-remove-dependency-FSL_SOC-for-Gianfar.patch |   36 +
 .../0018-temp-QE-headers-are-needed-by-FMD.patch   | 1326 +
 .../patches-4.1/0019-fmd-add-SDK1.9-codebase.patch |115016 ++++++++++++++++++++
 .../0020-devres-add-devm_alloc_percpu.patch        |  147 +
 .../patches-4.1/0021-net-readd-skb_recycle.patch   |   66 +
 .../0022-net-add-custom-NETIF-flags.patch          |   41 +
 ...e-netdev-watchdog-aware-of-hardware-multi.patch |   53 +
 .../patches-4.1/0024-dpa-add-SDK1.9-codebase.patch |17026 +++
 ...s-devicetree-doc-out-of-powerpc-directory.patch |  107 +
 ...c-fsl-move-mpc85xx.h-to-include-linux-fsl.patch |  300 +
 .../0027-fman-update-an-outdated-header.patch      |   56 +
 ..._eth-add-promisc-handler-for-proxy-driver.patch |   37 +
 ..._eth-remove-VERSION-and-dpa_get_ringparam.patch |  241 +
 ...030-dpaa_eth-add-EEE-callbacks-in-ethtool.patch |   71 +
 ...ve-exported-counters-from-debugfs-into-et.patch |  619 +
 .../0032-dpaa_eth-set-MAC-handle-for-MEMAC.patch   |   28 +
 .../0033-dpaa_eth-rename-ethtool-statistic.patch   |   26 +
 ...move-PPC-dependencies-from-the-macsec-deb.patch |   54 +
 ...map-the-S-G-table-prior-to-iterate-throug.patch |  112 +
 ...6-dpaa_eth-memset-the-S-G-entry-structure.patch |   30 +
 .../0037-dpaa_eth-add-S-G-for-onic.patch           |  495 +
 .../0038-dpaa_eth-remove-copyright-statement.patch |   28 +
 .../0039-dpaa_eth-remove-TODO-list.patch           |   39 +
 ...h-create-macro-def-for-numerical-constant.patch |   38 +
 ...eth-use-IFF_UP-to-check-the-Eth-interface.patch |   68 +
 ..._eth-rename-variables-and-remove-comments.patch |   75 +
 ...043-dpaa_eth-remove-dead-unnecessary-code.patch |  123 +
 ...paa_eth-use-common-preprocessor-procedure.patch |   30 +
 ...45-dpaa_eth-fix-unload-procedure-for-onic.patch |  110 +
 ...eth-fix-call-to-of_node_put-in-dts-parser.patch |   45 +
 ...eth-generic-fix-an-uninitialized-variable.patch |   25 +
 ...ove-debugfs-into-ethtool-stats-for-macsec.patch |  757 +
 ...-Move-debugfs-into-ethtool-stats-for-oNIC.patch |  667 +
 ...d-counter-for-Scatter-Gather-frames-on-RX.patch |  104 +
 ...APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch |   62 +
 .../0052-Port-QBMan-Code-from-SDK-1.9.patch        |23605 ++++
 ...d-invalidation-in-case-PAMU-is-not-enable.patch |   55 +
 .../0054-fsl_qbman-Use-do_div-when-dividing.patch  |   30 +
 .../0055-arm64-Add-pdev_archdata-for-dmamask.patch |   58 +
 ...pdate-QBMan-drivers-to-support-little-end.patch | 2549 +
 ...an-Enable-DPAA1-QBMan-for-ARM64-platforms.patch |   36 +
 .../0058-dpaa_eth-fix-the-bitfields-of-a-FD.patch  |   67 +
 .../0059-dpaa_eth-fix-S-G-for-ARM.patch            |   56 +
 ...an-Convenient-accessors-for-S-G-structure.patch |  168 +
 ...-fix-CGR-congestion-indication-processing.patch |   40 +
 .../0062-qbman-fix-qm_sg_entry-structure.patch     |   77 +
 ...fix-CGR-average-instantaneous-byte-counts.patch |   85 +
 ...064-fsl_qbman-Fix-Frame-Queue-Stash-setup.patch |   38 +
 .../0065-bman-fix-stockpile-logic.patch            |  196 +
 .../patches-4.1/0066-fmd-add-LS1043-support.patch  | 3599 +
 ...se-S-G-accessors-in-the-Shared-Mac-driver.patch |   78 +
 .../0068-dpaa_eth-fix-S-G-for-ARM.patch            |  212 +
 ...mset-bm_buffer-and-qm_sg_entry-structures.patch |   26 +
 ...eth-Fix-dma_map-unmap-for-the-Tx-S-G-path.patch |   87 +
 ...e-raw_smp_processor_id-to-get-queue-mappi.patch |   32 +
 .../0072-dpaa_eth-added-qsgmii-support.patch       |   56 +
 ...e-accessors-to-update-and-query-the-qm_sg.patch |  227 +
 ...-dpaa_eth-support-PTPd-1588-stack-for-ARM.patch |   48 +
 ...ad-ts-value-according-to-its-endianness-t.patch |   28 +
 ...76-dpaa_eth-fix-fq-dts-parser-for-macless.patch |   39 +
 ...7-dpaa_eth-fix-modification-of-const-data.patch |  226 +
 ...a_eth-add-primitives-for-buffer-alignment.patch |   32 +
 ...-dpaa_eth-remove-jumbo-frame-optimization.patch |   37 +
 ...aa_eth-allocate-one-full-page-for-buffers.patch |   33 +
 ...eth-create-particular-define-for-4K-issue.patch |   54 +
 ...-dpaa_eth-fix-S-G-for-TX-on-ARM-platforms.patch |  216 +
 ...h-create-a-S-G-frame-for-4K-contig-frames.patch |   39 +
 ...eth-fix-max-number-of-S-G-entries-for-ARM.patch |   47 +
 ...t-dma-coherent-mask-when-setting-dma-mask.patch |   26 +
 .../0086-dpaa_eth-force-DMA-coherency.patch        |   26 +
 .../0087-dpaa_eth-force-DMA-coherency-ops.patch    |   30 +
 ...88-dpaa_eth-devm_ioremap_prot-was-removed.patch |   59 +
 .../0089-dpaa_eth-include-needed-header.patch      |   25 +
 .../patches-4.1/0090-dpaa_eth-small-fixes.patch    |  129 +
 ...-dpaa_eth-use-proper-identifier-for-ARM64.patch |   27 +
 ...-dpaa_eth-enable-on-both-ARM64-or-FSL_SOC.patch |   25 +
 .../0093-dpaa_eth-remove-ASF-related-code.patch    |   29 +
 ...md-fix-issue-with-HM-in-CC-in-compat-mode.patch |   33 +
 ...a_eth-do-not-print-debug-message-as-error.patch |   26 +
 .../0096-fmd-adapt-to-the-new-clocking-model.patch |   65 +
 ...arm64-dts-align-to-the-new-clocking-model.patch |   30 +
 ...iq-optimize-the-CPU-frequency-switching-t.patch |  130 +
 ...iq-Don-t-look-at-clock-implementation-det.patch |  279 +
 ...-net-phy-Add-support-for-Realtek-RTL8211F.patch |  126 +
 ...0101-net-phy-add-RealTek-RTL8211DN-phy-id.patch |   48 +
 ...e-get_phy_c45_ids-to-support-more-c45-phy.patch |   60 +
 ...0103-net-phy-fix-a-bug-in-get_phy_c45_ids.patch |  126 +
 ...4-net-mdio-fix-mdio_bus_match-for-c45-PHY.patch |   54 +
 .../0105-net-phy-add-driver-for-aquantia-phy.patch |  210 +
 ...-net-fsl-Enable-XGMAC_MDIO-on-LS2085A-SoC.patch |   42 +
 ...change-ls2-arch-define-to-ARCH_LAYERSCAPE.patch |   29 +
 ...-phy-fix-PHY_RUNNING-in-phy_state_machine.patch |   56 +
 ...hy-add-interrupt-support-for-aquantia-phy.patch |  113 +
 ...oremap-for-normal-cacheable-non-shareable.patch |   46 +
 ...upport-to-remap-kernel-cacheable-memory-t.patch |   33 +
 ...le-add-support-to-map-cacheable-and-non-s.patch |   27 +
 ...fmd-remove-misuse-of-IRQF_NO_SUSPEND-flag.patch |   77 +
 .../0114-ls2085a-Add-support-for-reset.patch       |  145 +
 .../0115-dts-ls1043a-add-reset-node.patch          |   33 +
 .../0116-ls1043a-Add-support-for-reset.patch       |   61 +
 ...r-Kconfig-Change-define-to-ARCH_LAYERSCAP.patch |   27 +
 ...nware-Add-base-driver-for-Designware-PCIe.patch |  407 +
 ...are-find-msi-controller-via-msi-parent-ha.patch |   79 +
 ...0-pci-layerscape-Add-LS2085A-PCIe-support.patch |  326 +
 ...ape-PCIe-controller-stream-ID-partitionin.patch |  155 +
 ...yerscape-Add-compatible-string-for-LS2080.patch |   25 +
 ...ape-Add-compatible-in-probe-function-for-.patch |   28 +
 ...i-layerscape-Add-PCIe-RC-EP-mode-checking.patch |   48 +
 ...0125-PCI-layerscape-backport-from-4.4-rc1.patch |  387 +
 ...ape-PCIe-controller-stream-ID-partitionin.patch |  127 +
 ...7-pci-layerscape-fix-MSG-TLP-drop-setting.patch |   71 +
 .../0128-pci-msi-fix-compile-issue-on-arm32.patch  |   40 +
 ...designware-add-modifications-from-4.4-rc1.patch |  836 +
 ...-designware-remove-designware-MSI-support.patch |  331 +
 ...ignware-Add-support-non-dw-MSI-controller.patch |   89 +
 .../patches-4.1/0132-arm-Add-MSI-support.patch     |  369 +
 ...m64-layerscape-Enable-PCIe-for-Layerscape.patch |   25 +
 .../0134-ls1043a-msi-add-ls1043a-MSI-support.patch |  174 +
 .../patches-4.1/0135-arm64-add-NO_IRQ-macro.patch  |   32 +
 ...o-Port-gpio-driver-to-support-layerscape-.patch |  296 +
 .../0137-layerscape-dts-Update-GPIO-node.patch     |   72 +
 ...fc-Change-IO-accessor-based-on-endianness.patch |  686 +
 ...ers-memory-Add-deep-sleep-support-for-IFC.patch |  240 +
 ...ry-Update-dependency-of-IFC-for-Layerscap.patch |   61 +
 ...c-Segregate-IFC-fcm-and-runtime-registers.patch |  713 +
 ...-drivers-memory-Fix-build-error-for-arm64.patch |   58 +
 ...-compilation-error-when-COMPAT-not-enable.patch |   34 +
 ...sdhc-add-default-quirk-SDHCI_QUIRK_NO_HIS.patch |   32 +
 ...dd-fixup-of-broken-CMD23-for-Sandisk-card.patch |   42 +
 ...DT-binding-for-little-endian-eSDHC-host-c.patch |   28 +
 ...f-esdhc-support-both-BE-and-LE-host-contr.patch |  643 +
 ...fig-reconfigure-MMC_SDHCI_OF_ESDHC-option.patch |   42 +
 ...f-esdhc-avoid-writing-power-control-regis.patch |   36 +
 ...f-esdhc-add-remove-some-quirks-according-.patch |   65 +
 150 files changed, 183449 insertions(+)
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0002-arm64-Move-LS2080A-compilation-under-ARCH_LAYERSCAPE.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0003-dts-ls1043a-add-LS1043ARDB-board-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0004-arm64-Define-ARCH_LAYERSCAPE-for-Layerscape-SoC-fami.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0005-clk-qoriq-Move-chip-specific-knowledge-into-driver.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0006-clk-qoriq-Add-ls2080a-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0007-clk-qoriq-Add-ls1043a-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0008-clk-qoriq-fix-memory-leak.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0009-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0010-dts-ls1043ardb-add-mdio-phy-nodes.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0011-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0012-USB-Gadget-fsl-add-a-sanity-check-for-complete-handl.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0013-usb-kconfig-remove-dependency-FSL_SOC-for-ehci-fsl-d.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0014-arm-dts-ls1043a-Add-configure-gfladj-property-to-USB.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0015-powerpc-fsl-Move-fsl_guts.h-out-of-arch-powerpc.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0016-driver-memory-Removal-of-deprecated-NO_IRQ.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0017-net-fsl-remove-dependency-FSL_SOC-for-Gianfar.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0018-temp-QE-headers-are-needed-by-FMD.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0019-fmd-add-SDK1.9-codebase.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0020-devres-add-devm_alloc_percpu.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0021-net-readd-skb_recycle.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0022-net-add-custom-NETIF-flags.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0023-net-Make-the-netdev-watchdog-aware-of-hardware-multi.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0024-dpa-add-SDK1.9-codebase.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0025-dt-move-guts-devicetree-doc-out-of-powerpc-directory.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0026-powerpc-fsl-move-mpc85xx.h-to-include-linux-fsl.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0027-fman-update-an-outdated-header.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0028-dpaa_eth-add-promisc-handler-for-proxy-driver.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0029-dpaa_eth-remove-VERSION-and-dpa_get_ringparam.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0030-dpaa_eth-add-EEE-callbacks-in-ethtool.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0031-dpaa_eth-Move-exported-counters-from-debugfs-into-et.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0032-dpaa_eth-set-MAC-handle-for-MEMAC.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0033-dpaa_eth-rename-ethtool-statistic.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0034-dpaa_eth-Remove-PPC-dependencies-from-the-macsec-deb.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0035-dpaa_eth-Unmap-the-S-G-table-prior-to-iterate-throug.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0036-dpaa_eth-memset-the-S-G-entry-structure.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0037-dpaa_eth-add-S-G-for-onic.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0038-dpaa_eth-remove-copyright-statement.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0039-dpaa_eth-remove-TODO-list.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0040-dpaa_eth-create-macro-def-for-numerical-constant.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0041-dpaa_eth-use-IFF_UP-to-check-the-Eth-interface.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0042-dpaa_eth-rename-variables-and-remove-comments.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0043-dpaa_eth-remove-dead-unnecessary-code.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0044-dpaa_eth-use-common-preprocessor-procedure.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0045-dpaa_eth-fix-unload-procedure-for-onic.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0046-dpaa_eth-fix-call-to-of_node_put-in-dts-parser.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0047-dpaa_eth-generic-fix-an-uninitialized-variable.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0048-dpaa_eth-Move-debugfs-into-ethtool-stats-for-macsec.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0049-dpaa_eth-Move-debugfs-into-ethtool-stats-for-oNIC.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0050-dpaa_eth-Add-counter-for-Scatter-Gather-frames-on-RX.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0051-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0052-Port-QBMan-Code-from-SDK-1.9.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0053-fsl_qman-Add-invalidation-in-case-PAMU-is-not-enable.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0054-fsl_qbman-Use-do_div-when-dividing.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0055-arm64-Add-pdev_archdata-for-dmamask.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0056-fsl_qbman-Update-QBMan-drivers-to-support-little-end.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0057-fsl_qbman-Enable-DPAA1-QBMan-for-ARM64-platforms.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0058-dpaa_eth-fix-the-bitfields-of-a-FD.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0059-dpaa_eth-fix-S-G-for-ARM.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0060-fsl_qbman-Convenient-accessors-for-S-G-structure.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0061-fsl_qman-fix-CGR-congestion-indication-processing.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0062-qbman-fix-qm_sg_entry-structure.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0063-fsl_qbman-fix-CGR-average-instantaneous-byte-counts.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0064-fsl_qbman-Fix-Frame-Queue-Stash-setup.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0065-bman-fix-stockpile-logic.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0066-fmd-add-LS1043-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0067-dpaa_eth-Use-S-G-accessors-in-the-Shared-Mac-driver.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0068-dpaa_eth-fix-S-G-for-ARM.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0069-dpaa_eth-memset-bm_buffer-and-qm_sg_entry-structures.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0070-dpaa_eth-Fix-dma_map-unmap-for-the-Tx-S-G-path.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0071-dpaa_eth-Use-raw_smp_processor_id-to-get-queue-mappi.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0072-dpaa_eth-added-qsgmii-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0073-dpaa_eth-Use-accessors-to-update-and-query-the-qm_sg.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0074-dpaa_eth-support-PTPd-1588-stack-for-ARM.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0075-dpaa_eth-read-ts-value-according-to-its-endianness-t.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0076-dpaa_eth-fix-fq-dts-parser-for-macless.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0077-dpaa_eth-fix-modification-of-const-data.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0078-dpaa_eth-add-primitives-for-buffer-alignment.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0079-dpaa_eth-remove-jumbo-frame-optimization.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0080-dpaa_eth-allocate-one-full-page-for-buffers.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0081-dpaa_eth-create-particular-define-for-4K-issue.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0082-dpaa_eth-fix-S-G-for-TX-on-ARM-platforms.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0083-dpaa_eth-create-a-S-G-frame-for-4K-contig-frames.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0084-dpaa_eth-fix-max-number-of-S-G-entries-for-ARM.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0085-dpaa_eth-set-dma-coherent-mask-when-setting-dma-mask.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0086-dpaa_eth-force-DMA-coherency.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0087-dpaa_eth-force-DMA-coherency-ops.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0088-dpaa_eth-devm_ioremap_prot-was-removed.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0089-dpaa_eth-include-needed-header.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0090-dpaa_eth-small-fixes.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0091-dpaa_eth-use-proper-identifier-for-ARM64.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0092-dpaa_eth-enable-on-both-ARM64-or-FSL_SOC.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0093-dpaa_eth-remove-ASF-related-code.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0094-fmd-fix-issue-with-HM-in-CC-in-compat-mode.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0095-dpaa_eth-do-not-print-debug-message-as-error.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0096-fmd-adapt-to-the-new-clocking-model.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0097-arm64-dts-align-to-the-new-clocking-model.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0098-cpufreq-qoriq-optimize-the-CPU-frequency-switching-t.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0099-cpufreq-qoriq-Don-t-look-at-clock-implementation-det.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0100-net-phy-Add-support-for-Realtek-RTL8211F.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0101-net-phy-add-RealTek-RTL8211DN-phy-id.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0102-net-phy-tune-get_phy_c45_ids-to-support-more-c45-phy.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0103-net-phy-fix-a-bug-in-get_phy_c45_ids.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0104-net-mdio-fix-mdio_bus_match-for-c45-PHY.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0105-net-phy-add-driver-for-aquantia-phy.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0106-net-fsl-Enable-XGMAC_MDIO-on-LS2085A-SoC.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0107-net-fsl-change-ls2-arch-define-to-ARCH_LAYERSCAPE.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0108-net-phy-fix-PHY_RUNNING-in-phy_state_machine.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0109-net-phy-add-interrupt-support-for-aquantia-phy.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0110-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0111-arm64-add-support-to-remap-kernel-cacheable-memory-t.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0112-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0113-fmd-remove-misuse-of-IRQF_NO_SUSPEND-flag.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0114-ls2085a-Add-support-for-reset.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0115-dts-ls1043a-add-reset-node.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0116-ls1043a-Add-support-for-reset.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0117-reset-driver-Kconfig-Change-define-to-ARCH_LAYERSCAP.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0118-pci-designware-Add-base-driver-for-Designware-PCIe.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0119-pci-designware-find-msi-controller-via-msi-parent-ha.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0120-pci-layerscape-Add-LS2085A-PCIe-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0121-pci-layerscape-PCIe-controller-stream-ID-partitionin.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0122-pci-layerscape-Add-compatible-string-for-LS2080.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0123-pci-layerscape-Add-compatible-in-probe-function-for-.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0124-pci-layerscape-Add-PCIe-RC-EP-mode-checking.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0125-PCI-layerscape-backport-from-4.4-rc1.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0126-pci-layerscape-PCIe-controller-stream-ID-partitionin.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0127-pci-layerscape-fix-MSG-TLP-drop-setting.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0128-pci-msi-fix-compile-issue-on-arm32.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0129-PCI-designware-add-modifications-from-4.4-rc1.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0130-PCI-designware-remove-designware-MSI-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0131-pci-designware-Add-support-non-dw-MSI-controller.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0132-arm-Add-MSI-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0133-arm64-layerscape-Enable-PCIe-for-Layerscape.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0134-ls1043a-msi-add-ls1043a-MSI-support.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0135-arm64-add-NO_IRQ-macro.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0136-drivers-gpio-Port-gpio-driver-to-support-layerscape-.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0137-layerscape-dts-Update-GPIO-node.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0138-fsl_ifc-Change-IO-accessor-based-on-endianness.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0139-drivers-memory-Add-deep-sleep-support-for-IFC.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0140-driver-memory-Update-dependency-of-IFC-for-Layerscap.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0141-mtd-ifc-Segregate-IFC-fcm-and-runtime-registers.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0142-drivers-memory-Fix-build-error-for-arm64.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0143-fsl-ifc-fix-compilation-error-when-COMPAT-not-enable.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0144-mmc-sdhci-esdhc-add-default-quirk-SDHCI_QUIRK_NO_HIS.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0145-mmc-block-add-fixup-of-broken-CMD23-for-Sandisk-card.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0146-mmc-dt-add-DT-binding-for-little-endian-eSDHC-host-c.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0147-mmc-sdhci-of-esdhc-support-both-BE-and-LE-host-contr.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0148-mmc-kconfig-reconfigure-MMC_SDHCI_OF_ESDHC-option.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0149-mmc-sdhci-of-esdhc-avoid-writing-power-control-regis.patch
 create mode 100644 target/linux/layerscape-64b/patches-4.1/0150-mmc-sdhci-of-esdhc-add-remove-some-quirks-according-.patch

diff --git a/target/linux/layerscape-64b/patches-4.1/0001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch b/target/linux/layerscape-64b/patches-4.1/0001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch
new file mode 100644
index 0000000..96d8bc2
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch
@@ -0,0 +1,558 @@
+From 99904118b8ad879b3164173a50c74ca8a9efb687 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <Mingkai.Hu at freescale.com>
+Date: Mon, 21 Jul 2014 14:48:42 +0800
+Subject: [PATCH 001/151] arm64/ls1043a: add DTS for Freescale LS1043A SoC
+
+LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
+similar to LS1021a which complies to Chassis 2.1 spec.
+
+Following levels of DTSI/DTS files have been created for the
+LS1043A SoC family:
+
+- fsl-ls1043a.dtsi:
+  DTS-Include file for FSL LS1043A SoC.
+
+Signed-off-by: Li Yang <leoli at freescale.com>
+Signed-off-by: Hou Zhiqiang <B48286 at freescale.com>
+Signed-off-by: Mingkai Hu <Mingkai.Hu at freescale.com>
+Signed-off-by: Wenbin Song <Wenbin.Song at freescale.com>
+Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 +++++++++++++++++++++++++
+ 1 file changed, 525 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+new file mode 100644
+index 0000000..cb00a84
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -0,0 +1,525 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015, Freescale Semiconductor
++ *
++ * Mingkai Hu <Mingkai.hu at freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/ {
++	compatible = "fsl,ls1043a";
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	cpus {
++		#address-cells = <2>;
++		#size-cells = <0>;
++
++		/*
++		 * We expect the enable-method for cpu's to be "psci", but this
++		 * is dependent on the SoC FW, which will fill this in.
++		 *
++		 * Currently supported enable-method is psci v0.2
++		 */
++		cpu0: cpu at 0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x0 0x0>;
++			clocks = <&clockgen 1 0>;
++		};
++
++		cpu1: cpu at 1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x0 0x1>;
++			clocks = <&clockgen 1 0>;
++		};
++
++		cpu2: cpu at 2 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x0 0x2>;
++			clocks = <&clockgen 1 0>;
++		};
++
++		cpu3: cpu at 3 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x0 0x3>;
++			clocks = <&clockgen 1 0>;
++		};
++	};
++
++	memory at 80000000 {
++		device_type = "memory";
++		reg = <0x0 0x80000000 0 0x80000000>;
++		      /* DRAM space 1, size: 2GiB DRAM */
++	};
++
++	sysclk: sysclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "sysclk";
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <1 13 0x1>, /* Physical Secure PPI */
++			     <1 14 0x1>, /* Physical Non-Secure PPI */
++			     <1 11 0x1>, /* Virtual PPI */
++			     <1 10 0x1>; /* Hypervisor PPI */
++	};
++
++	pmu {
++		compatible = "arm,armv8-pmuv3";
++		interrupts = <0 106 0x4>,
++			     <0 107 0x4>,
++			     <0 95 0x4>,
++			     <0 97 0x4>;
++		interrupt-affinity = <&cpu0>,
++				     <&cpu1>,
++				     <&cpu2>,
++				     <&cpu3>;
++	};
++
++	gic: interrupt-controller at 1400000 {
++		compatible = "arm,gic-400";
++		#interrupt-cells = <3>;
++		interrupt-controller;
++		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
++		      <0x0 0x1402000 0 0x2000>, /* GICC */
++		      <0x0 0x1404000 0 0x2000>, /* GICH */
++		      <0x0 0x1406000 0 0x2000>; /* GICV */
++		interrupts = <1 9 0xf08>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		clockgen: clocking at 1ee1000 {
++			compatible = "fsl,ls1043a-clockgen";
++			reg = <0x0 0x1ee1000 0x0 0x1000>;
++			#clock-cells = <2>;
++			clocks = <&sysclk>;
++		};
++
++		scfg: scfg at 1570000 {
++			compatible = "fsl,ls1043a-scfg", "syscon";
++			reg = <0x0 0x1570000 0x0 0x10000>;
++			big-endian;
++		};
++
++		dcfg: dcfg at 1ee0000 {
++			compatible = "fsl,ls1043a-dcfg", "syscon";
++			reg = <0x0 0x1ee0000 0x0 0x10000>;
++		};
++
++		ifc: ifc at 1530000 {
++			compatible = "fsl,ifc", "simple-bus";
++			reg = <0x0 0x1530000 0x0 0x10000>;
++			interrupts = <0 43 0x4>;
++		};
++
++		esdhc: esdhc at 1560000 {
++			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
++			reg = <0x0 0x1560000 0x0 0x10000>;
++			interrupts = <0 62 0x4>;
++			clock-frequency = <0>;
++			voltage-ranges = <1800 1800 3300 3300>;
++			sdhci,auto-cmd12;
++			big-endian;
++			bus-width = <4>;
++		};
++
++		dspi0: dspi at 2100000 {
++			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2100000 0x0 0x10000>;
++			interrupts = <0 64 0x4>;
++			clock-names = "dspi";
++			clocks = <&clockgen 4 0>;
++			spi-num-chipselects = <5>;
++			big-endian;
++			status = "disabled";
++		};
++
++		dspi1: dspi at 2110000 {
++			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2110000 0x0 0x10000>;
++			interrupts = <0 65 0x4>;
++			clock-names = "dspi";
++			clocks = <&clockgen 4 0>;
++			spi-num-chipselects = <5>;
++			big-endian;
++			status = "disabled";
++		};
++
++		i2c0: i2c at 2180000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2180000 0x0 0x10000>;
++			interrupts = <0 56 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 0>;
++			dmas = <&edma0 1 39>,
++			       <&edma0 1 38>;
++			dma-names = "tx", "rx";
++			status = "disabled";
++		};
++
++		i2c1: i2c at 2190000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2190000 0x0 0x10000>;
++			interrupts = <0 57 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 0>;
++			status = "disabled";
++		};
++
++		i2c2: i2c at 21a0000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x21a0000 0x0 0x10000>;
++			interrupts = <0 58 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 0>;
++			status = "disabled";
++		};
++
++		i2c3: i2c at 21b0000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x21b0000 0x0 0x10000>;
++			interrupts = <0 59 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 0>;
++			status = "disabled";
++		};
++
++		duart0: serial at 21c0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0500 0x0 0x100>;
++			interrupts = <0 54 0x4>;
++			clocks = <&clockgen 4 0>;
++		};
++
++		duart1: serial at 21c0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0600 0x0 0x100>;
++			interrupts = <0 54 0x4>;
++			clocks = <&clockgen 4 0>;
++		};
++
++		duart2: serial at 21d0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21d0500 0x0 0x100>;
++			interrupts = <0 55 0x4>;
++			clocks = <&clockgen 4 0>;
++		};
++
++		duart3: serial at 21d0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21d0600 0x0 0x100>;
++			interrupts = <0 55 0x4>;
++			clocks = <&clockgen 4 0>;
++		};
++
++		gpio1: gpio at 2300000 {
++			compatible = "fsl,ls1043a-gpio";
++			reg = <0x0 0x2300000 0x0 0x10000>;
++			interrupts = <0 66 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio2: gpio at 2310000 {
++			compatible = "fsl,ls1043a-gpio";
++			reg = <0x0 0x2310000 0x0 0x10000>;
++			interrupts = <0 67 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio3: gpio at 2320000 {
++			compatible = "fsl,ls1043a-gpio";
++			reg = <0x0 0x2320000 0x0 0x10000>;
++			interrupts = <0 68 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio4: gpio at 2330000 {
++			compatible = "fsl,ls1043a-gpio";
++			reg = <0x0 0x2330000 0x0 0x10000>;
++			interrupts = <0 134 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		lpuart0: serial at 2950000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2950000 0x0 0x1000>;
++			interrupts = <0 48 0x4>;
++			clocks = <&clockgen 0 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart1: serial at 2960000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2960000 0x0 0x1000>;
++			interrupts = <0 49 0x4>;
++			clocks = <&clockgen 4 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart2: serial at 2970000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2970000 0x0 0x1000>;
++			interrupts = <0 50 0x4>;
++			clocks = <&clockgen 4 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart3: serial at 2980000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2980000 0x0 0x1000>;
++			interrupts = <0 51 0x4>;
++			clocks = <&clockgen 4 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart4: serial at 2990000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2990000 0x0 0x1000>;
++			interrupts = <0 52 0x4>;
++			clocks = <&clockgen 4 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart5: serial at 29a0000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x29a0000 0x0 0x1000>;
++			interrupts = <0 53 0x4>;
++			clocks = <&clockgen 4 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		wdog0: wdog at 2ad0000 {
++			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
++			reg = <0x0 0x2ad0000 0x0 0x10000>;
++			interrupts = <0 83 0x4>;
++			clocks = <&clockgen 4 0>;
++			clock-names = "wdog";
++			big-endian;
++		};
++
++		edma0: edma at 2c00000 {
++			#dma-cells = <2>;
++			compatible = "fsl,vf610-edma";
++			reg = <0x0 0x2c00000 0x0 0x10000>,
++			      <0x0 0x2c10000 0x0 0x10000>,
++			      <0x0 0x2c20000 0x0 0x10000>;
++			interrupts = <0 103 0x4>,
++				     <0 103 0x4>;
++			interrupt-names = "edma-tx", "edma-err";
++			dma-channels = <32>;
++			big-endian;
++			clock-names = "dmamux0", "dmamux1";
++			clocks = <&clockgen 4 0>,
++				 <&clockgen 4 0>;
++		};
++
++		usb0: usb3 at 2f00000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x2f00000 0x0 0x10000>;
++			interrupts = <0 60 0x4>;
++			dr_mode = "host";
++		};
++
++		usb1: usb3 at 3000000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3000000 0x0 0x10000>;
++			interrupts = <0 61 0x4>;
++			dr_mode = "host";
++		};
++
++		usb2: usb3 at 3100000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3100000 0x0 0x10000>;
++			interrupts = <0 63 0x4>;
++			dr_mode = "host";
++		};
++
++		sata: sata at 3200000 {
++			compatible = "fsl,ls1043a-ahci";
++			reg = <0x0 0x3200000 0x0 0x10000>;
++			interrupts = <0 69 0x4>;
++			clocks = <&clockgen 4 0>;
++		};
++
++		msi1: msi-controller1 at 1571000 {
++			compatible = "fsl,1s1043a-msi";
++			reg = <0x0 0x1571000 0x0 0x4>,
++			      <0x0 0x1571004 0x0 0x4>;
++			reg-names = "msiir", "msir";
++			msi-controller;
++			interrupts = <0 116 0x4>;
++		};
++
++		msi2: msi-controller2 at 1572000 {
++			compatible = "fsl,1s1043a-msi";
++			reg = <0x0 0x1572000 0x0 0x4>,
++			      <0x0 0x1572004 0x0 0x4>;
++			reg-names = "msiir", "msir";
++			msi-controller;
++			interrupts = <0 126 0x4>;
++		};
++
++		msi3: msi-controller3 at 1573000 {
++			compatible = "fsl,1s1043a-msi";
++			reg = <0x0 0x1573000 0x0 0x4>,
++			      <0x0 0x1573004 0x0 0x4>;
++			reg-names = "msiir", "msir";
++			msi-controller;
++			interrupts = <0 160 0x4>;
++		};
++
++		pcie at 3400000 {
++			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 118 0x4>, /* controller interrupt */
++				     <0 117 0x4>; /* PME interrupt */
++			interrupt-names = "intr", "pme";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi1>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
++					<0000 0 0 2 &gic 0 111 0x4>,
++					<0000 0 0 3 &gic 0 112 0x4>,
++					<0000 0 0 4 &gic 0 113 0x4>;
++		};
++
++		pcie at 3500000 {
++			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
++			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 128 0x4>,
++				     <0 127 0x4>;
++			interrupt-names = "intr", "pme";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			num-lanes = <2>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi2>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
++					<0000 0 0 2 &gic 0 121 0x4>,
++					<0000 0 0 3 &gic 0 122 0x4>,
++					<0000 0 0 4 &gic 0 123 0x4>;
++		};
++
++		pcie at 3600000 {
++			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
++			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 162 0x4>,
++				     <0 161 0x4>;
++			interrupt-names = "intr", "pme";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			num-lanes = <2>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi3>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
++					<0000 0 0 2 &gic 0 155 0x4>,
++					<0000 0 0 3 &gic 0 156 0x4>,
++					<0000 0 0 4 &gic 0 157 0x4>;
++		};
++	};
++
++};
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0002-arm64-Move-LS2080A-compilation-under-ARCH_LAYERSCAPE.patch b/target/linux/layerscape-64b/patches-4.1/0002-arm64-Move-LS2080A-compilation-under-ARCH_LAYERSCAPE.patch
new file mode 100644
index 0000000..1886cc3
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0002-arm64-Move-LS2080A-compilation-under-ARCH_LAYERSCAPE.patch
@@ -0,0 +1,31 @@
+From df2ccfd4f949234baad7bdabea187b31218976b5 Mon Sep 17 00:00:00 2001
+From: Rai Harninder-B01044 <harninder.rai at freescale.com>
+Date: Mon, 18 Apr 2016 15:39:11 +0800
+Subject: [PATCH 002/151] arm64: Move LS2080A compilation under ARCH_LAYERSCAPE
+
+commit d40c2fe65ebfbd88fd5e2eafc92df6a597c28136
+[context adjustment]
+
+ARCH_LAYERSCAPE is the common define for Layerscape SoC family
+So, move the compilation of LS2085A device tree files under
+this define
+
+Signed-off-by: Rai Harninder-B01044 <harninder.rai at freescale.com>
+Integrated-by: Zhao Qiang <qiang.zhao at nxp.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index 4f2de3e..fc6fca3 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -1,4 +1,4 @@
+-dtb-$(CONFIG_ARCH_FSL_LS2085A) += fsl-ls2085a-simu.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2085a-simu.dtb
+  
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0003-dts-ls1043a-add-LS1043ARDB-board-support.patch b/target/linux/layerscape-64b/patches-4.1/0003-dts-ls1043a-add-LS1043ARDB-board-support.patch
new file mode 100644
index 0000000..ecbd875
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0003-dts-ls1043a-add-LS1043ARDB-board-support.patch
@@ -0,0 +1,156 @@
+From ac9d9c52ee5d18870654b9e893ed81c7f9957a99 Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie at freescale.com>
+Date: Mon, 18 Apr 2016 15:44:25 +0800
+Subject: [PATCH 003/151] dts/ls1043a: add LS1043ARDB board support
+
+commit 9a6fce16a82d3412c9350b9f08eacebaa81c0a3d
+[context adjustment]
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
+Signed-off-by: Mingkai Hu <Mingkai.Hu at freescale.com>
+Signed-off-by: Wenbin Song <Wenbin.Song at freescale.com>
+Signed-off-by: Hou Zhiqiang <B48286 at freescale.com>
+Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
+Integrated-by: Zhao Qiang <qiang.zhao at nxp.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile            |   2 +-
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 117 ++++++++++++++++++++++
+ 2 files changed, 118 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index fc6fca3..5d847c8 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -1,4 +1,4 @@
+-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2085a-simu.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2085a-simu.dtb fsl-ls1043a-rdb.dtb
+  
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+new file mode 100644
+index 0000000..c95a0e7
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -0,0 +1,117 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015, Freescale Semiconductor
++ *
++ * Mingkai Hu <Mingkai.hu at freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "fsl-ls1043a.dtsi"
++
++/ {
++	model = "LS1043A RDB Board";
++	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
++};
++
++&i2c0 {
++	status = "okay";
++	ina220 at 40 {
++		compatible = "ti,ina220";
++		reg = <0x40>;
++		shunt-resistor = <1000>;
++	};
++	adt7461a at 4c {
++		compatible = "adi,adt7461";
++		reg = <0x4c>;
++	};
++	eeprom at 56 {
++		compatible = "at24,24c512";
++		reg = <0x52>;
++	};
++	eeprom at 57 {
++		compatible = "at24,24c512";
++		reg = <0x53>;
++	};
++	rtc at 68 {
++		compatible = "pericom,pt7c4338";
++		reg = <0x68>;
++	};
++};
++
++&ifc {
++	status = "okay";
++	#address-cells = <2>;
++	#size-cells = <1>;
++	/* NOR, NAND Flashes and FPGA on board */
++	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
++		  0x1 0x0 0x0 0x7e800000 0x00010000
++		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
++
++		nor at 0,0 {
++			compatible = "cfi-flash";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			reg = <0x0 0x0 0x8000000>;
++			bank-width = <2>;
++			device-width = <1>;
++		};
++
++		nand at 1,0 {
++			compatible = "fsl,ifc-nand";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			reg = <0x1 0x0 0x10000>;
++		};
++
++		cpld: board-control at 2,0 {
++			compatible = "fsl,ls1043ardb-cpld";
++			reg = <0x2 0x0 0x0000100>;
++		};
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&duart1 {
++	status = "okay";
++};
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0004-arm64-Define-ARCH_LAYERSCAPE-for-Layerscape-SoC-fami.patch b/target/linux/layerscape-64b/patches-4.1/0004-arm64-Define-ARCH_LAYERSCAPE-for-Layerscape-SoC-fami.patch
new file mode 100644
index 0000000..1a09f69
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0004-arm64-Define-ARCH_LAYERSCAPE-for-Layerscape-SoC-fami.patch
@@ -0,0 +1,49 @@
+From 2593849ea9e052411e9de5e68064942db901d9a9 Mon Sep 17 00:00:00 2001
+From: Rai Harninder-B01044 <harninder.rai at freescale.com>
+Date: Tue, 27 Oct 2015 13:20:12 +0530
+Subject: [PATCH 004/151] arm64: Define ARCH_LAYERSCAPE for Layerscape SoC
+ family
+
+Introduce a common ARCH_LAYERSCAPE for layerscape SoC family
+and remove the erstwhile specific ARCH_FSL_LS2085A
+
+Signed-off-by: Rai Harninder-B01044 <harninder.rai at freescale.com>
+---
+ arch/arm64/Kconfig           | 6 +++---
+ arch/arm64/configs/defconfig | 2 +-
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
+index 6f0a3b4..bf4c50b 100644
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -180,10 +180,10 @@ config ARCH_EXYNOS7
+ 	help
+ 	  This enables support for Samsung Exynos7 SoC family
+ 
+-config ARCH_FSL_LS2085A
+-	bool "Freescale LS2085A SOC"
++config ARCH_LAYERSCAPE
++	bool "Freescale Layerscape SoC family"
+ 	help
+-	  This enables support for Freescale LS2085A SOC.
++	  This enables support for Freescale Layerscape SoC family
+ 
+ config ARCH_MEDIATEK
+ 	bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 2ed7449..bfdc78c 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -32,7 +32,7 @@ CONFIG_MODULE_UNLOAD=y
+ # CONFIG_BLK_DEV_BSG is not set
+ # CONFIG_IOSCHED_DEADLINE is not set
+ CONFIG_ARCH_EXYNOS7=y
+-CONFIG_ARCH_FSL_LS2085A=y
++CONFIG_ARCH_LAYERSCAPE=y
+ CONFIG_ARCH_MEDIATEK=y
+ CONFIG_ARCH_SEATTLE=y
+ CONFIG_ARCH_TEGRA=y
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0005-clk-qoriq-Move-chip-specific-knowledge-into-driver.patch b/target/linux/layerscape-64b/patches-4.1/0005-clk-qoriq-Move-chip-specific-knowledge-into-driver.patch
new file mode 100644
index 0000000..6e7df85
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0005-clk-qoriq-Move-chip-specific-knowledge-into-driver.patch
@@ -0,0 +1,1579 @@
+From 600b6fee7a14ef13bbeccb3d4ca4bfb9c62c9e31 Mon Sep 17 00:00:00 2001
+From: Scott Wood <scottwood at freescale.com>
+Date: Fri, 15 Jan 2016 07:34:25 +0000
+Subject: [PATCH 005/151] clk: qoriq: Move chip-specific knowledge into driver
+
+The device tree should describe the chips (or chip-like subblocks) in
+the system, but it generally does not describe individual registers --
+it should identify, rather than describe, a programming interface.
+
+This has not been the case with the QorIQ clockgen nodes.  The
+knowledge of what each bit setting of CLKCnCSR means is encoded in
+three places (binding, pll node, and mux node), and the last also needs
+to know which options are valid on a particular chip.  All three of
+these locations are considered stable ABI, making it difficult to fix
+mistakes (of which I have found several), much less refactor the
+abstraction to be able to address problems, limitations, or new chips.
+
+Under the current binding, a pll clock specifier of 2 means that the
+PLL is divided by 4 -- and the driver implements this, unless there
+happen to be four clock-output-names rather than 3, in which case it
+interprets it as PLL divided by 3.  This does not appear in the binding
+documentation at all.  That hack is now considered stable ABI.
+
+The current device tree nodes contain errors, such as saying that
+T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options.
+The current binding also ignores some restrictions on clock selection,
+such as p5020's requirement that if a core uses the "wrong" PLL, that
+PLL must be clocked lower than the "correct" PLL and be at most 80% of
+the rated CPU frequency.
+
+Possibly because of the lack of the ability to express such nuance in
+the binding, some valid options are omitted from the device trees, such
+as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from
+PLL1 (again, only if they are at most 80% of rated CPU frequency).
+This omission, combined with excessive caution in the cpufreq driver
+(addressed in a subsequent patch), means that currently on a 1500 MHz
+p4080 with typical PLL configuration, cpufreq can lower the frequency
+to 1200 MHz on half the CPUs and do nothing on the others.  With this
+patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a
+rev3 p4080 half can be lowered to 750 MHz and the other half to 600
+MHz.
+
+The current binding only deals with CPU clocks.  To describe FMan in
+the device tree, we need to describe its clock.  Some chips have
+additional muxes that work like the CPU muxes, but are not described in
+the device tree.  Others require inspecting the Reset Control Word to
+determine which PLL is used.  Rather than continue to extend this mess,
+replace it.  Have the driver bind to the chip-specific clockgen
+compatible, and keep the detailed description of quirky chip variations
+in the driver, where it can be easily fixed, refactored, and extended.
+
+Older device trees will continue to work (including a workaround for
+old ls1021a device trees that are missing compatible and reg in the
+clockgen node, which even the old binding required).  The pll/mux
+details in old device trees will be ignored, but "clocks" properties
+pointing at the old nodes will still work, and be directed at the
+corresponding new clock.
+
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+Acked-by: Stephen Boyd <sboyd at codeaurora.org>
+(cherry picked from commit 0dfc86b3173feee96f36e71879aa6dd56a4d7925)
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+---
+ .../devicetree/bindings/clock/qoriq-clock.txt      |   61 +-
+ drivers/clk/clk-qoriq.c                            | 1261 ++++++++++++++++----
+ 2 files changed, 1090 insertions(+), 232 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+index df4a259..16a3ec4 100644
+--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
++++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+@@ -1,6 +1,6 @@
+ * Clock Block on Freescale QorIQ Platforms
+ 
+-Freescale qoriq chips take primary clocking input from the external
++Freescale QorIQ chips take primary clocking input from the external
+ SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+ multiple phase locked loops (PLL) to create a variety of frequencies
+ which can then be passed to a variety of internal logic, including
+@@ -13,14 +13,16 @@ which the chip complies.
+ Chassis Version		Example Chips
+ ---------------		-------------
+ 1.0			p4080, p5020, p5040
+-2.0			t4240, b4860, t1040
++2.0			t4240, b4860
+ 
+ 1. Clock Block Binding
+ 
+ Required properties:
+-- compatible: Should contain a specific clock block compatible string
+-	and a single chassis clock compatible string.
+-	Clock block strings include, but not limited to, one of the:
++- compatible: Should contain a chip-specific clock block compatible
++	string and (if applicable) may contain a chassis-version clock
++	compatible string.
++
++	Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
+ 	* "fsl,p2041-clockgen"
+ 	* "fsl,p3041-clockgen"
+ 	* "fsl,p4080-clockgen"
+@@ -30,15 +32,14 @@ Required properties:
+ 	* "fsl,b4420-clockgen"
+ 	* "fsl,b4860-clockgen"
+ 	* "fsl,ls1021a-clockgen"
+-	Chassis clock strings include:
++	Chassis-version clock strings include:
+ 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
+ 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
+ - reg: Describes the address of the device's resources within the
+ 	address space defined by its parent bus, and resource zero
+ 	represents the clock register set
+-- clock-frequency: Input system clock frequency
+ 
+-Recommended properties:
++Optional properties:
+ - ranges: Allows valid translation between child's address space and
+ 	parent's. Must be present if the device has sub-nodes.
+ - #address-cells: Specifies the number of cells used to represent
+@@ -47,8 +48,46 @@ Recommended properties:
+ - #size-cells: Specifies the number of cells used to represent
+ 	the size of an address. Must be present if the device has
+ 	sub-nodes and set to 1 if present
++- clock-frequency: Input system clock frequency (SYSCLK)
++- clocks: If clock-frequency is not specified, sysclk may be provided
++	as an input clock.  Either clock-frequency or clocks must be
++	provided.
++
++2. Clock Provider
++
++The clockgen node should act as a clock provider, though in older device
++trees the children of the clockgen node are the clock providers.
++
++When the clockgen node is a clock provider, #clock-cells = <2>.
++The first cell of the clock specifier is the clock type, and the
++second cell is the clock index for the specified type.
++
++	Type#	Name		Index Cell
++	0	sysclk		must be 0
++	1	cmux		index (n in CLKCnCSR)
++	2	hwaccel		index (n in CLKCGnHWACSR)
++	3	fman		0 for fm1, 1 for fm2
++	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
++
++3. Example
++
++	clockgen: global-utilities at e1000 {
++		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
++		clock-frequency = <133333333>;
++		reg = <0xe1000 0x1000>;
++		#clock-cells = <2>;
++	};
++
++	fman at 400000 {
++		...
++		clocks = <&clockgen 3 0>;
++		...
++	};
++}
++4. Legacy Child Nodes
+ 
+-2. Clock Provider/Consumer Binding
++NOTE: These nodes are deprecated.  Kernels should continue to support
++device trees with these nodes, but new device trees should not use them.
+ 
+ Most of the bindings are from the common clock binding[1].
+  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+@@ -82,7 +121,7 @@ Recommended properties:
+ - reg: Should be the offset and length of clock block base address.
+ 	The length should be 4.
+ 
+-Example for clock block and clock provider:
++Legacy Example:
+ / {
+ 	clockgen: global-utilities at e1000 {
+ 		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+@@ -142,7 +181,7 @@ Example for clock block and clock provider:
+ 	};
+ };
+ 
+-Example for clock consumer:
++Example for legacy clock consumer:
+ 
+ / {
+ 	cpu0: PowerPC,e5500 at 0 {
+diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
+index cda90a9..06281a3 100644
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -10,7 +10,9 @@
+ 
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+ 
++#include <linux/clk.h>
+ #include <linux/clk-provider.h>
++#include <linux/fsl/guts.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+@@ -19,213 +21,934 @@
+ #include <linux/of.h>
+ #include <linux/slab.h>
+ 
+-struct cmux_clk {
++#define PLL_DIV1	0
++#define PLL_DIV2	1
++#define PLL_DIV3	2
++#define PLL_DIV4	3
++
++#define PLATFORM_PLL	0
++#define CGA_PLL1	1
++#define CGA_PLL2	2
++#define CGA_PLL3	3
++#define CGA_PLL4	4	/* only on clockgen-1.0, which lacks CGB */
++#define CGB_PLL1	4
++#define CGB_PLL2	5
++
++struct clockgen_pll_div {
++	struct clk *clk;
++	char name[32];
++};
++
++struct clockgen_pll {
++	struct clockgen_pll_div div[4];
++};
++
++#define CLKSEL_VALID	1
++#define CLKSEL_80PCT	2	/* Only allowed if PLL <= 80% of max cpu freq */
++
++struct clockgen_sourceinfo {
++	u32 flags;	/* CLKSEL_xxx */
++	int pll;	/* CGx_PLLn */
++	int div;	/* PLL_DIVn */
++};
++
++#define NUM_MUX_PARENTS	16
++
++struct clockgen_muxinfo {
++	struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
++};
++
++#define NUM_HWACCEL	5
++#define NUM_CMUX	8
++
++struct clockgen;
++
++/*
++ * cmux freq must be >= platform pll.
++ * If not set, cmux freq must be >= platform pll/2
++ */
++#define CG_CMUX_GE_PLAT		1
++#define CG_PLL_8BIT		2	/* PLLCnGSR[CFG] is 8 bits, not 6 */
++
++struct clockgen_chipinfo {
++	const char *compat, *guts_compat;
++	const struct clockgen_muxinfo *cmux_groups[2];
++	const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
++	void (*init_periph)(struct clockgen *cg);
++	int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
++	u32 pll_mask;	/* 1 << n bit set if PLL n is valid */
++	u32 flags;	/* CG_xxx */
++};
++
++struct clockgen {
++	struct device_node *node;
++	void __iomem *regs;
++	struct clockgen_chipinfo info; /* mutable copy */
++	struct clk *sysclk;
++	struct clockgen_pll pll[6];
++	struct clk *cmux[NUM_CMUX];
++	struct clk *hwaccel[NUM_HWACCEL];
++	struct clk *fman[2];
++	struct ccsr_guts __iomem *guts;
++};
++
++static struct clockgen clockgen;
++
++static const struct clockgen_muxinfo p2041_cmux_grp1 = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++	}
++};
++
++static const struct clockgen_muxinfo p2041_cmux_grp2 = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		[4] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++	}
++};
++
++static const struct clockgen_muxinfo p5020_cmux_grp1 = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		[4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
++	}
++};
++
++static const struct clockgen_muxinfo p5020_cmux_grp2 = {
++	{
++		[0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
++		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++	}
++};
++
++static const struct clockgen_muxinfo p5040_cmux_grp1 = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		[4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
++		[5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
++	}
++};
++
++static const struct clockgen_muxinfo p5040_cmux_grp2 = {
++	{
++		[0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
++		[1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
++		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++	}
++};
++
++static const struct clockgen_muxinfo p4080_cmux_grp1 = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		[8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
++	}
++};
++
++static const struct clockgen_muxinfo p4080_cmux_grp2 = {
++	{
++		[0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
++		[8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
++		[9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
++		[12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
++		[13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
++	}
++};
++
++static const struct clockgen_muxinfo t1023_cmux = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++	}
++};
++
++static const struct clockgen_muxinfo t1040_cmux = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++	}
++};
++
++
++static const struct clockgen_muxinfo clockgen2_cmux_cga = {
++	{
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
++		{},
++		{ CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
++	},
++};
++
++static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
++	{
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
++	},
++};
++
++static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
++	{
++		{ CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
++		{ CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
++		{},
++		{ CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
++		{ CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
++	},
++};
++
++static const struct clockgen_muxinfo t1023_hwa1 = {
++	{
++		{},
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
++	},
++};
++
++static const struct clockgen_muxinfo t1023_hwa2 = {
++	{
++		[6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++	},
++};
++
++static const struct clockgen_muxinfo t2080_hwa1 = {
++	{
++		{},
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
++		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++	},
++};
++
++static const struct clockgen_muxinfo t2080_hwa2 = {
++	{
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
++		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
++	},
++};
++
++static const struct clockgen_muxinfo t4240_hwa1 = {
++	{
++		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++	},
++};
++
++static const struct clockgen_muxinfo t4240_hwa4 = {
++	{
++		[2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
++		[3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
++		[4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
++		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
++		[6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
++	},
++};
++
++static const struct clockgen_muxinfo t4240_hwa5 = {
++	{
++		[2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
++		[3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
++		[4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
++		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
++		[6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
++		[7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
++	},
++};
++
++#define RCWSR7_FM1_CLK_SEL	0x40000000
++#define RCWSR7_FM2_CLK_SEL	0x20000000
++#define RCWSR7_HWA_ASYNC_DIV	0x04000000
++
++static void __init p2041_init_periph(struct clockgen *cg)
++{
++	u32 reg;
++
++	reg = ioread32be(&cg->guts->rcwsr[7]);
++
++	if (reg & RCWSR7_FM1_CLK_SEL)
++		cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
++	else
++		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
++}
++
++static void __init p4080_init_periph(struct clockgen *cg)
++{
++	u32 reg;
++
++	reg = ioread32be(&cg->guts->rcwsr[7]);
++
++	if (reg & RCWSR7_FM1_CLK_SEL)
++		cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
++	else
++		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
++
++	if (reg & RCWSR7_FM2_CLK_SEL)
++		cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
++	else
++		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
++}
++
++static void __init p5020_init_periph(struct clockgen *cg)
++{
++	u32 reg;
++	int div = PLL_DIV2;
++
++	reg = ioread32be(&cg->guts->rcwsr[7]);
++	if (reg & RCWSR7_HWA_ASYNC_DIV)
++		div = PLL_DIV4;
++
++	if (reg & RCWSR7_FM1_CLK_SEL)
++		cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
++	else
++		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
++}
++
++static void __init p5040_init_periph(struct clockgen *cg)
++{
++	u32 reg;
++	int div = PLL_DIV2;
++
++	reg = ioread32be(&cg->guts->rcwsr[7]);
++	if (reg & RCWSR7_HWA_ASYNC_DIV)
++		div = PLL_DIV4;
++
++	if (reg & RCWSR7_FM1_CLK_SEL)
++		cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
++	else
++		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
++
++	if (reg & RCWSR7_FM2_CLK_SEL)
++		cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
++	else
++		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
++}
++
++static void __init t1023_init_periph(struct clockgen *cg)
++{
++	cg->fman[0] = cg->hwaccel[1];
++}
++
++static void __init t1040_init_periph(struct clockgen *cg)
++{
++	cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
++}
++
++static void __init t2080_init_periph(struct clockgen *cg)
++{
++	cg->fman[0] = cg->hwaccel[0];
++}
++
++static void __init t4240_init_periph(struct clockgen *cg)
++{
++	cg->fman[0] = cg->hwaccel[3];
++	cg->fman[1] = cg->hwaccel[4];
++}
++
++static const struct clockgen_chipinfo chipinfo[] = {
++	{
++		.compat = "fsl,b4420-clockgen",
++		.guts_compat = "fsl,b4860-device-config",
++		.init_periph = t2080_init_periph,
++		.cmux_groups = {
++			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
++		},
++		.hwaccel = {
++			&t2080_hwa1
++		},
++		.cmux_to_group = {
++			0, 1, 1, 1, -1
++		},
++		.pll_mask = 0x3f,
++		.flags = CG_PLL_8BIT,
++	},
++	{
++		.compat = "fsl,b4860-clockgen",
++		.guts_compat = "fsl,b4860-device-config",
++		.init_periph = t2080_init_periph,
++		.cmux_groups = {
++			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
++		},
++		.hwaccel = {
++			&t2080_hwa1
++		},
++		.cmux_to_group = {
++			0, 1, 1, 1, -1
++		},
++		.pll_mask = 0x3f,
++		.flags = CG_PLL_8BIT,
++	},
++	{
++		.compat = "fsl,ls1021a-clockgen",
++		.cmux_groups = {
++			&t1023_cmux
++		},
++		.cmux_to_group = {
++			0, -1
++		},
++		.pll_mask = 0x03,
++	},
++	{
++		.compat = "fsl,p2041-clockgen",
++		.guts_compat = "fsl,qoriq-device-config-1.0",
++		.init_periph = p2041_init_periph,
++		.cmux_groups = {
++			&p2041_cmux_grp1, &p2041_cmux_grp2
++		},
++		.cmux_to_group = {
++			0, 0, 1, 1, -1
++		},
++		.pll_mask = 0x07,
++	},
++	{
++		.compat = "fsl,p3041-clockgen",
++		.guts_compat = "fsl,qoriq-device-config-1.0",
++		.init_periph = p2041_init_periph,
++		.cmux_groups = {
++			&p2041_cmux_grp1, &p2041_cmux_grp2
++		},
++		.cmux_to_group = {
++			0, 0, 1, 1, -1
++		},
++		.pll_mask = 0x07,
++	},
++	{
++		.compat = "fsl,p4080-clockgen",
++		.guts_compat = "fsl,qoriq-device-config-1.0",
++		.init_periph = p4080_init_periph,
++		.cmux_groups = {
++			&p4080_cmux_grp1, &p4080_cmux_grp2
++		},
++		.cmux_to_group = {
++			0, 0, 0, 0, 1, 1, 1, 1
++		},
++		.pll_mask = 0x1f,
++	},
++	{
++		.compat = "fsl,p5020-clockgen",
++		.guts_compat = "fsl,qoriq-device-config-1.0",
++		.init_periph = p5020_init_periph,
++		.cmux_groups = {
++			&p2041_cmux_grp1, &p2041_cmux_grp2
++		},
++		.cmux_to_group = {
++			0, 1, -1
++		},
++		.pll_mask = 0x07,
++	},
++	{
++		.compat = "fsl,p5040-clockgen",
++		.guts_compat = "fsl,p5040-device-config",
++		.init_periph = p5040_init_periph,
++		.cmux_groups = {
++			&p5040_cmux_grp1, &p5040_cmux_grp2
++		},
++		.cmux_to_group = {
++			0, 0, 1, 1, -1
++		},
++		.pll_mask = 0x0f,
++	},
++	{
++		.compat = "fsl,t1023-clockgen",
++		.guts_compat = "fsl,t1023-device-config",
++		.init_periph = t1023_init_periph,
++		.cmux_groups = {
++			&t1023_cmux
++		},
++		.hwaccel = {
++			&t1023_hwa1, &t1023_hwa2
++		},
++		.cmux_to_group = {
++			0, 0, -1
++		},
++		.pll_mask = 0x03,
++		.flags = CG_PLL_8BIT,
++	},
++	{
++		.compat = "fsl,t1040-clockgen",
++		.guts_compat = "fsl,t1040-device-config",
++		.init_periph = t1040_init_periph,
++		.cmux_groups = {
++			&t1040_cmux
++		},
++		.cmux_to_group = {
++			0, 0, 0, 0, -1
++		},
++		.pll_mask = 0x07,
++		.flags = CG_PLL_8BIT,
++	},
++	{
++		.compat = "fsl,t2080-clockgen",
++		.guts_compat = "fsl,t2080-device-config",
++		.init_periph = t2080_init_periph,
++		.cmux_groups = {
++			&clockgen2_cmux_cga12
++		},
++		.hwaccel = {
++			&t2080_hwa1, &t2080_hwa2
++		},
++		.cmux_to_group = {
++			0, -1
++		},
++		.pll_mask = 0x07,
++		.flags = CG_PLL_8BIT,
++	},
++	{
++		.compat = "fsl,t4240-clockgen",
++		.guts_compat = "fsl,t4240-device-config",
++		.init_periph = t4240_init_periph,
++		.cmux_groups = {
++			&clockgen2_cmux_cga, &clockgen2_cmux_cgb
++		},
++		.hwaccel = {
++			&t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
++		},
++		.cmux_to_group = {
++			0, 0, 1, -1
++		},
++		.pll_mask = 0x3f,
++		.flags = CG_PLL_8BIT,
++	},
++	{},
++};
++
++struct mux_hwclock {
+ 	struct clk_hw hw;
+-	void __iomem *reg;
+-	unsigned int clk_per_pll;
+-	u32 flags;
++	struct clockgen *cg;
++	const struct clockgen_muxinfo *info;
++	u32 __iomem *reg;
++	u8 parent_to_clksel[NUM_MUX_PARENTS];
++	s8 clksel_to_parent[NUM_MUX_PARENTS];
++	int num_parents;
+ };
+ 
+-#define PLL_KILL			BIT(31)
++#define to_mux_hwclock(p)	container_of(p, struct mux_hwclock, hw)
++#define CLKSEL_MASK		0x78000000
+ #define	CLKSEL_SHIFT		27
+-#define CLKSEL_ADJUST		BIT(0)
+-#define to_cmux_clk(p)		container_of(p, struct cmux_clk, hw)
+ 
+-static int cmux_set_parent(struct clk_hw *hw, u8 idx)
++static int mux_set_parent(struct clk_hw *hw, u8 idx)
+ {
+-	struct cmux_clk *clk = to_cmux_clk(hw);
++	struct mux_hwclock *hwc = to_mux_hwclock(hw);
+ 	u32 clksel;
+ 
+-	clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll;
+-	if (clk->flags & CLKSEL_ADJUST)
+-		clksel += 8;
+-	clksel = (clksel & 0xf) << CLKSEL_SHIFT;
+-	iowrite32be(clksel, clk->reg);
++	if (idx >= hwc->num_parents)
++		return -EINVAL;
++
++	clksel = hwc->parent_to_clksel[idx];
++	iowrite32be((clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
+ 
+ 	return 0;
+ }
+ 
+-static u8 cmux_get_parent(struct clk_hw *hw)
++static u8 mux_get_parent(struct clk_hw *hw)
+ {
+-	struct cmux_clk *clk = to_cmux_clk(hw);
++	struct mux_hwclock *hwc = to_mux_hwclock(hw);
+ 	u32 clksel;
++	s8 ret;
+ 
+-	clksel = ioread32be(clk->reg);
+-	clksel = (clksel >> CLKSEL_SHIFT) & 0xf;
+-	if (clk->flags & CLKSEL_ADJUST)
+-		clksel -= 8;
+-	clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4;
++	clksel = (ioread32be(hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
+ 
+-	return clksel;
++	ret = hwc->clksel_to_parent[clksel];
++	if (ret < 0) {
++		pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
++		return 0;
++	}
++
++	return ret;
+ }
+ 
+ static const struct clk_ops cmux_ops = {
+-	.get_parent = cmux_get_parent,
+-	.set_parent = cmux_set_parent,
++	.get_parent = mux_get_parent,
++	.set_parent = mux_set_parent,
+ };
+ 
+-static void __init core_mux_init(struct device_node *np)
++/*
++ * Don't allow setting for now, as the clock options haven't been
++ * sanitized for additional restrictions.
++ */
++static const struct clk_ops hwaccel_ops = {
++	.get_parent = mux_get_parent,
++};
++
++static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
++						  struct mux_hwclock *hwc,
++						  int idx)
+ {
+-	struct clk *clk;
+-	struct clk_init_data init;
+-	struct cmux_clk *cmux_clk;
+-	struct device_node *node;
+-	int rc, count, i;
+-	u32	offset;
+-	const char *clk_name;
+-	const char **parent_names;
+-	struct of_phandle_args clkspec;
++	int pll, div;
+ 
+-	rc = of_property_read_u32(np, "reg", &offset);
+-	if (rc) {
+-		pr_err("%s: could not get reg property\n", np->name);
+-		return;
+-	}
++	if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
++		return NULL;
+ 
+-	/* get the input clock source count */
+-	count = of_property_count_strings(np, "clock-names");
+-	if (count < 0) {
+-		pr_err("%s: get clock count error\n", np->name);
+-		return;
+-	}
+-	parent_names = kcalloc(count, sizeof(char *), GFP_KERNEL);
+-	if (!parent_names)
+-		return;
++	pll = hwc->info->clksel[idx].pll;
++	div = hwc->info->clksel[idx].div;
+ 
+-	for (i = 0; i < count; i++)
+-		parent_names[i] = of_clk_get_parent_name(np, i);
++	return &cg->pll[pll].div[div];
++}
+ 
+-	cmux_clk = kzalloc(sizeof(*cmux_clk), GFP_KERNEL);
+-	if (!cmux_clk)
+-		goto err_name;
++static struct clk * __init create_mux_common(struct clockgen *cg,
++					     struct mux_hwclock *hwc,
++					     const struct clk_ops *ops,
++					     unsigned long min_rate,
++					     unsigned long pct80_rate,
++					     const char *fmt, int idx)
++{
++	struct clk_init_data init = {};
++	struct clk *clk;
++	const struct clockgen_pll_div *div;
++	const char *parent_names[NUM_MUX_PARENTS];
++	char name[32];
++	int i, j;
+ 
+-	cmux_clk->reg = of_iomap(np, 0);
+-	if (!cmux_clk->reg) {
+-		pr_err("%s: could not map register\n", __func__);
+-		goto err_clk;
+-	}
++	snprintf(name, sizeof(name), fmt, idx);
+ 
+-	rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,
+-					&clkspec);
+-	if (rc) {
+-		pr_err("%s: parse clock node error\n", __func__);
+-		goto err_clk;
+-	}
++	for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
++		unsigned long rate;
+ 
+-	cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np,
+-			"clock-output-names");
+-	of_node_put(clkspec.np);
++		hwc->clksel_to_parent[i] = -1;
+ 
+-	node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen");
+-	if (node && (offset >= 0x80))
+-		cmux_clk->flags = CLKSEL_ADJUST;
++		div = get_pll_div(cg, hwc, i);
++		if (!div)
++			continue;
+ 
+-	rc = of_property_read_string_index(np, "clock-output-names",
+-					   0, &clk_name);
+-	if (rc) {
+-		pr_err("%s: read clock names error\n", np->name);
+-		goto err_clk;
++		rate = clk_get_rate(div->clk);
++
++		if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
++		    rate > pct80_rate)
++			continue;
++		if (rate < min_rate)
++			continue;
++
++		parent_names[j] = div->name;
++		hwc->parent_to_clksel[j] = i;
++		hwc->clksel_to_parent[i] = j;
++		j++;
+ 	}
+ 
+-	init.name = clk_name;
+-	init.ops = &cmux_ops;
++	init.name = name;
++	init.ops = ops;
+ 	init.parent_names = parent_names;
+-	init.num_parents = count;
++	init.num_parents = hwc->num_parents = j;
+ 	init.flags = 0;
+-	cmux_clk->hw.init = &init;
++	hwc->hw.init = &init;
++	hwc->cg = cg;
+ 
+-	clk = clk_register(NULL, &cmux_clk->hw);
++	clk = clk_register(NULL, &hwc->hw);
+ 	if (IS_ERR(clk)) {
+-		pr_err("%s: could not register clock\n", clk_name);
+-		goto err_clk;
++		pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
++		       PTR_ERR(clk));
++		kfree(hwc);
++		return NULL;
++	}
++
++	return clk;
++}
++
++static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
++{
++	struct mux_hwclock *hwc;
++	const struct clockgen_pll_div *div;
++	unsigned long plat_rate, min_rate;
++	u64 pct80_rate;
++	u32 clksel;
++
++	hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
++	if (!hwc)
++		return NULL;
++
++	hwc->reg = cg->regs + 0x20 * idx;
++	hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
++
++	/*
++	 * Find the rate for the default clksel, and treat it as the
++	 * maximum rated core frequency.  If this is an incorrect
++	 * assumption, certain clock options (possibly including the
++	 * default clksel) may be inappropriately excluded on certain
++	 * chips.
++	 */
++	clksel = (ioread32be(hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
++	div = get_pll_div(cg, hwc, clksel);
++	if (!div)
++		return NULL;
++
++	pct80_rate = clk_get_rate(div->clk);
++	pct80_rate *= 8;
++	do_div(pct80_rate, 10);
++
++	plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
++
++	if (cg->info.flags & CG_CMUX_GE_PLAT)
++		min_rate = plat_rate;
++	else
++		min_rate = plat_rate / 2;
++
++	return create_mux_common(cg, hwc, &cmux_ops, min_rate,
++				 pct80_rate, "cg-cmux%d", idx);
++}
++
++static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
++{
++	struct mux_hwclock *hwc;
++
++	hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
++	if (!hwc)
++		return NULL;
++
++	hwc->reg = cg->regs + 0x20 * idx + 0x10;
++	hwc->info = cg->info.hwaccel[idx];
++
++	return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0,
++				 "cg-hwaccel%d", idx);
++}
++
++static void __init create_muxes(struct clockgen *cg)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
++		if (cg->info.cmux_to_group[i] < 0)
++			break;
++		if (cg->info.cmux_to_group[i] >=
++		    ARRAY_SIZE(cg->info.cmux_groups)) {
++			WARN_ON_ONCE(1);
++			continue;
++		}
++
++		cg->cmux[i] = create_one_cmux(cg, i);
+ 	}
+ 
++	for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
++		if (!cg->info.hwaccel[i])
++			continue;
++
++		cg->hwaccel[i] = create_one_hwaccel(cg, i);
++	}
++}
++
++static void __init clockgen_init(struct device_node *np);
++
++/* Legacy nodes may get probed before the parent clockgen node */
++static void __init legacy_init_clockgen(struct device_node *np)
++{
++	if (!clockgen.node)
++		clockgen_init(of_get_parent(np));
++}
++
++/* Legacy node */
++static void __init core_mux_init(struct device_node *np)
++{
++	struct clk *clk;
++	struct resource res;
++	int idx, rc;
++
++	legacy_init_clockgen(np);
++
++	if (of_address_to_resource(np, 0, &res))
++		return;
++
++	idx = (res.start & 0xf0) >> 5;
++	clk = clockgen.cmux[idx];
++
+ 	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ 	if (rc) {
+-		pr_err("Could not register clock provider for node:%s\n",
+-		       np->name);
+-		goto err_clk;
++		pr_err("%s: Couldn't register clk provider for node %s: %d\n",
++		       __func__, np->name, rc);
++		return;
+ 	}
+-	goto err_name;
++}
+ 
+-err_clk:
+-	kfree(cmux_clk);
+-err_name:
+-	/* free *_names because they are reallocated when registered */
+-	kfree(parent_names);
++static struct clk *sysclk_from_fixed(struct device_node *node, const char *name)
++{
++	u32 rate;
++
++	if (of_property_read_u32(node, "clock-frequency", &rate))
++		return ERR_PTR(-ENODEV);
++
++	return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+ }
+ 
+-static void __init core_pll_init(struct device_node *np)
++static struct clk *sysclk_from_parent(const char *name)
++{
++	struct clk *clk;
++	const char *parent_name;
++
++	clk = of_clk_get(clockgen.node, 0);
++	if (IS_ERR(clk))
++		return clk;
++
++	/* Register the input clock under the desired name. */
++	parent_name = __clk_get_name(clk);
++	clk = clk_register_fixed_factor(NULL, name, parent_name,
++					0, 1, 1);
++	if (IS_ERR(clk))
++		pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
++		       PTR_ERR(clk));
++
++	return clk;
++}
++
++static struct clk * __init create_sysclk(const char *name)
++{
++	struct device_node *sysclk;
++	struct clk *clk;
++
++	clk = sysclk_from_fixed(clockgen.node, name);
++	if (!IS_ERR(clk))
++		return clk;
++
++	clk = sysclk_from_parent(name);
++	if (!IS_ERR(clk))
++		return clk;
++
++	sysclk = of_get_child_by_name(clockgen.node, "sysclk");
++	if (sysclk) {
++		clk = sysclk_from_fixed(sysclk, name);
++		if (!IS_ERR(clk))
++			return clk;
++	}
++
++	pr_err("%s: No input clock\n", __func__);
++	return NULL;
++}
++
++/* Legacy node */
++static void __init sysclk_init(struct device_node *node)
++{
++	struct clk *clk;
++
++	legacy_init_clockgen(node);
++
++	clk = clockgen.sysclk;
++	if (clk)
++		of_clk_add_provider(node, of_clk_src_simple_get, clk);
++}
++
++#define PLL_KILL BIT(31)
++
++static void __init create_one_pll(struct clockgen *cg, int idx)
+ {
++	u32 __iomem *reg;
+ 	u32 mult;
+-	int i, rc, count;
+-	const char *clk_name, *parent_name;
+-	struct clk_onecell_data *onecell_data;
+-	struct clk      **subclks;
+-	void __iomem *base;
++	struct clockgen_pll *pll = &cg->pll[idx];
++	int i;
+ 
+-	base = of_iomap(np, 0);
+-	if (!base) {
+-		pr_err("iomap error\n");
++	if (!(cg->info.pll_mask & (1 << idx)))
+ 		return;
+-	}
+ 
+-	/* get the multiple of PLL */
+-	mult = ioread32be(base);
++	if (idx == PLATFORM_PLL)
++		reg = cg->regs + 0xc00;
++	else
++		reg = cg->regs + 0x800 + 0x20 * (idx - 1);
+ 
+-	/* check if this PLL is disabled */
++	/* Get the multiple of PLL */
++	mult = ioread32be(reg);
++
++	/* Check if this PLL is disabled */
+ 	if (mult & PLL_KILL) {
+-		pr_debug("PLL:%s is disabled\n", np->name);
+-		goto err_map;
++		pr_debug("%s(): pll %p disabled\n", __func__, reg);
++		return;
+ 	}
+-	mult = (mult >> 1) & 0x3f;
+ 
+-	parent_name = of_clk_get_parent_name(np, 0);
+-	if (!parent_name) {
+-		pr_err("PLL: %s must have a parent\n", np->name);
+-		goto err_map;
++	if ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)
++		mult = (mult & GENMASK(8, 1)) >> 1;
++	else
++		mult = (mult & GENMASK(6, 1)) >> 1;
++
++	for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
++		struct clk *clk;
++
++		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
++			 "cg-pll%d-div%d", idx, i + 1);
++
++		clk = clk_register_fixed_factor(NULL,
++				pll->div[i].name, "cg-sysclk", 0, mult, i + 1);
++		if (IS_ERR(clk)) {
++			pr_err("%s: %s: register failed %ld\n",
++			       __func__, pll->div[i].name, PTR_ERR(clk));
++			continue;
++		}
++
++		pll->div[i].clk = clk;
+ 	}
++}
++
++static void __init create_plls(struct clockgen *cg)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
++		create_one_pll(cg, i);
++}
+ 
++static void __init legacy_pll_init(struct device_node *np, int idx)
++{
++	struct clockgen_pll *pll;
++	struct clk_onecell_data *onecell_data;
++	struct clk **subclks;
++	int count, rc;
++
++	legacy_init_clockgen(np);
++
++	pll = &clockgen.pll[idx];
+ 	count = of_property_count_strings(np, "clock-output-names");
+-	if (count < 0 || count > 4) {
+-		pr_err("%s: clock is not supported\n", np->name);
+-		goto err_map;
+-	}
+ 
+-	subclks = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
++	BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
++	subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
+ 	if (!subclks)
+-		goto err_map;
++		return;
+ 
+ 	onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
+ 	if (!onecell_data)
+ 		goto err_clks;
+ 
+-	for (i = 0; i < count; i++) {
+-		rc = of_property_read_string_index(np, "clock-output-names",
+-						   i, &clk_name);
+-		if (rc) {
+-			pr_err("%s: could not get clock names\n", np->name);
+-			goto err_cell;
+-		}
+-
+-		/*
+-		 * when count == 4, there are 4 output clocks:
+-		 * /1, /2, /3, /4 respectively
+-		 * when count < 4, there are at least 2 output clocks:
+-		 * /1, /2, (/4, if count == 3) respectively.
+-		 */
+-		if (count == 4)
+-			subclks[i] = clk_register_fixed_factor(NULL, clk_name,
+-					parent_name, 0, mult, 1 + i);
+-		else
+-
+-			subclks[i] = clk_register_fixed_factor(NULL, clk_name,
+-					parent_name, 0, mult, 1 << i);
+-
+-		if (IS_ERR(subclks[i])) {
+-			pr_err("%s: could not register clock\n", clk_name);
+-			goto err_cell;
+-		}
++	if (count <= 3) {
++		subclks[0] = pll->div[0].clk;
++		subclks[1] = pll->div[1].clk;
++		subclks[2] = pll->div[3].clk;
++	} else {
++		subclks[0] = pll->div[0].clk;
++		subclks[1] = pll->div[1].clk;
++		subclks[2] = pll->div[2].clk;
++		subclks[3] = pll->div[3].clk;
+ 	}
+ 
+ 	onecell_data->clks = subclks;
+@@ -233,125 +956,221 @@ static void __init core_pll_init(struct device_node *np)
+ 
+ 	rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
+ 	if (rc) {
+-		pr_err("Could not register clk provider for node:%s\n",
+-		       np->name);
++		pr_err("%s: Couldn't register clk provider for node %s: %d\n",
++		       __func__, np->name, rc);
+ 		goto err_cell;
+ 	}
+ 
+-	iounmap(base);
+ 	return;
+ err_cell:
+ 	kfree(onecell_data);
+ err_clks:
+ 	kfree(subclks);
+-err_map:
+-	iounmap(base);
+ }
+ 
+-static void __init sysclk_init(struct device_node *node)
++/* Legacy node */
++static void __init pltfrm_pll_init(struct device_node *np)
+ {
+-	struct clk *clk;
+-	const char *clk_name = node->name;
+-	struct device_node *np = of_get_parent(node);
+-	u32 rate;
++	legacy_pll_init(np, PLATFORM_PLL);
++}
+ 
+-	if (!np) {
+-		pr_err("could not get parent node\n");
++/* Legacy node */
++static void __init core_pll_init(struct device_node *np)
++{
++	struct resource res;
++	int idx;
++
++	if (of_address_to_resource(np, 0, &res))
+ 		return;
++
++	if ((res.start & 0xfff) == 0xc00) {
++		/*
++		 * ls1021a devtree labels the platform PLL
++		 * with the core PLL compatible
++		 */
++		pltfrm_pll_init(np);
++	} else {
++		idx = (res.start & 0xf0) >> 5;
++		legacy_pll_init(np, CGA_PLL1 + idx);
+ 	}
++}
+ 
+-	if (of_property_read_u32(np, "clock-frequency", &rate)) {
+-		of_node_put(node);
+-		return;
++static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
++{
++	struct clockgen *cg = data;
++	struct clk *clk;
++	struct clockgen_pll *pll;
++	u32 type, idx;
++
++	if (clkspec->args_count < 2) {
++		pr_err("%s: insufficient phandle args\n", __func__);
++		return ERR_PTR(-EINVAL);
+ 	}
+ 
+-	of_property_read_string(np, "clock-output-names", &clk_name);
++	type = clkspec->args[0];
++	idx = clkspec->args[1];
+ 
+-	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
+-	if (!IS_ERR(clk))
+-		of_clk_add_provider(np, of_clk_src_simple_get, clk);
++	switch (type) {
++	case 0:
++		if (idx != 0)
++			goto bad_args;
++		clk = cg->sysclk;
++		break;
++	case 1:
++		if (idx >= ARRAY_SIZE(cg->cmux))
++			goto bad_args;
++		clk = cg->cmux[idx];
++		break;
++	case 2:
++		if (idx >= ARRAY_SIZE(cg->hwaccel))
++			goto bad_args;
++		clk = cg->hwaccel[idx];
++		break;
++	case 3:
++		if (idx >= ARRAY_SIZE(cg->fman))
++			goto bad_args;
++		clk = cg->fman[idx];
++		break;
++	case 4:
++		pll = &cg->pll[PLATFORM_PLL];
++		if (idx >= ARRAY_SIZE(pll->div))
++			goto bad_args;
++		clk = pll->div[idx].clk;
++		break;
++	default:
++		goto bad_args;
++	}
++
++	if (!clk)
++		return ERR_PTR(-ENOENT);
++	return clk;
++
++bad_args:
++	pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
++	return ERR_PTR(-EINVAL);
+ }
+ 
+-static void __init pltfrm_pll_init(struct device_node *np)
++#ifdef CONFIG_PPC
++#include <asm/mpc85xx.h>
++
++static const u32 a4510_svrs[] __initconst = {
++	(SVR_P2040 << 8) | 0x10,	/* P2040 1.0 */
++	(SVR_P2040 << 8) | 0x11,	/* P2040 1.1 */
++	(SVR_P2041 << 8) | 0x10,	/* P2041 1.0 */
++	(SVR_P2041 << 8) | 0x11,	/* P2041 1.1 */
++	(SVR_P3041 << 8) | 0x10,	/* P3041 1.0 */
++	(SVR_P3041 << 8) | 0x11,	/* P3041 1.1 */
++	(SVR_P4040 << 8) | 0x20,	/* P4040 2.0 */
++	(SVR_P4080 << 8) | 0x20,	/* P4080 2.0 */
++	(SVR_P5010 << 8) | 0x10,	/* P5010 1.0 */
++	(SVR_P5010 << 8) | 0x20,	/* P5010 2.0 */
++	(SVR_P5020 << 8) | 0x10,	/* P5020 1.0 */
++	(SVR_P5021 << 8) | 0x10,	/* P5021 1.0 */
++	(SVR_P5040 << 8) | 0x10,	/* P5040 1.0 */
++};
++
++#define SVR_SECURITY	0x80000	/* The Security (E) bit */
++
++static bool __init has_erratum_a4510(void)
+ {
+-	void __iomem *base;
+-	uint32_t mult;
+-	const char *parent_name, *clk_name;
+-	int i, _errno;
+-	struct clk_onecell_data *cod;
+-
+-	base = of_iomap(np, 0);
+-	if (!base) {
+-		pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
+-		return;
++	u32 svr = mfspr(SPRN_SVR);
++	int i;
++
++	svr &= ~SVR_SECURITY;
++
++	for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
++		if (svr == a4510_svrs[i])
++			return true;
+ 	}
+ 
+-	/* Get the multiple of PLL */
+-	mult = ioread32be(base);
++	return false;
++}
++#else
++static bool __init has_erratum_a4510(void)
++{
++	return false;
++}
++#endif
+ 
+-	iounmap(base);
++static void __init clockgen_init(struct device_node *np)
++{
++	int i, ret;
++	bool is_old_ls1021a = false;
+ 
+-	/* Check if this PLL is disabled */
+-	if (mult & PLL_KILL) {
+-		pr_debug("%s(): %s: Disabled\n", __func__, np->name);
++	/* May have already been called by a legacy probe */
++	if (clockgen.node)
+ 		return;
+-	}
+-	mult = (mult & GENMASK(6, 1)) >> 1;
+ 
+-	parent_name = of_clk_get_parent_name(np, 0);
+-	if (!parent_name) {
+-		pr_err("%s(): %s: of_clk_get_parent_name() failed\n",
+-		       __func__, np->name);
++	clockgen.node = np;
++	clockgen.regs = of_iomap(np, 0);
++	if (!clockgen.regs &&
++	    of_device_is_compatible(of_root, "fsl,ls1021a")) {
++		/* Compatibility hack for old, broken device trees */
++		clockgen.regs = ioremap(0x1ee1000, 0x1000);
++		is_old_ls1021a = true;
++	}
++	if (!clockgen.regs) {
++		pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
+ 		return;
+ 	}
+ 
+-	i = of_property_count_strings(np, "clock-output-names");
+-	if (i < 0) {
+-		pr_err("%s(): %s: of_property_count_strings(clock-output-names) = %d\n",
+-		       __func__, np->name, i);
+-		return;
++	for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
++		if (of_device_is_compatible(np, chipinfo[i].compat))
++			break;
++		if (is_old_ls1021a &&
++		    !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
++			break;
+ 	}
+ 
+-	cod = kmalloc(sizeof(*cod) + i * sizeof(struct clk *), GFP_KERNEL);
+-	if (!cod)
+-		return;
+-	cod->clks = (struct clk **)(cod + 1);
+-	cod->clk_num = i;
+-
+-	for (i = 0; i < cod->clk_num; i++) {
+-		_errno = of_property_read_string_index(np, "clock-output-names",
+-						       i, &clk_name);
+-		if (_errno < 0) {
+-			pr_err("%s(): %s: of_property_read_string_index(clock-output-names) = %d\n",
+-			       __func__, np->name, _errno);
+-			goto return_clk_unregister;
+-		}
++	if (i == ARRAY_SIZE(chipinfo)) {
++		pr_err("%s: unknown clockgen node %s\n", __func__,
++		       np->full_name);
++		goto err;
++	}
++	clockgen.info = chipinfo[i];
++
++	if (clockgen.info.guts_compat) {
++		struct device_node *guts;
+ 
+-		cod->clks[i] = clk_register_fixed_factor(NULL, clk_name,
+-					       parent_name, 0, mult, 1 + i);
+-		if (IS_ERR(cod->clks[i])) {
+-			pr_err("%s(): %s: clk_register_fixed_factor(%s) = %ld\n",
+-			       __func__, np->name,
+-			       clk_name, PTR_ERR(cod->clks[i]));
+-			goto return_clk_unregister;
++		guts = of_find_compatible_node(NULL, NULL,
++					       clockgen.info.guts_compat);
++		if (guts) {
++			clockgen.guts = of_iomap(guts, 0);
++			if (!clockgen.guts) {
++				pr_err("%s: Couldn't map %s regs\n", __func__,
++				       guts->full_name);
++			}
+ 		}
++
+ 	}
+ 
+-	_errno = of_clk_add_provider(np, of_clk_src_onecell_get, cod);
+-	if (_errno < 0) {
+-		pr_err("%s(): %s: of_clk_add_provider() = %d\n",
+-		       __func__, np->name, _errno);
+-		goto return_clk_unregister;
++	if (has_erratum_a4510())
++		clockgen.info.flags |= CG_CMUX_GE_PLAT;
++
++	clockgen.sysclk = create_sysclk("cg-sysclk");
++	create_plls(&clockgen);
++	create_muxes(&clockgen);
++
++	if (clockgen.info.init_periph)
++		clockgen.info.init_periph(&clockgen);
++
++	ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
++	if (ret) {
++		pr_err("%s: Couldn't register clk provider for node %s: %d\n",
++		       __func__, np->name, ret);
+ 	}
+ 
+ 	return;
+-
+-return_clk_unregister:
+-	while (--i >= 0)
+-		clk_unregister(cod->clks[i]);
+-	kfree(cod);
++err:
++	iounmap(clockgen.regs);
++	clockgen.regs = NULL;
+ }
+ 
++CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
++
++/* Legacy nodes */
+ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
+ CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
+ CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0006-clk-qoriq-Add-ls2080a-support.patch b/target/linux/layerscape-64b/patches-4.1/0006-clk-qoriq-Add-ls2080a-support.patch
new file mode 100644
index 0000000..5081a0c
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0006-clk-qoriq-Add-ls2080a-support.patch
@@ -0,0 +1,181 @@
+From c6a404c4471e7eeb25f3eb51b6327a2f3a5639e0 Mon Sep 17 00:00:00 2001
+From: Scott Wood <scottwood at freescale.com>
+Date: Fri, 15 Jan 2016 07:34:26 +0000
+Subject: [PATCH 006/151] clk: qoriq: Add ls2080a support.
+
+LS2080A is the first implementation of the chassis 3 clockgen, which
+has a different register layout than previous chips.  It is also little
+endian, unlike previous chips.
+
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+Acked-by: Stephen Boyd <sboyd at codeaurora.org>
+(cherry picked from commit 9e19ca2f627e5a6ee7425c48cc30b7356995b691)
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+---
+ drivers/clk/Kconfig     |  2 +-
+ drivers/clk/clk-qoriq.c | 77 +++++++++++++++++++++++++++++++++++++++++++------
+ 2 files changed, 69 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index 9897f35..0f7a0a1 100644
+--- a/drivers/clk/Kconfig
++++ b/drivers/clk/Kconfig
+@@ -104,7 +104,7 @@ config COMMON_CLK_AXI_CLKGEN
+ 
+ config CLK_QORIQ
+ 	bool "Clock driver for Freescale QorIQ platforms"
+-	depends on (PPC_E500MC || ARM) && OF
++	depends on (PPC_E500MC || ARM || ARM64) && OF
+ 	---help---
+ 	  This adds the clock driver support for Freescale QorIQ platforms
+ 	  using common clock framework.
+diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
+index 06281a3..8f9c93b 100644
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -68,7 +68,10 @@ struct clockgen;
+  * If not set, cmux freq must be >= platform pll/2
+  */
+ #define CG_CMUX_GE_PLAT		1
++
+ #define CG_PLL_8BIT		2	/* PLLCnGSR[CFG] is 8 bits, not 6 */
++#define CG_VER3			4	/* version 3 cg: reg layout different */
++#define CG_LITTLE_ENDIAN	8
+ 
+ struct clockgen_chipinfo {
+ 	const char *compat, *guts_compat;
+@@ -94,6 +97,26 @@ struct clockgen {
+ 
+ static struct clockgen clockgen;
+ 
++static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
++{
++	if (cg->info.flags & CG_LITTLE_ENDIAN)
++		iowrite32(val, reg);
++	else
++		iowrite32be(val, reg);
++}
++
++static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
++{
++	u32 val;
++
++	if (cg->info.flags & CG_LITTLE_ENDIAN)
++		val = ioread32(reg);
++	else
++		val = ioread32be(reg);
++
++	return val;
++}
++
+ static const struct clockgen_muxinfo p2041_cmux_grp1 = {
+ 	{
+ 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+@@ -429,6 +452,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
+ 		.pll_mask = 0x03,
+ 	},
+ 	{
++		.compat = "fsl,ls2080a-clockgen",
++		.cmux_groups = {
++			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
++		},
++		.cmux_to_group = {
++			0, 0, 1, 1, -1
++		},
++		.pll_mask = 0x37,
++		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
++	},
++	{
+ 		.compat = "fsl,p2041-clockgen",
+ 		.guts_compat = "fsl,qoriq-device-config-1.0",
+ 		.init_periph = p2041_init_periph,
+@@ -575,7 +609,7 @@ static int mux_set_parent(struct clk_hw *hw, u8 idx)
+ 		return -EINVAL;
+ 
+ 	clksel = hwc->parent_to_clksel[idx];
+-	iowrite32be((clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
++	cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
+ 
+ 	return 0;
+ }
+@@ -586,7 +620,7 @@ static u8 mux_get_parent(struct clk_hw *hw)
+ 	u32 clksel;
+ 	s8 ret;
+ 
+-	clksel = (ioread32be(hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
++	clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
+ 
+ 	ret = hwc->clksel_to_parent[clksel];
+ 	if (ret < 0) {
+@@ -705,7 +739,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
+ 	 * default clksel) may be inappropriately excluded on certain
+ 	 * chips.
+ 	 */
+-	clksel = (ioread32be(hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
++	clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
+ 	div = get_pll_div(cg, hwc, clksel);
+ 	if (!div)
+ 		return NULL;
+@@ -874,13 +908,36 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
+ 	if (!(cg->info.pll_mask & (1 << idx)))
+ 		return;
+ 
+-	if (idx == PLATFORM_PLL)
+-		reg = cg->regs + 0xc00;
+-	else
+-		reg = cg->regs + 0x800 + 0x20 * (idx - 1);
++	if (cg->info.flags & CG_VER3) {
++		switch (idx) {
++		case PLATFORM_PLL:
++			reg = cg->regs + 0x60080;
++			break;
++		case CGA_PLL1:
++			reg = cg->regs + 0x80;
++			break;
++		case CGA_PLL2:
++			reg = cg->regs + 0xa0;
++			break;
++		case CGB_PLL1:
++			reg = cg->regs + 0x10080;
++			break;
++		case CGB_PLL2:
++			reg = cg->regs + 0x100a0;
++			break;
++		default:
++			WARN_ONCE(1, "index %d\n", idx);
++			return;
++		}
++	} else {
++		if (idx == PLATFORM_PLL)
++			reg = cg->regs + 0xc00;
++		else
++			reg = cg->regs + 0x800 + 0x20 * (idx - 1);
++	}
+ 
+ 	/* Get the multiple of PLL */
+-	mult = ioread32be(reg);
++	mult = cg_in(cg, reg);
+ 
+ 	/* Check if this PLL is disabled */
+ 	if (mult & PLL_KILL) {
+@@ -888,7 +945,8 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
+ 		return;
+ 	}
+ 
+-	if ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)
++	if ((cg->info.flags & CG_VER3) ||
++	    ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
+ 		mult = (mult & GENMASK(8, 1)) >> 1;
+ 	else
+ 		mult = (mult & GENMASK(6, 1)) >> 1;
+@@ -1169,6 +1227,7 @@ err:
+ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+ 
+ /* Legacy nodes */
+ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0007-clk-qoriq-Add-ls1043a-support.patch b/target/linux/layerscape-64b/patches-4.1/0007-clk-qoriq-Add-ls1043a-support.patch
new file mode 100644
index 0000000..fedf3cb
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0007-clk-qoriq-Add-ls1043a-support.patch
@@ -0,0 +1,80 @@
+From b1399d9751ac9e6cc6f9daf185fc2caaeb2cca77 Mon Sep 17 00:00:00 2001
+From: Hou Zhiqiang <B48286 at freescale.com>
+Date: Fri, 15 Jan 2016 07:34:28 +0000
+Subject: [PATCH 007/151] clk: qoriq: Add ls1043a support.
+
+Signed-off-by: Hou Zhiqiang <B48286 at freescale.com>
+Acked-by: Stephen Boyd <sboyd at codeaurora.org>
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+(cherry picked from commit e994412c5f19402a834f4b0d95e9159d1c7b0fb8)
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+---
+ drivers/clk/clk-qoriq.c | 38 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
+index 8f9c93b..b189688 100644
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -244,6 +244,28 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
+ 	},
+ };
+ 
++static const struct clockgen_muxinfo ls1043a_hwa1 = {
++	{
++		{},
++		{},
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
++		{},
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++	},
++};
++
++static const struct clockgen_muxinfo ls1043a_hwa2 = {
++	{
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++	},
++};
++
+ static const struct clockgen_muxinfo t1023_hwa1 = {
+ 	{
+ 		{},
+@@ -452,6 +474,21 @@ static const struct clockgen_chipinfo chipinfo[] = {
+ 		.pll_mask = 0x03,
+ 	},
+ 	{
++		.compat = "fsl,ls1043a-clockgen",
++		.init_periph = t2080_init_periph,
++		.cmux_groups = {
++			&t1040_cmux
++		},
++		.hwaccel = {
++			&ls1043a_hwa1, &ls1043a_hwa2
++		},
++		.cmux_to_group = {
++			0, -1
++		},
++		.pll_mask = 0x07,
++		.flags = CG_PLL_8BIT,
++	},
++	{
+ 		.compat = "fsl,ls2080a-clockgen",
+ 		.cmux_groups = {
+ 			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+@@ -1227,6 +1264,7 @@ err:
+ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+ 
+ /* Legacy nodes */
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0008-clk-qoriq-fix-memory-leak.patch b/target/linux/layerscape-64b/patches-4.1/0008-clk-qoriq-fix-memory-leak.patch
new file mode 100644
index 0000000..bfdcbb9
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0008-clk-qoriq-fix-memory-leak.patch
@@ -0,0 +1,36 @@
+From d95e65cb2998c6e066e3bf62d0b8ac546f0afa90 Mon Sep 17 00:00:00 2001
+From: Sudip Mukherjee <sudipm.mukherjee at gmail.com>
+Date: Fri, 15 Jan 2016 07:34:29 +0000
+Subject: [PATCH 008/151] clk: qoriq: fix memory leak
+
+If get_pll_div() fails we exited by returning NULL but we missed
+releasing hwc.
+
+Signed-off-by: Sudip Mukherjee <sudip at vectorindia.org>
+Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver")
+Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
+(cherry picked from commit 279104e3ade92b38198fdaead9e84bd80057693a)
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+---
+ drivers/clk/clk-qoriq.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
+index b189688..f8739d0 100644
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -778,8 +778,10 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
+ 	 */
+ 	clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
+ 	div = get_pll_div(cg, hwc, clksel);
+-	if (!div)
++	if (!div) {
++		kfree(hwc);
+ 		return NULL;
++	}
+ 
+ 	pct80_rate = clk_get_rate(div->clk);
+ 	pct80_rate *= 8;
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0009-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch b/target/linux/layerscape-64b/patches-4.1/0009-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch
new file mode 100644
index 0000000..3dbaa0f
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0009-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch
@@ -0,0 +1,754 @@
+From 0e60f48b37d3979674cd01e3a2d461c4e1a9301a Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie at freescale.com>
+Date: Thu, 21 Jan 2016 11:27:15 +0800
+Subject: [PATCH 009/151] dts: ls1043a: add fman/bman/qman/ethernet nodes
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi     | 461 +++++++++++++++++++++
+ .../boot/dts/freescale/qoriq-bman1-portals.dtsi    | 104 +++++
+ .../boot/dts/freescale/qoriq-qman1-portals.dtsi    | 136 ++++++
+ 3 files changed, 701 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+index cb00a84..5654173 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -50,6 +50,16 @@
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
++	aliases {
++		ethernet0 = &fm1mac1;
++		ethernet1 = &fm1mac2;
++		ethernet2 = &fm1mac3;
++		ethernet3 = &fm1mac4;
++		ethernet4 = &fm1mac5;
++		ethernet5 = &fm1mac6;
++		ethernet6 = &fm1mac9;
++	};
++
+ 	cpus {
+ 		#address-cells = <2>;
+ 		#size-cells = <0>;
+@@ -174,6 +184,323 @@
+ 			bus-width = <4>;
+ 		};
+ 
++		qman: qman at 1880000 {
++			compatible = "fsl,qman";
++			reg = <0x00 0x1880000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++		};
++
++		bman: bman at 1890000 {
++			compatible = "fsl,bman";
++			reg = <0x00 0x1890000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++		};
++
++		fman0: fman at 1a00000 {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			cell-index = <0>;
++			compatible = "fsl,fman", "simple-bus";
++			ranges = <0x0 0x00 0x1a00000 0x100000>;
++			reg = <0x00 0x1a00000 0x0 0x100000>;
++			clock-frequency = <0>;
++			interrupts = <0 44 0x4>,
++				     <0 45 0x4>;
++
++			cc {
++				compatible = "fsl,fman-cc";
++			};
++
++			muram at 0 {
++				compatible = "fsl,fman-muram";
++				reg = <0x0 0x60000>;
++			};
++
++			bmi at 80000 {
++				compatible = "fsl,fman-bmi";
++				reg = <0x80000 0x400>;
++			};
++
++			qmi at 80400 {
++				compatible = "fsl,fman-qmi";
++				reg = <0x80400 0x400>;
++			};
++
++			fman0_oh1: port at 82000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x82000 0x1000>;
++			};
++
++			fman0_oh2: port at 83000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x83000 0x1000>;
++			};
++
++			fman0_oh3: port at 84000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x84000 0x1000>;
++			};
++
++			fman0_oh4: port at 85000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x85000 0x1000>;
++			};
++
++			fman0_oh5: port at 86000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x86000 0x1000>;
++			};
++
++			fman0_oh6: port at 87000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x87000 0x1000>;
++			};
++
++			policer at c0000 {
++				compatible = "fsl,fman-policer";
++				reg = <0xc0000 0x1000>;
++			};
++
++			keygen at c1000 {
++				compatible = "fsl,fman-keygen";
++				reg = <0xc1000 0x1000>;
++			};
++
++			dma at c2000 {
++				compatible = "fsl,fman-dma";
++				reg = <0xc2000 0x1000>;
++			};
++
++			fpm at c3000 {
++				compatible = "fsl,fman-fpm";
++				reg = <0xc3000 0x1000>;
++			};
++
++			parser at c7000 {
++				compatible = "fsl,fman-parser";
++				reg = <0xc7000 0x1000>;
++			};
++
++			vsps at dc000 {
++				compatible = "fsl,fman-vsps";
++				reg = <0xdc000 0x1000>;
++			};
++
++			mdio0: mdio at fc000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xfc000 0x1000>;
++			};
++
++			xmdio0: mdio at fd000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xfd000 0x1000>;
++			};
++
++			fman0_rx0: port at 88000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x88000 0x1000>;
++			};
++
++			fman0_tx0: port at a8000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xa8000 0x1000>;
++			};
++
++			fm1mac1: ethernet at e0000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe0000 0x1000>;
++				fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio at e1000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe1000 0x1000>;
++			};
++
++			fman0_rx1: port at 89000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x89000 0x1000>;
++			};
++
++			fman0_tx1: port at a9000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xa9000 0x1000>;
++			};
++
++			fm1mac2: ethernet at e2000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe2000 0x1000>;
++				fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio at e3000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe3000 0x1000>;
++			};
++
++			fman0_rx2: port at 8a000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8a000 0x1000>;
++			};
++
++			fman0_tx2: port at aa000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xaa000 0x1000>;
++			};
++
++			fm1mac3: ethernet at e4000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe4000 0x1000>;
++				fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio at e5000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe5000 0x1000>;
++			};
++
++			fman0_rx3: port at 8b000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8b000 0x1000>;
++			};
++
++			fman0_tx3: port at ab000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xab000 0x1000>;
++			};
++
++			fm1mac4: ethernet at e6000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe6000 0x1000>;
++				fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio at e7000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe7000 0x1000>;
++			};
++
++			fman0_rx4: port at 8c000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8c000 0x1000>;
++			};
++
++			fman0_tx4: port at ac000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xac000 0x1000>;
++			};
++
++			fm1mac5: ethernet at e8000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe8000 0x1000>;
++				fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio at e9000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe9000 0x1000>;
++			};
++
++			fman0_rx5: port at 8d000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8d000 0x1000>;
++			};
++
++			fman0_tx5: port at ad000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xad000 0x1000>;
++			};
++
++			fm1mac6: ethernet at ea000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-memac";
++				reg = <0xea000 0x1000>;
++				fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio at eb000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xeb000 0x1000>;
++			};
++
++			fman0_10g_rx0: port at 90000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-10g-rx";
++				reg = <0x90000 0x1000>;
++			};
++
++			fman0_10g_tx0: port at b0000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-10g-tx";
++				reg = <0xb0000 0x1000>;
++				fsl,qman-channel-id = <0x800>;
++			};
++
++			fm1mac9: ethernet at f0000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-memac";
++				reg = <0xf0000 0x1000>;
++				fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
++			};
++
++			mdio at f1000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xf1000 0x1000>;
++			};
++
++			ptp_timer0: rtc at fe000 {
++				compatible = "fsl,fman-rtc";
++				reg = <0xfe000 0x1000>;
++			};
++		};
++
+ 		dspi0: dspi at 2100000 {
+ 			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ 			#address-cells = <1>;
+@@ -522,4 +849,138 @@
+ 		};
+ 	};
+ 
++	fsl,dpaa {
++		compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
++		ethernet at 0 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac1>;
++		};
++		ethernet at 1 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac2>;
++		};
++		ethernet at 2 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac3>;
++		};
++		ethernet at 3 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac4>;
++		};
++		ethernet at 4 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac5>;
++		};
++		ethernet at 5 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac6>;
++		};
++		ethernet at 8 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac9>;
++		};
++	};
++
++	qportals: qman-portals at 500000000 {
++		   ranges = <0x0 0x5 0x00000000 0x8000000>;
++        };
++	bportals: bman-portals at 508000000 {
++		   ranges = <0x0 0x5 0x08000000 0x8000000>;
++        };
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		bman_fbpr: bman-fbpr {
++			size = <0 0x1000000>;
++			alignment = <0 0x1000000>;
++		};
++		qman_fqd: qman-fqd {
++			size = <0 0x400000>;
++			alignment = <0 0x400000>;
++		};
++		qman_pfdr: qman-pfdr {
++			size = <0 0x2000000>;
++			alignment = <0 0x2000000>;
++		};
++	};
+ };
++
++&fman0 {
++	/* offline - 1 */
++	port at 82000 {
++		fsl,qman-channel-id = <0x809>;
++	};
++
++	/* tx - 10g - 2 */
++	port at a8000 {
++		fsl,qman-channel-id = <0x802>;
++	};
++	/* tx - 10g - 3 */
++	port at a9000 {
++		fsl,qman-channel-id = <0x803>;
++	};
++	/* tx - 1g - 2 */
++	port at aa000 {
++		fsl,qman-channel-id = <0x804>;
++	};
++	/* tx - 1g - 3 */
++	port at ab000 {
++		fsl,qman-channel-id = <0x805>;
++	};
++	/* tx - 1g - 4 */
++	port at ac000 {
++		fsl,qman-channel-id = <0x806>;
++	};
++	/* tx - 1g - 5 */
++	port at ad000 {
++		fsl,qman-channel-id = <0x807>;
++	};
++	/* tx - 10g - 0 */
++	port at b0000 {
++		fsl,qman-channel-id = <0x800>;
++	};
++	/* tx - 10g - 1 */
++	port at b1000 {
++		fsl,qman-channel-id = <0x801>;
++	};
++	/* offline - 2 */
++	port at 83000 {
++		fsl,qman-channel-id = <0x80a>;
++	};
++	/* offline - 3 */
++	port at 84000 {
++		fsl,qman-channel-id = <0x80b>;
++	};
++	/* offline - 4 */
++	port at 85000 {
++		fsl,qman-channel-id = <0x80c>;
++	};
++	/* offline - 5 */
++	port at 86000 {
++		fsl,qman-channel-id = <0x80d>;
++	};
++	/* offline - 6 */
++	port at 87000 {
++		fsl,qman-channel-id = <0x80e>;
++	};
++};
++
++&bman_fbpr {
++	compatible = "fsl,bman-fbpr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&qman_fqd {
++	compatible = "fsl,qman-fqd";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&qman_pfdr {
++	compatible = "fsl,qman-pfdr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++/include/ "qoriq-qman1-portals.dtsi"
++/include/ "qoriq-bman1-portals.dtsi"
+diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
+new file mode 100644
+index 0000000..b733ff0
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
+@@ -0,0 +1,104 @@
++/*
++ * QorIQ BMan Portal device tree stub for 10 portals
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++&bportals {
++	  #address-cells = <1>;
++	  #size-cells = <1>;
++	  compatible = "simple-bus";
++	  bportal0: bman-portal at 0 {
++		cell-index = <0>;
++		compatible = "fsl,bman-portal";
++		reg = <0x0 0x4000 0x4000000 0x4000>;
++		interrupts = <0 173 0x4>;
++	};
++	bportal1: bman-portal at 10000 {
++		cell-index = <1>;
++		compatible = "fsl,bman-portal";
++		reg = <0x10000 0x4000 0x4010000 0x4000>;
++		interrupts = <0 175 0x4>;
++	};
++	bportal2: bman-portal at 20000 {
++		cell-index = <2>;
++		compatible = "fsl,bman-portal";
++		reg = <0x20000 0x4000 0x4020000 0x4000>;
++		interrupts = <0 177 0x4>;
++	};
++	bportal3: bman-portal at 30000 {
++		cell-index = <3>;
++		compatible = "fsl,bman-portal";
++		reg = <0x30000 0x4000 0x4030000 0x4000>;
++		interrupts = <0 179 0x4>;
++	};
++	bportal4: bman-portal at 40000 {
++		cell-index = <4>;
++		compatible = "fsl,bman-portal";
++		reg = <0x40000 0x4000 0x4040000 0x4000>;
++		interrupts = <0 181 0x4>;
++		};
++	bportal5: bman-portal at 50000 {
++		cell-index = <5>;
++		compatible = "fsl,bman-portal";
++		reg = <0x50000 0x4000 0x4050000 0x4000>;
++		interrupts = <0 183 0x4>;
++	};
++	bportal6: bman-portal at 60000 {
++		cell-index = <6>;
++		compatible = "fsl,bman-portal";
++		reg = <0x60000 0x4000 0x4060000 0x4000>;
++		interrupts = <0 185 0x4>;
++	};
++	bportal7: bman-portal at 70000 {
++		cell-index = <7>;
++		compatible = "fsl,bman-portal";
++		reg = <0x70000 0x4000 0x4070000 0x4000>;
++		interrupts = <0 187 0x4>;
++	};
++	bportal8: bman-portal at 80000 {
++		cell-index = <8>;
++		compatible = "fsl,bman-portal";
++		reg = <0x80000 0x4000 0x4080000 0x4000>;
++		interrupts = <0 189 0x4>;
++	};
++/*	bportal9: bman-portal at 90000 {
++		cell-index = <9>;
++		compatible = "fsl,bman-portal";
++		reg = <0x90000 0x4000 0x4090000 0x4000>;
++		interrupts = <0 191 0x4>;
++	}; */
++	 bman-bpids at 0 {
++                compatible = "fsl,bpid-range";
++                fsl,bpid-range = <32 32>;
++        };
++
++};
+diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+new file mode 100644
+index 0000000..f01b58b
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+@@ -0,0 +1,136 @@
++/*
++ * QorIQ QMan Portal device tree stub for 10 portals & 15 pool channels
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++&qportals {
++
++	  #address-cells = <1>;
++	  #size-cells = <1>;
++	  compatible = "simple-bus";
++	  qportal0: qman-portal at 0 {
++		cell-index = <0>;
++		compatible = "fsl,qman-portal";
++		reg = <0x0 0x4000 0x4000000 0x4000>;
++		interrupts = <0 172 0x4>;
++		fsl,qman-channel-id = <0x0>;
++	};
++
++	qportal1: qman-portal at 10000 {
++		  cell-index = <1>;
++		  compatible = "fsl,qman-portal";
++		  reg = <0x10000 0x4000 0x4010000 0x4000>;
++		  interrupts = <0 174 0x4>;
++		  fsl,qman-channel-id = <1>;
++	};
++
++	qportal2: qman-portal at 20000 {
++		  cell-index = <2>;
++		  compatible = "fsl,qman-portal";
++		  reg = <0x20000 0x4000 0x4020000 0x4000>;
++		  interrupts = <0 176 0x4>;
++		  fsl,qman-channel-id = <2>;
++	};
++
++	qportal3: qman-portal at 30000 {
++		  cell-index = <3>;
++		  compatible = "fsl,qman-portal";
++		  reg = <0x30000 0x4000 0x4030000 0x4000>;
++		  interrupts = <0 178 0x4>;
++		  fsl,qman-channel-id = <3>;
++	};
++
++	qportal4: qman-portal at 40000 {
++		  cell-index = <4>;
++		  compatible = "fsl,qman-portal";
++		  reg = <0x40000 0x4000 0x4040000 0x4000>;
++		  interrupts = <0 180 0x4>;
++		  fsl,qman-channel-id = <4>;
++	};
++
++	qportal5: qman-portal at 50000 {
++		  cell-index = <5>;
++		  compatible = "fsl,qman-portal";
++		  reg = <0x50000 0x4000 0x4050000 0x4000>;
++		  interrupts = <0 182 0x4>;
++		  fsl,qman-channel-id = <5>;
++	};
++
++	qportal6: qman-portal at 60000 {
++		  cell-index = <6>;
++		  compatible = "fsl,qman-portal";
++		  reg = <0x60000 0x4000 0x4060000 0x4000>;
++		  interrupts = <0 184 0x4>;
++		  fsl,qman-channel-id = <6>;
++	};
++
++	qportal7: qman-portal at 70000 {
++		  cell-index = <7>;
++		  compatible = "fsl,qman-portal";
++		  reg = <0x70000 0x4000 0x4070000 0x4000>;
++		  interrupts = <0 186 0x4>;
++		  fsl,qman-channel-id = <7>;
++	};
++
++	qportal8: qman-portal at 80000 {
++		cell-index = <8>;
++		compatible = "fsl,qman-portal";
++		reg = <0x80000 0x4000 0x4080000 0x4000>;
++		interrupts = <0 188 0x4>;
++		fsl,qman-channel-id = <8>;
++	};
++
++/*	qportal9: qman-portal at 90000 {
++		cell-index = <9>;
++		compatible = "fsl,qman-portal";
++		reg = <0x90000 0x4000 0x4090000 0x4000>;
++		interrupts = <0 190 0x4>;
++		fsl,qman-channel-id = <9>;
++	}; */
++
++	qman-fqids at 0 {
++                compatible = "fsl,fqid-range";
++                fsl,fqid-range = <256 256>;
++        };
++        qman-fqids at 1 {
++                compatible = "fsl,fqid-range";
++                fsl,fqid-range = <32768 32768>;
++        };
++        qman-pools at 0 {
++                compatible = "fsl,pool-channel-range";
++                fsl,pool-channel-range = <0x401 0xf>;
++        };
++        qman-cgrids at 0 {
++                compatible = "fsl,cgrid-range";
++                fsl,cgrid-range = <0 256>;
++        };
++
++};
+\ No newline at end of file
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0010-dts-ls1043ardb-add-mdio-phy-nodes.patch b/target/linux/layerscape-64b/patches-4.1/0010-dts-ls1043ardb-add-mdio-phy-nodes.patch
new file mode 100644
index 0000000..ea90a2e
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0010-dts-ls1043ardb-add-mdio-phy-nodes.patch
@@ -0,0 +1,86 @@
+From 923a43e7e2180ea46e4e4088560f763d39006c07 Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie at freescale.com>
+Date: Thu, 21 Jan 2016 11:29:22 +0800
+Subject: [PATCH 010/151] dts: ls1043ardb: add mdio & phy nodes
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 65 +++++++++++++++++++++++
+ 1 file changed, 65 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+index c95a0e7..bba79bf 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -115,3 +115,68 @@
+ &duart1 {
+ 	status = "okay";
+ };
++
++&fman0 {
++	ethernet at e0000 {
++		phy-handle = <&qsgmii_phy1>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet at e2000 {
++		phy-handle = <&qsgmii_phy2>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet at e4000 {
++		phy-handle = <&rgmii_phy1>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet at e6000 {
++		phy-handle = <&rgmii_phy2>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet at e8000 {
++		phy-handle = <&qsgmii_phy3>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet at ea000 {
++		phy-handle = <&qsgmii_phy4>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet at f0000 { /* 10GEC1 */
++		phy-handle = <&aqr105_phy>;
++		phy-connection-type = "xgmii";
++	};
++
++	mdio at fc000 {
++		rgmii_phy1: ethernet-phy at 1 {
++			reg = <0x1>;
++		};
++		rgmii_phy2: ethernet-phy at 2 {
++			reg = <0x2>;
++		};
++		qsgmii_phy1: ethernet-phy at 3 {
++			reg = <0x4>;
++		};
++		qsgmii_phy2: ethernet-phy at 4 {
++			reg = <0x5>;
++		};
++		qsgmii_phy3: ethernet-phy at 5 {
++			reg = <0x6>;
++		};
++		qsgmii_phy4: ethernet-phy at 6 {
++			reg = <0x7>;
++		};
++	};
++
++	mdio at fd000 {
++		aqr105_phy: ethernet-phy at c {
++			compatible = "ethernet-phy-ieee802.3-c45";
++			reg = <0x1>;
++		};
++	};
++};
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0011-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch b/target/linux/layerscape-64b/patches-4.1/0011-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch
new file mode 100644
index 0000000..549a669
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0011-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch
@@ -0,0 +1,86 @@
+From 81fc89888a98d76369b88506d45fc5f0ecb3e030 Mon Sep 17 00:00:00 2001
+From: Zhao Qiang <B45475 at freescale.com>
+Date: Fri, 10 Oct 2014 10:38:48 +0800
+Subject: [PATCH 011/151] arch: arm: add ARM specific fucntions required for
+ ehci fsl driver
+
+Add below functions for ARM platform which are used by ehci fsl driver:
+1. spin_event_timeout function
+2. set/clear bits functions
+
+Signed-off-by: Zhao Qiang <B45475 at freescale.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
+---
+ arch/arm/include/asm/delay.h | 16 ++++++++++++++++
+ arch/arm/include/asm/io.h    | 28 ++++++++++++++++++++++++++++
+ 2 files changed, 44 insertions(+)
+
+diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
+index dff714d..a932f99 100644
+--- a/arch/arm/include/asm/delay.h
++++ b/arch/arm/include/asm/delay.h
+@@ -57,6 +57,22 @@ extern void __bad_udelay(void);
+ 			__const_udelay((n) * UDELAY_MULT)) :		\
+ 	  __udelay(n))
+ 
++#define spin_event_timeout(condition, timeout, delay)                          \
++({                                                                             \
++	typeof(condition) __ret;                                               \
++	int i = 0;							       \
++	while (!(__ret = (condition)) && (i++ < timeout)) {		       \
++		if (delay)                                                     \
++			udelay(delay);                                         \
++		else                                                           \
++			cpu_relax();					       \
++		udelay(1);						       \
++	}								       \
++	if (!__ret)                                                            \
++		__ret = (condition);                                           \
++	__ret;		                                                       \
++})
++
+ /* Loop-based definitions for assembly code. */
+ extern void __loop_delay(unsigned long loops);
+ extern void __loop_udelay(unsigned long usecs);
+diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
+index db58deb..e242160 100644
+--- a/arch/arm/include/asm/io.h
++++ b/arch/arm/include/asm/io.h
+@@ -227,6 +227,34 @@ extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
+ #endif
+ #endif
+ 
++/* access ports */
++#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
++#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
++
++#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
++#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
++
++#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
++#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
++
++/* Clear and set bits in one shot.  These macros can be used to clear and
++ * set multiple bits in a register using a single read-modify-write.  These
++ * macros can also be used to set a multiple-bit bit pattern using a mask,
++ * by specifying the mask in the 'clear' parameter and the new bit pattern
++ * in the 'set' parameter.
++ */
++
++#define clrsetbits_be32(addr, clear, set) \
++	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le32(addr, clear, set) \
++	iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_be16(addr, clear, set) \
++	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le16(addr, clear, set) \
++	iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_8(addr, clear, set) \
++	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
++
+ /*
+  *  IO port access primitives
+  *  -------------------------
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0012-USB-Gadget-fsl-add-a-sanity-check-for-complete-handl.patch b/target/linux/layerscape-64b/patches-4.1/0012-USB-Gadget-fsl-add-a-sanity-check-for-complete-handl.patch
new file mode 100644
index 0000000..384b3af
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0012-USB-Gadget-fsl-add-a-sanity-check-for-complete-handl.patch
@@ -0,0 +1,36 @@
+From 6ddf7073e8dbae0827b33b863df65b86f9b03ece Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat at freescale.com>
+Date: Mon, 25 Jan 2016 16:11:46 +0530
+Subject: [PATCH 012/151] USB : Gadget : fsl: add a sanity check for complete
+ handler
+
+complete handler is replaced by usb_gadget_giveback_request by below commit,
+which removed the sanity check which was added for fsl specific gadget driver.
+usb: gadget: Refactor request completion (304f7e5e1d08fa2f5674c1323bd0ebd806c86b81).
+
+Above change is causing crash in fsl gadget driver, Hence adding the check back.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
+---
+ drivers/usb/gadget/udc/fsl_udc_core.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c b/drivers/usb/gadget/udc/fsl_udc_core.c
+index c60022b..75ddf1a 100644
+--- a/drivers/usb/gadget/udc/fsl_udc_core.c
++++ b/drivers/usb/gadget/udc/fsl_udc_core.c
+@@ -198,7 +198,10 @@ __acquires(ep->udc->lock)
+ 
+ 	spin_unlock(&ep->udc->lock);
+ 
+-	usb_gadget_giveback_request(&ep->ep, &req->req);
++	/* this complete() should a func implemented by gadget layer,
++	* eg fsg->bulk_in_complete() */
++	if (req->req.complete)
++		usb_gadget_giveback_request(&ep->ep, &req->req);
+ 
+ 	spin_lock(&ep->udc->lock);
+ 	ep->stopped = stopped;
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0013-usb-kconfig-remove-dependency-FSL_SOC-for-ehci-fsl-d.patch b/target/linux/layerscape-64b/patches-4.1/0013-usb-kconfig-remove-dependency-FSL_SOC-for-ehci-fsl-d.patch
new file mode 100644
index 0000000..f3f18cc
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0013-usb-kconfig-remove-dependency-FSL_SOC-for-ehci-fsl-d.patch
@@ -0,0 +1,30 @@
+From 3ad386c4e2386a85052edca9dfd261e122a2b026 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat at freescale.com>
+Date: Thu, 14 Jan 2016 10:58:59 +0530
+Subject: [PATCH 013/151] usb: kconfig: remove dependency FSL_SOC for ehci fsl
+ driver
+
+CONFIG_USB_EHCI_FSL is not dependent on FSL_SOC, it can be built on
+non-PPC platforms.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
+---
+ drivers/usb/host/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 688698a..5e0ae5c 100644
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -145,7 +145,7 @@ config XPS_USB_HCD_XILINX
+ 
+ config USB_EHCI_FSL
+ 	bool "Support for Freescale PPC on-chip EHCI USB controller"
+-	depends on FSL_SOC
++	depends on USB_EHCI_HCD
+ 	select USB_EHCI_ROOT_HUB_TT
+ 	select USB_FSL_MPH_DR_OF if OF
+ 	---help---
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0014-arm-dts-ls1043a-Add-configure-gfladj-property-to-USB.patch b/target/linux/layerscape-64b/patches-4.1/0014-arm-dts-ls1043a-Add-configure-gfladj-property-to-USB.patch
new file mode 100644
index 0000000..6960318
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0014-arm-dts-ls1043a-Add-configure-gfladj-property-to-USB.patch
@@ -0,0 +1,38 @@
+From 31fa3f01c9b7146c0bc1d810b43045df58f1452d Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat at freescale.com>
+Date: Wed, 27 Jan 2016 11:37:25 +0530
+Subject: [PATCH 014/151] arm:dts:ls1043a : Add configure-gfladj property to
+ USB3 node
+
+Add "configure-gfladj" boolean property to USB3 node. This property
+is used to determine whether frame length adjustent is required
+or not
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+index 5654173..5c6fb76 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -733,6 +733,7 @@
+ 			reg = <0x0 0x3000000 0x0 0x10000>;
+ 			interrupts = <0 61 0x4>;
+ 			dr_mode = "host";
++			configure-gfladj;
+ 		};
+ 
+ 		usb2: usb3 at 3100000 {
+@@ -740,6 +741,7 @@
+ 			reg = <0x0 0x3100000 0x0 0x10000>;
+ 			interrupts = <0 63 0x4>;
+ 			dr_mode = "host";
++			configure-gfladj;
+ 		};
+ 
+ 		sata: sata at 3200000 {
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0015-powerpc-fsl-Move-fsl_guts.h-out-of-arch-powerpc.patch b/target/linux/layerscape-64b/patches-4.1/0015-powerpc-fsl-Move-fsl_guts.h-out-of-arch-powerpc.patch
new file mode 100644
index 0000000..abc7d6b
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0015-powerpc-fsl-Move-fsl_guts.h-out-of-arch-powerpc.patch
@@ -0,0 +1,637 @@
+From 4fa144cf81d35aa3e213bf6107ecefe042fb8e52 Mon Sep 17 00:00:00 2001
+From: Scott Wood <scottwood at freescale.com>
+Date: Fri, 15 Jan 2016 07:34:24 +0000
+Subject: [PATCH 015/151] powerpc/fsl: Move fsl_guts.h out of arch/powerpc
+
+Freescale's Layerscape ARM chips use the same structure.
+
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+(cherry picked from commit 948486544713492f00ac8a9572909101ea892cb0)
+Signed-off-by: Scott Wood <scottwood at freescale.com>
+---
+ arch/powerpc/include/asm/fsl_guts.h        | 192 -----------------------------
+ arch/powerpc/platforms/85xx/mpc85xx_mds.c  |   2 +-
+ arch/powerpc/platforms/85xx/mpc85xx_rdb.c  |   2 +-
+ arch/powerpc/platforms/85xx/p1022_ds.c     |   2 +-
+ arch/powerpc/platforms/85xx/p1022_rdk.c    |   2 +-
+ arch/powerpc/platforms/85xx/smp.c          |   2 +-
+ arch/powerpc/platforms/85xx/twr_p102x.c    |   2 +-
+ arch/powerpc/platforms/86xx/mpc8610_hpcd.c |   2 +-
+ drivers/iommu/fsl_pamu.c                   |   2 +-
+ include/linux/fsl/guts.h                   | 192 +++++++++++++++++++++++++++++
+ sound/soc/fsl/mpc8610_hpcd.c               |   2 +-
+ sound/soc/fsl/p1022_ds.c                   |   2 +-
+ sound/soc/fsl/p1022_rdk.c                  |   2 +-
+ 13 files changed, 203 insertions(+), 203 deletions(-)
+ delete mode 100644 arch/powerpc/include/asm/fsl_guts.h
+ create mode 100644 include/linux/fsl/guts.h
+
+diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
+deleted file mode 100644
+index 43b6bb1..0000000
+--- a/arch/powerpc/include/asm/fsl_guts.h
++++ /dev/null
+@@ -1,192 +0,0 @@
+-/**
+- * Freecale 85xx and 86xx Global Utilties register set
+- *
+- * Authors: Jeff Brown
+- *          Timur Tabi <timur at freescale.com>
+- *
+- * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- */
+-
+-#ifndef __ASM_POWERPC_FSL_GUTS_H__
+-#define __ASM_POWERPC_FSL_GUTS_H__
+-#ifdef __KERNEL__
+-
+-/**
+- * Global Utility Registers.
+- *
+- * Not all registers defined in this structure are available on all chips, so
+- * you are expected to know whether a given register actually exists on your
+- * chip before you access it.
+- *
+- * Also, some registers are similar on different chips but have slightly
+- * different names.  In these cases, one name is chosen to avoid extraneous
+- * #ifdefs.
+- */
+-struct ccsr_guts {
+-	__be32	porpllsr;	/* 0x.0000 - POR PLL Ratio Status Register */
+-	__be32	porbmsr;	/* 0x.0004 - POR Boot Mode Status Register */
+-	__be32	porimpscr;	/* 0x.0008 - POR I/O Impedance Status and Control Register */
+-	__be32	pordevsr;	/* 0x.000c - POR I/O Device Status Register */
+-	__be32	pordbgmsr;	/* 0x.0010 - POR Debug Mode Status Register */
+-	__be32	pordevsr2;	/* 0x.0014 - POR device status register 2 */
+-	u8	res018[0x20 - 0x18];
+-	__be32	porcir;		/* 0x.0020 - POR Configuration Information Register */
+-	u8	res024[0x30 - 0x24];
+-	__be32	gpiocr;		/* 0x.0030 - GPIO Control Register */
+-	u8	res034[0x40 - 0x34];
+-	__be32	gpoutdr;	/* 0x.0040 - General-Purpose Output Data Register */
+-	u8	res044[0x50 - 0x44];
+-	__be32	gpindr;		/* 0x.0050 - General-Purpose Input Data Register */
+-	u8	res054[0x60 - 0x54];
+-	__be32	pmuxcr;		/* 0x.0060 - Alternate Function Signal Multiplex Control */
+-        __be32  pmuxcr2;	/* 0x.0064 - Alternate function signal multiplex control 2 */
+-        __be32  dmuxcr;		/* 0x.0068 - DMA Mux Control Register */
+-        u8	res06c[0x70 - 0x6c];
+-	__be32	devdisr;	/* 0x.0070 - Device Disable Control */
+-#define CCSR_GUTS_DEVDISR_TB1	0x00001000
+-#define CCSR_GUTS_DEVDISR_TB0	0x00004000
+-	__be32	devdisr2;	/* 0x.0074 - Device Disable Control 2 */
+-	u8	res078[0x7c - 0x78];
+-	__be32  pmjcr;		/* 0x.007c - 4 Power Management Jog Control Register */
+-	__be32	powmgtcsr;	/* 0x.0080 - Power Management Status and Control Register */
+-	__be32  pmrccr;		/* 0x.0084 - Power Management Reset Counter Configuration Register */
+-	__be32  pmpdccr;	/* 0x.0088 - Power Management Power Down Counter Configuration Register */
+-	__be32  pmcdr;		/* 0x.008c - 4Power management clock disable register */
+-	__be32	mcpsumr;	/* 0x.0090 - Machine Check Summary Register */
+-	__be32	rstrscr;	/* 0x.0094 - Reset Request Status and Control Register */
+-	__be32  ectrstcr;	/* 0x.0098 - Exception reset control register */
+-	__be32  autorstsr;	/* 0x.009c - Automatic reset status register */
+-	__be32	pvr;		/* 0x.00a0 - Processor Version Register */
+-	__be32	svr;		/* 0x.00a4 - System Version Register */
+-	u8	res0a8[0xb0 - 0xa8];
+-	__be32	rstcr;		/* 0x.00b0 - Reset Control Register */
+-	u8	res0b4[0xc0 - 0xb4];
+-	__be32  iovselsr;	/* 0x.00c0 - I/O voltage select status register
+-					     Called 'elbcvselcr' on 86xx SOCs */
+-	u8	res0c4[0x100 - 0xc4];
+-	__be32	rcwsr[16];	/* 0x.0100 - Reset Control Word Status registers
+-					     There are 16 registers */
+-	u8	res140[0x224 - 0x140];
+-	__be32  iodelay1;	/* 0x.0224 - IO delay control register 1 */
+-	__be32  iodelay2;	/* 0x.0228 - IO delay control register 2 */
+-	u8	res22c[0x604 - 0x22c];
+-	__be32	pamubypenr; 	/* 0x.604 - PAMU bypass enable register */
+-	u8	res608[0x800 - 0x608];
+-	__be32	clkdvdr;	/* 0x.0800 - Clock Divide Register */
+-	u8	res804[0x900 - 0x804];
+-	__be32	ircr;		/* 0x.0900 - Infrared Control Register */
+-	u8	res904[0x908 - 0x904];
+-	__be32	dmacr;		/* 0x.0908 - DMA Control Register */
+-	u8	res90c[0x914 - 0x90c];
+-	__be32	elbccr;		/* 0x.0914 - eLBC Control Register */
+-	u8	res918[0xb20 - 0x918];
+-	__be32	ddr1clkdr;	/* 0x.0b20 - DDR1 Clock Disable Register */
+-	__be32	ddr2clkdr;	/* 0x.0b24 - DDR2 Clock Disable Register */
+-	__be32	ddrclkdr;	/* 0x.0b28 - DDR Clock Disable Register */
+-	u8	resb2c[0xe00 - 0xb2c];
+-	__be32	clkocr;		/* 0x.0e00 - Clock Out Select Register */
+-	u8	rese04[0xe10 - 0xe04];
+-	__be32	ddrdllcr;	/* 0x.0e10 - DDR DLL Control Register */
+-	u8	rese14[0xe20 - 0xe14];
+-	__be32	lbcdllcr;	/* 0x.0e20 - LBC DLL Control Register */
+-	__be32  cpfor;		/* 0x.0e24 - L2 charge pump fuse override register */
+-	u8	rese28[0xf04 - 0xe28];
+-	__be32	srds1cr0;	/* 0x.0f04 - SerDes1 Control Register 0 */
+-	__be32	srds1cr1;	/* 0x.0f08 - SerDes1 Control Register 0 */
+-	u8	resf0c[0xf2c - 0xf0c];
+-	__be32  itcr;		/* 0x.0f2c - Internal transaction control register */
+-	u8	resf30[0xf40 - 0xf30];
+-	__be32	srds2cr0;	/* 0x.0f40 - SerDes2 Control Register 0 */
+-	__be32	srds2cr1;	/* 0x.0f44 - SerDes2 Control Register 0 */
+-} __attribute__ ((packed));
+-
+-
+-/* Alternate function signal multiplex control */
+-#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
+-
+-#ifdef CONFIG_PPC_86xx
+-
+-#define CCSR_GUTS_DMACR_DEV_SSI	0	/* DMA controller/channel set to SSI */
+-#define CCSR_GUTS_DMACR_DEV_IR	1	/* DMA controller/channel set to IR */
+-
+-/*
+- * Set the DMACR register in the GUTS
+- *
+- * The DMACR register determines the source of initiated transfers for each
+- * channel on each DMA controller.  Rather than have a bunch of repetitive
+- * macros for the bit patterns, we just have a function that calculates
+- * them.
+- *
+- * guts: Pointer to GUTS structure
+- * co: The DMA controller (0 or 1)
+- * ch: The channel on the DMA controller (0, 1, 2, or 3)
+- * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
+- */
+-static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
+-	unsigned int co, unsigned int ch, unsigned int device)
+-{
+-	unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
+-
+-	clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
+-}
+-
+-#define CCSR_GUTS_PMUXCR_LDPSEL		0x00010000
+-#define CCSR_GUTS_PMUXCR_SSI1_MASK	0x0000C000	/* Bitmask for SSI1 */
+-#define CCSR_GUTS_PMUXCR_SSI1_LA	0x00000000	/* Latched address */
+-#define CCSR_GUTS_PMUXCR_SSI1_HI	0x00004000	/* High impedance */
+-#define CCSR_GUTS_PMUXCR_SSI1_SSI	0x00008000	/* Used for SSI1 */
+-#define CCSR_GUTS_PMUXCR_SSI2_MASK	0x00003000	/* Bitmask for SSI2 */
+-#define CCSR_GUTS_PMUXCR_SSI2_LA	0x00000000	/* Latched address */
+-#define CCSR_GUTS_PMUXCR_SSI2_HI	0x00001000	/* High impedance */
+-#define CCSR_GUTS_PMUXCR_SSI2_SSI	0x00002000	/* Used for SSI2 */
+-#define CCSR_GUTS_PMUXCR_LA_22_25_LA	0x00000000	/* Latched Address */
+-#define CCSR_GUTS_PMUXCR_LA_22_25_HI	0x00000400	/* High impedance */
+-#define CCSR_GUTS_PMUXCR_DBGDRV		0x00000200	/* Signals not driven */
+-#define CCSR_GUTS_PMUXCR_DMA2_0		0x00000008
+-#define CCSR_GUTS_PMUXCR_DMA2_3		0x00000004
+-#define CCSR_GUTS_PMUXCR_DMA1_0		0x00000002
+-#define CCSR_GUTS_PMUXCR_DMA1_3		0x00000001
+-
+-/*
+- * Set the DMA external control bits in the GUTS
+- *
+- * The DMA external control bits in the PMUXCR are only meaningful for
+- * channels 0 and 3.  Any other channels are ignored.
+- *
+- * guts: Pointer to GUTS structure
+- * co: The DMA controller (0 or 1)
+- * ch: The channel on the DMA controller (0, 1, 2, or 3)
+- * value: the new value for the bit (0 or 1)
+- */
+-static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
+-	unsigned int co, unsigned int ch, unsigned int value)
+-{
+-	if ((ch == 0) || (ch == 3)) {
+-		unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
+-
+-		clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
+-	}
+-}
+-
+-#define CCSR_GUTS_CLKDVDR_PXCKEN	0x80000000
+-#define CCSR_GUTS_CLKDVDR_SSICKEN	0x20000000
+-#define CCSR_GUTS_CLKDVDR_PXCKINV	0x10000000
+-#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
+-#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK	0x06000000
+-#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
+-	(((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
+-#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT	16
+-#define CCSR_GUTS_CLKDVDR_PXCLK_MASK	0x001F0000
+-#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
+-#define CCSR_GUTS_CLKDVDR_SSICLK_MASK	0x000000FF
+-#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
+-
+-#endif
+-
+-#endif
+-#endif
+diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+index a392e94..f0be439 100644
+--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
++++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+@@ -34,6 +34,7 @@
+ #include <linux/of_device.h>
+ #include <linux/phy.h>
+ #include <linux/memblock.h>
++#include <linux/fsl/guts.h>
+ 
+ #include <linux/atomic.h>
+ #include <asm/time.h>
+@@ -51,7 +52,6 @@
+ #include <asm/qe_ic.h>
+ #include <asm/mpic.h>
+ #include <asm/swiotlb.h>
+-#include <asm/fsl_guts.h>
+ #include "smp.h"
+ 
+ #include "mpc85xx.h"
+diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+index e358bed..50dcc00 100644
+--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
++++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+@@ -17,6 +17,7 @@
+ #include <linux/seq_file.h>
+ #include <linux/interrupt.h>
+ #include <linux/of_platform.h>
++#include <linux/fsl/guts.h>
+ 
+ #include <asm/time.h>
+ #include <asm/machdep.h>
+@@ -27,7 +28,6 @@
+ #include <asm/mpic.h>
+ #include <asm/qe.h>
+ #include <asm/qe_ic.h>
+-#include <asm/fsl_guts.h>
+ 
+ #include <sysdev/fsl_soc.h>
+ #include <sysdev/fsl_pci.h>
+diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
+index 6ac986d..371df82 100644
+--- a/arch/powerpc/platforms/85xx/p1022_ds.c
++++ b/arch/powerpc/platforms/85xx/p1022_ds.c
+@@ -16,6 +16,7 @@
+  * kind, whether express or implied.
+  */
+ 
++#include <linux/fsl/guts.h>
+ #include <linux/pci.h>
+ #include <linux/of_platform.h>
+ #include <asm/div64.h>
+@@ -25,7 +26,6 @@
+ #include <sysdev/fsl_soc.h>
+ #include <sysdev/fsl_pci.h>
+ #include <asm/udbg.h>
+-#include <asm/fsl_guts.h>
+ #include <asm/fsl_lbc.h>
+ #include "smp.h"
+ 
+diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
+index 680232d..5087bec 100644
+--- a/arch/powerpc/platforms/85xx/p1022_rdk.c
++++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
+@@ -12,6 +12,7 @@
+  * kind, whether express or implied.
+  */
+ 
++#include <linux/fsl/guts.h>
+ #include <linux/pci.h>
+ #include <linux/of_platform.h>
+ #include <asm/div64.h>
+@@ -21,7 +22,6 @@
+ #include <sysdev/fsl_soc.h>
+ #include <sysdev/fsl_pci.h>
+ #include <asm/udbg.h>
+-#include <asm/fsl_guts.h>
+ #include "smp.h"
+ 
+ #include "mpc85xx.h"
+diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
+index 8631ac5..c88981f 100644
+--- a/arch/powerpc/platforms/85xx/smp.c
++++ b/arch/powerpc/platforms/85xx/smp.c
+@@ -19,6 +19,7 @@
+ #include <linux/kexec.h>
+ #include <linux/highmem.h>
+ #include <linux/cpu.h>
++#include <linux/fsl/guts.h>
+ 
+ #include <asm/machdep.h>
+ #include <asm/pgtable.h>
+@@ -26,7 +27,6 @@
+ #include <asm/mpic.h>
+ #include <asm/cacheflush.h>
+ #include <asm/dbell.h>
+-#include <asm/fsl_guts.h>
+ #include <asm/code-patching.h>
+ #include <asm/cputhreads.h>
+ 
+diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
+index 1eadb6d..2799120 100644
+--- a/arch/powerpc/platforms/85xx/twr_p102x.c
++++ b/arch/powerpc/platforms/85xx/twr_p102x.c
+@@ -15,6 +15,7 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/errno.h>
++#include <linux/fsl/guts.h>
+ #include <linux/pci.h>
+ #include <linux/of_platform.h>
+ 
+@@ -23,7 +24,6 @@
+ #include <asm/mpic.h>
+ #include <asm/qe.h>
+ #include <asm/qe_ic.h>
+-#include <asm/fsl_guts.h>
+ 
+ #include <sysdev/fsl_soc.h>
+ #include <sysdev/fsl_pci.h>
+diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+index 55413a5..437a9c3 100644
+--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
++++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+@@ -24,6 +24,7 @@
+ #include <linux/delay.h>
+ #include <linux/seq_file.h>
+ #include <linux/of.h>
++#include <linux/fsl/guts.h>
+ 
+ #include <asm/time.h>
+ #include <asm/machdep.h>
+@@ -38,7 +39,6 @@
+ #include <sysdev/fsl_pci.h>
+ #include <sysdev/fsl_soc.h>
+ #include <sysdev/simple_gpio.h>
+-#include <asm/fsl_guts.h>
+ 
+ #include "mpc86xx.h"
+ 
+diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c
+index 2570f2a..a34355f 100644
+--- a/drivers/iommu/fsl_pamu.c
++++ b/drivers/iommu/fsl_pamu.c
+@@ -20,11 +20,11 @@
+ 
+ #include "fsl_pamu.h"
+ 
++#include <linux/fsl/guts.h>
+ #include <linux/interrupt.h>
+ #include <linux/genalloc.h>
+ 
+ #include <asm/mpc85xx.h>
+-#include <asm/fsl_guts.h>
+ 
+ /* define indexes for each operation mapping scenario */
+ #define OMI_QMAN        0x00
+diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
+new file mode 100644
+index 0000000..84d971f
+--- /dev/null
++++ b/include/linux/fsl/guts.h
+@@ -0,0 +1,192 @@
++/**
++ * Freecale 85xx and 86xx Global Utilties register set
++ *
++ * Authors: Jeff Brown
++ *          Timur Tabi <timur at freescale.com>
++ *
++ * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++#ifndef __FSL_GUTS_H__
++#define __FSL_GUTS_H__
++
++#include <linux/types.h>
++
++/**
++ * Global Utility Registers.
++ *
++ * Not all registers defined in this structure are available on all chips, so
++ * you are expected to know whether a given register actually exists on your
++ * chip before you access it.
++ *
++ * Also, some registers are similar on different chips but have slightly
++ * different names.  In these cases, one name is chosen to avoid extraneous
++ * #ifdefs.
++ */
++struct ccsr_guts {
++	__be32	porpllsr;	/* 0x.0000 - POR PLL Ratio Status Register */
++	__be32	porbmsr;	/* 0x.0004 - POR Boot Mode Status Register */
++	__be32	porimpscr;	/* 0x.0008 - POR I/O Impedance Status and Control Register */
++	__be32	pordevsr;	/* 0x.000c - POR I/O Device Status Register */
++	__be32	pordbgmsr;	/* 0x.0010 - POR Debug Mode Status Register */
++	__be32	pordevsr2;	/* 0x.0014 - POR device status register 2 */
++	u8	res018[0x20 - 0x18];
++	__be32	porcir;		/* 0x.0020 - POR Configuration Information Register */
++	u8	res024[0x30 - 0x24];
++	__be32	gpiocr;		/* 0x.0030 - GPIO Control Register */
++	u8	res034[0x40 - 0x34];
++	__be32	gpoutdr;	/* 0x.0040 - General-Purpose Output Data Register */
++	u8	res044[0x50 - 0x44];
++	__be32	gpindr;		/* 0x.0050 - General-Purpose Input Data Register */
++	u8	res054[0x60 - 0x54];
++	__be32	pmuxcr;		/* 0x.0060 - Alternate Function Signal Multiplex Control */
++        __be32  pmuxcr2;	/* 0x.0064 - Alternate function signal multiplex control 2 */
++        __be32  dmuxcr;		/* 0x.0068 - DMA Mux Control Register */
++        u8	res06c[0x70 - 0x6c];
++	__be32	devdisr;	/* 0x.0070 - Device Disable Control */
++#define CCSR_GUTS_DEVDISR_TB1	0x00001000
++#define CCSR_GUTS_DEVDISR_TB0	0x00004000
++	__be32	devdisr2;	/* 0x.0074 - Device Disable Control 2 */
++	u8	res078[0x7c - 0x78];
++	__be32  pmjcr;		/* 0x.007c - 4 Power Management Jog Control Register */
++	__be32	powmgtcsr;	/* 0x.0080 - Power Management Status and Control Register */
++	__be32  pmrccr;		/* 0x.0084 - Power Management Reset Counter Configuration Register */
++	__be32  pmpdccr;	/* 0x.0088 - Power Management Power Down Counter Configuration Register */
++	__be32  pmcdr;		/* 0x.008c - 4Power management clock disable register */
++	__be32	mcpsumr;	/* 0x.0090 - Machine Check Summary Register */
++	__be32	rstrscr;	/* 0x.0094 - Reset Request Status and Control Register */
++	__be32  ectrstcr;	/* 0x.0098 - Exception reset control register */
++	__be32  autorstsr;	/* 0x.009c - Automatic reset status register */
++	__be32	pvr;		/* 0x.00a0 - Processor Version Register */
++	__be32	svr;		/* 0x.00a4 - System Version Register */
++	u8	res0a8[0xb0 - 0xa8];
++	__be32	rstcr;		/* 0x.00b0 - Reset Control Register */
++	u8	res0b4[0xc0 - 0xb4];
++	__be32  iovselsr;	/* 0x.00c0 - I/O voltage select status register
++					     Called 'elbcvselcr' on 86xx SOCs */
++	u8	res0c4[0x100 - 0xc4];
++	__be32	rcwsr[16];	/* 0x.0100 - Reset Control Word Status registers
++					     There are 16 registers */
++	u8	res140[0x224 - 0x140];
++	__be32  iodelay1;	/* 0x.0224 - IO delay control register 1 */
++	__be32  iodelay2;	/* 0x.0228 - IO delay control register 2 */
++	u8	res22c[0x604 - 0x22c];
++	__be32	pamubypenr; 	/* 0x.604 - PAMU bypass enable register */
++	u8	res608[0x800 - 0x608];
++	__be32	clkdvdr;	/* 0x.0800 - Clock Divide Register */
++	u8	res804[0x900 - 0x804];
++	__be32	ircr;		/* 0x.0900 - Infrared Control Register */
++	u8	res904[0x908 - 0x904];
++	__be32	dmacr;		/* 0x.0908 - DMA Control Register */
++	u8	res90c[0x914 - 0x90c];
++	__be32	elbccr;		/* 0x.0914 - eLBC Control Register */
++	u8	res918[0xb20 - 0x918];
++	__be32	ddr1clkdr;	/* 0x.0b20 - DDR1 Clock Disable Register */
++	__be32	ddr2clkdr;	/* 0x.0b24 - DDR2 Clock Disable Register */
++	__be32	ddrclkdr;	/* 0x.0b28 - DDR Clock Disable Register */
++	u8	resb2c[0xe00 - 0xb2c];
++	__be32	clkocr;		/* 0x.0e00 - Clock Out Select Register */
++	u8	rese04[0xe10 - 0xe04];
++	__be32	ddrdllcr;	/* 0x.0e10 - DDR DLL Control Register */
++	u8	rese14[0xe20 - 0xe14];
++	__be32	lbcdllcr;	/* 0x.0e20 - LBC DLL Control Register */
++	__be32  cpfor;		/* 0x.0e24 - L2 charge pump fuse override register */
++	u8	rese28[0xf04 - 0xe28];
++	__be32	srds1cr0;	/* 0x.0f04 - SerDes1 Control Register 0 */
++	__be32	srds1cr1;	/* 0x.0f08 - SerDes1 Control Register 0 */
++	u8	resf0c[0xf2c - 0xf0c];
++	__be32  itcr;		/* 0x.0f2c - Internal transaction control register */
++	u8	resf30[0xf40 - 0xf30];
++	__be32	srds2cr0;	/* 0x.0f40 - SerDes2 Control Register 0 */
++	__be32	srds2cr1;	/* 0x.0f44 - SerDes2 Control Register 0 */
++} __attribute__ ((packed));
++
++
++/* Alternate function signal multiplex control */
++#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
++
++#ifdef CONFIG_PPC_86xx
++
++#define CCSR_GUTS_DMACR_DEV_SSI	0	/* DMA controller/channel set to SSI */
++#define CCSR_GUTS_DMACR_DEV_IR	1	/* DMA controller/channel set to IR */
++
++/*
++ * Set the DMACR register in the GUTS
++ *
++ * The DMACR register determines the source of initiated transfers for each
++ * channel on each DMA controller.  Rather than have a bunch of repetitive
++ * macros for the bit patterns, we just have a function that calculates
++ * them.
++ *
++ * guts: Pointer to GUTS structure
++ * co: The DMA controller (0 or 1)
++ * ch: The channel on the DMA controller (0, 1, 2, or 3)
++ * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
++ */
++static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
++	unsigned int co, unsigned int ch, unsigned int device)
++{
++	unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
++
++	clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
++}
++
++#define CCSR_GUTS_PMUXCR_LDPSEL		0x00010000
++#define CCSR_GUTS_PMUXCR_SSI1_MASK	0x0000C000	/* Bitmask for SSI1 */
++#define CCSR_GUTS_PMUXCR_SSI1_LA	0x00000000	/* Latched address */
++#define CCSR_GUTS_PMUXCR_SSI1_HI	0x00004000	/* High impedance */
++#define CCSR_GUTS_PMUXCR_SSI1_SSI	0x00008000	/* Used for SSI1 */
++#define CCSR_GUTS_PMUXCR_SSI2_MASK	0x00003000	/* Bitmask for SSI2 */
++#define CCSR_GUTS_PMUXCR_SSI2_LA	0x00000000	/* Latched address */
++#define CCSR_GUTS_PMUXCR_SSI2_HI	0x00001000	/* High impedance */
++#define CCSR_GUTS_PMUXCR_SSI2_SSI	0x00002000	/* Used for SSI2 */
++#define CCSR_GUTS_PMUXCR_LA_22_25_LA	0x00000000	/* Latched Address */
++#define CCSR_GUTS_PMUXCR_LA_22_25_HI	0x00000400	/* High impedance */
++#define CCSR_GUTS_PMUXCR_DBGDRV		0x00000200	/* Signals not driven */
++#define CCSR_GUTS_PMUXCR_DMA2_0		0x00000008
++#define CCSR_GUTS_PMUXCR_DMA2_3		0x00000004
++#define CCSR_GUTS_PMUXCR_DMA1_0		0x00000002
++#define CCSR_GUTS_PMUXCR_DMA1_3		0x00000001
++
++/*
++ * Set the DMA external control bits in the GUTS
++ *
++ * The DMA external control bits in the PMUXCR are only meaningful for
++ * channels 0 and 3.  Any other channels are ignored.
++ *
++ * guts: Pointer to GUTS structure
++ * co: The DMA controller (0 or 1)
++ * ch: The channel on the DMA controller (0, 1, 2, or 3)
++ * value: the new value for the bit (0 or 1)
++ */
++static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
++	unsigned int co, unsigned int ch, unsigned int value)
++{
++	if ((ch == 0) || (ch == 3)) {
++		unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
++
++		clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
++	}
++}
++
++#define CCSR_GUTS_CLKDVDR_PXCKEN	0x80000000
++#define CCSR_GUTS_CLKDVDR_SSICKEN	0x20000000
++#define CCSR_GUTS_CLKDVDR_PXCKINV	0x10000000
++#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
++#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK	0x06000000
++#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
++	(((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
++#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT	16
++#define CCSR_GUTS_CLKDVDR_PXCLK_MASK	0x001F0000
++#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
++#define CCSR_GUTS_CLKDVDR_SSICLK_MASK	0x000000FF
++#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
++
++#endif
++
++#endif
+diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
+index 9621b91..6f236f1 100644
+--- a/sound/soc/fsl/mpc8610_hpcd.c
++++ b/sound/soc/fsl/mpc8610_hpcd.c
+@@ -12,11 +12,11 @@
+ 
+ #include <linux/module.h>
+ #include <linux/interrupt.h>
++#include <linux/fsl/guts.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/slab.h>
+ #include <sound/soc.h>
+-#include <asm/fsl_guts.h>
+ 
+ #include "fsl_dma.h"
+ #include "fsl_ssi.h"
+diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
+index 71c1a7d..747aab0 100644
+--- a/sound/soc/fsl/p1022_ds.c
++++ b/sound/soc/fsl/p1022_ds.c
+@@ -11,12 +11,12 @@
+  */
+ 
+ #include <linux/module.h>
++#include <linux/fsl/guts.h>
+ #include <linux/interrupt.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/slab.h>
+ #include <sound/soc.h>
+-#include <asm/fsl_guts.h>
+ 
+ #include "fsl_dma.h"
+ #include "fsl_ssi.h"
+diff --git a/sound/soc/fsl/p1022_rdk.c b/sound/soc/fsl/p1022_rdk.c
+index ee29048..1dd49e5 100644
+--- a/sound/soc/fsl/p1022_rdk.c
++++ b/sound/soc/fsl/p1022_rdk.c
+@@ -18,12 +18,12 @@
+  */
+ 
+ #include <linux/module.h>
++#include <linux/fsl/guts.h>
+ #include <linux/interrupt.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/slab.h>
+ #include <sound/soc.h>
+-#include <asm/fsl_guts.h>
+ 
+ #include "fsl_dma.h"
+ #include "fsl_ssi.h"
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0016-driver-memory-Removal-of-deprecated-NO_IRQ.patch b/target/linux/layerscape-64b/patches-4.1/0016-driver-memory-Removal-of-deprecated-NO_IRQ.patch
new file mode 100644
index 0000000..1dcb99d
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0016-driver-memory-Removal-of-deprecated-NO_IRQ.patch
@@ -0,0 +1,29 @@
+From af33865c6ca19eb849e7d00c9c58037aed9d8c5d Mon Sep 17 00:00:00 2001
+From: Raghav Dogra <raghav at freescale.com>
+Date: Wed, 16 Dec 2015 16:11:31 +0530
+Subject: [PATCH 016/151] driver/memory: Removal of deprecated NO_IRQ
+
+Replacing the NO_IRQ macro with 0. If there is no interrupt,
+returned value will be 0 regardless of what NO_IRQ is defined.
+
+Signed-off-by: Raghav Dogra <raghav at freescale.com>
+---
+ drivers/memory/fsl_ifc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c
+index 410c397..5f6d42d 100644
+--- a/drivers/memory/fsl_ifc.c
++++ b/drivers/memory/fsl_ifc.c
+@@ -242,7 +242,7 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
+ 
+ 	/* get the Controller level irq */
+ 	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
+-	if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
++	if (fsl_ifc_ctrl_dev->irq == 0) {
+ 		dev_err(&dev->dev, "failed to get irq resource "
+ 							"for IFC\n");
+ 		ret = -ENODEV;
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0017-net-fsl-remove-dependency-FSL_SOC-for-Gianfar.patch b/target/linux/layerscape-64b/patches-4.1/0017-net-fsl-remove-dependency-FSL_SOC-for-Gianfar.patch
new file mode 100644
index 0000000..7b8a1b0
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0017-net-fsl-remove-dependency-FSL_SOC-for-Gianfar.patch
@@ -0,0 +1,36 @@
+From d08a08ee248e0f59ca61e38e537991baf1f2abe1 Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965 at freescale.com>
+Date: Thu, 25 Jun 2015 11:34:38 +0800
+Subject: [PATCH 017/151] net/fsl: remove dependency FSL_SOC for Gianfar
+
+CONFIG_GIANFAR is not depended on FSL_SOC, it
+can be built on non-PPC platforms.
+
+Signed-off-by: Alison Wang <alison.wang at freescale.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+ drivers/net/ethernet/freescale/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
+index 25e3425..e383dba 100644
+--- a/drivers/net/ethernet/freescale/Kconfig
++++ b/drivers/net/ethernet/freescale/Kconfig
+@@ -85,12 +85,12 @@ config UGETH_TX_ON_DEMAND
+ 
+ config GIANFAR
+ 	tristate "Gianfar Ethernet"
+-	depends on FSL_SOC
+ 	select FSL_PQ_MDIO
+ 	select PHYLIB
+ 	select CRC32
+ 	---help---
+ 	  This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
+-	  and MPC86xx family of chips, and the FEC on the 8540.
++	  and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
++	  on the 8540.
+ 
+ endif # NET_VENDOR_FREESCALE
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0018-temp-QE-headers-are-needed-by-FMD.patch b/target/linux/layerscape-64b/patches-4.1/0018-temp-QE-headers-are-needed-by-FMD.patch
new file mode 100644
index 0000000..98adc07
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0018-temp-QE-headers-are-needed-by-FMD.patch
@@ -0,0 +1,1326 @@
+From b6c8e00238ca26861c85e2aeab1d8ecbd7b6ea43 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur at freescale.com>
+Date: Tue, 5 Jan 2016 15:41:28 +0200
+Subject: [PATCH 018/151] temp: QE headers are needed by FMD
+
+Signed-off-by: Madalin Bucur <madalin.bucur at freescale.com>
+---
+ include/linux/fsl/immap_qe.h | 488 ++++++++++++++++++++++++++
+ include/linux/fsl/qe.h       | 810 +++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 1298 insertions(+)
+ create mode 100644 include/linux/fsl/immap_qe.h
+ create mode 100644 include/linux/fsl/qe.h
+
+diff --git a/include/linux/fsl/immap_qe.h b/include/linux/fsl/immap_qe.h
+new file mode 100644
+index 0000000..bd1ebd4
+--- /dev/null
++++ b/include/linux/fsl/immap_qe.h
+@@ -0,0 +1,488 @@
++/*
++ * QUICC Engine (QE) Internal Memory Map.
++ * The Internal Memory Map for devices with QE on them. This
++ * is the superset of all QE devices (8360, etc.).
++ * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Authors:
++ *		Shlomi Gridish <gridish at freescale.com>
++ *		Li Yang <leoli at freescale.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef _ASM_POWERPC_IMMAP_QE_H
++#define _ASM_POWERPC_IMMAP_QE_H
++#ifdef __KERNEL__
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++
++#define QE_IMMAP_SIZE	(1024 * 1024)	/* 1MB from 1MB+IMMR */
++
++/* QE I-RAM */
++struct qe_iram {
++	__be32	iadd;		/* I-RAM Address Register */
++	__be32	idata;		/* I-RAM Data Register */
++	u8	res0[0x04];
++	__be32	iready;		/* I-RAM Ready Register */
++	u8	res1[0x70];
++} __packed;
++
++/* QE Interrupt Controller */
++struct qe_ic_regs {
++	__be32	qicr;
++	__be32	qivec;
++	__be32	qripnr;
++	__be32	qipnr;
++	__be32	qipxcc;
++	__be32	qipycc;
++	__be32	qipwcc;
++	__be32	qipzcc;
++	__be32	qimr;
++	__be32	qrimr;
++	__be32	qicnr;
++	u8	res0[0x4];
++	__be32	qiprta;
++	__be32	qiprtb;
++	u8	res1[0x4];
++	__be32	qricr;
++	u8	res2[0x20];
++	__be32	qhivec;
++	u8	res3[0x1C];
++} __packed;
++
++/* Communications Processor */
++struct cp_qe {
++	__be32	cecr;		/* QE command register */
++	__be32	ceccr;		/* QE controller configuration register */
++	__be32	cecdr;		/* QE command data register */
++	u8	res0[0xA];
++	__be16	ceter;		/* QE timer event register */
++	u8	res1[0x2];
++	__be16	cetmr;		/* QE timers mask register */
++	__be32	cetscr;		/* QE time-stamp timer control register */
++	__be32	cetsr1;		/* QE time-stamp register 1 */
++	__be32	cetsr2;		/* QE time-stamp register 2 */
++	u8	res2[0x8];
++	__be32	cevter;		/* QE virtual tasks event register */
++	__be32	cevtmr;		/* QE virtual tasks mask register */
++	__be16	cercr;		/* QE RAM control register */
++	u8	res3[0x2];
++	u8	res4[0x24];
++	__be16	ceexe1;		/* QE external request 1 event register */
++	u8	res5[0x2];
++	__be16	ceexm1;		/* QE external request 1 mask register */
++	u8	res6[0x2];
++	__be16	ceexe2;		/* QE external request 2 event register */
++	u8	res7[0x2];
++	__be16	ceexm2;		/* QE external request 2 mask register */
++	u8	res8[0x2];
++	__be16	ceexe3;		/* QE external request 3 event register */
++	u8	res9[0x2];
++	__be16	ceexm3;		/* QE external request 3 mask register */
++	u8	res10[0x2];
++	__be16	ceexe4;		/* QE external request 4 event register */
++	u8	res11[0x2];
++	__be16	ceexm4;		/* QE external request 4 mask register */
++	u8	res12[0x3A];
++	__be32	ceurnr;		/* QE microcode revision number register */
++	u8	res13[0x244];
++} __packed;
++
++/* QE Multiplexer */
++struct qe_mux {
++	__be32	cmxgcr;		/* CMX general clock route register */
++	__be32	cmxsi1cr_l;	/* CMX SI1 clock route low register */
++	__be32	cmxsi1cr_h;	/* CMX SI1 clock route high register */
++	__be32	cmxsi1syr;	/* CMX SI1 SYNC route register */
++	__be32	cmxucr[4];	/* CMX UCCx clock route registers */
++	__be32	cmxupcr;	/* CMX UPC clock route register */
++	u8	res0[0x1C];
++} __packed;
++
++/* QE Timers */
++struct qe_timers {
++	u8	gtcfr1;		/* Timer 1 and Timer 2 global config register*/
++	u8	res0[0x3];
++	u8	gtcfr2;		/* Timer 3 and timer 4 global config register*/
++	u8	res1[0xB];
++	__be16	gtmdr1;		/* Timer 1 mode register */
++	__be16	gtmdr2;		/* Timer 2 mode register */
++	__be16	gtrfr1;		/* Timer 1 reference register */
++	__be16	gtrfr2;		/* Timer 2 reference register */
++	__be16	gtcpr1;		/* Timer 1 capture register */
++	__be16	gtcpr2;		/* Timer 2 capture register */
++	__be16	gtcnr1;		/* Timer 1 counter */
++	__be16	gtcnr2;		/* Timer 2 counter */
++	__be16	gtmdr3;		/* Timer 3 mode register */
++	__be16	gtmdr4;		/* Timer 4 mode register */
++	__be16	gtrfr3;		/* Timer 3 reference register */
++	__be16	gtrfr4;		/* Timer 4 reference register */
++	__be16	gtcpr3;		/* Timer 3 capture register */
++	__be16	gtcpr4;		/* Timer 4 capture register */
++	__be16	gtcnr3;		/* Timer 3 counter */
++	__be16	gtcnr4;		/* Timer 4 counter */
++	__be16	gtevr1;		/* Timer 1 event register */
++	__be16	gtevr2;		/* Timer 2 event register */
++	__be16	gtevr3;		/* Timer 3 event register */
++	__be16	gtevr4;		/* Timer 4 event register */
++	__be16	gtps;		/* Timer 1 prescale register */
++	u8 res2[0x46];
++} __packed;
++
++/* BRG */
++struct qe_brg {
++	__be32	brgc[16];	/* BRG configuration registers */
++	u8	res0[0x40];
++} __packed;
++
++/* SPI */
++struct spi {
++	u8	res0[0x20];
++	__be32	spmode;		/* SPI mode register */
++	u8	res1[0x2];
++	u8	spie;		/* SPI event register */
++	u8	res2[0x1];
++	u8	res3[0x2];
++	u8	spim;		/* SPI mask register */
++	u8	res4[0x1];
++	u8	res5[0x1];
++	u8	spcom;		/* SPI command register */
++	u8	res6[0x2];
++	__be32	spitd;		/* SPI transmit data register (cpu mode) */
++	__be32	spird;		/* SPI receive data register (cpu mode) */
++	u8	res7[0x8];
++} __packed;
++
++/* SI */
++struct si1 {
++	__be16	sixmr1[4];	/* SI1 TDMx (x = A B C D) mode register */
++	u8	siglmr1_h;	/* SI1 global mode register high */
++	u8	res0[0x1];
++	u8	sicmdr1_h;	/* SI1 command register high */
++	u8	res2[0x1];
++	u8	sistr1_h;	/* SI1 status register high */
++	u8	res3[0x1];
++	__be16	sirsr1_h;	/* SI1 RAM shadow address register high */
++	u8	sitarc1;	/* SI1 RAM counter Tx TDMA */
++	u8	sitbrc1;	/* SI1 RAM counter Tx TDMB */
++	u8	sitcrc1;	/* SI1 RAM counter Tx TDMC */
++	u8	sitdrc1;	/* SI1 RAM counter Tx TDMD */
++	u8	sirarc1;	/* SI1 RAM counter Rx TDMA */
++	u8	sirbrc1;	/* SI1 RAM counter Rx TDMB */
++	u8	sircrc1;	/* SI1 RAM counter Rx TDMC */
++	u8	sirdrc1;	/* SI1 RAM counter Rx TDMD */
++	u8	res4[0x8];
++	__be16	siemr1;		/* SI1 TDME mode register 16 bits */
++	__be16	sifmr1;		/* SI1 TDMF mode register 16 bits */
++	__be16	sigmr1;		/* SI1 TDMG mode register 16 bits */
++	__be16	sihmr1;		/* SI1 TDMH mode register 16 bits */
++	u8	siglmg1_l;	/* SI1 global mode register low 8 bits */
++	u8	res5[0x1];
++	u8	sicmdr1_l;	/* SI1 command register low 8 bits */
++	u8	res6[0x1];
++	u8	sistr1_l;	/* SI1 status register low 8 bits */
++	u8	res7[0x1];
++	__be16	sirsr1_l;	/* SI1 RAM shadow address register low 16 bits*/
++	u8	siterc1;	/* SI1 RAM counter Tx TDME 8 bits */
++	u8	sitfrc1;	/* SI1 RAM counter Tx TDMF 8 bits */
++	u8	sitgrc1;	/* SI1 RAM counter Tx TDMG 8 bits */
++	u8	sithrc1;	/* SI1 RAM counter Tx TDMH 8 bits */
++	u8	sirerc1;	/* SI1 RAM counter Rx TDME 8 bits */
++	u8	sirfrc1;	/* SI1 RAM counter Rx TDMF 8 bits */
++	u8	sirgrc1;	/* SI1 RAM counter Rx TDMG 8 bits */
++	u8	sirhrc1;	/* SI1 RAM counter Rx TDMH 8 bits */
++	u8	res8[0x8];
++	__be32	siml1;		/* SI1 multiframe limit register */
++	u8	siedm1;		/* SI1 extended diagnostic mode register */
++	u8	res9[0xBB];
++} __packed;
++
++/* SI Routing Tables */
++struct sir {
++	u8	tx[0x400];
++	u8	rx[0x400];
++	u8	res0[0x800];
++} __packed;
++
++/* USB Controller */
++struct qe_usb_ctlr {
++	u8	usb_usmod;
++	u8	usb_usadr;
++	u8	usb_uscom;
++	u8	res1[1];
++	__be16  usb_usep[4];
++	u8	res2[4];
++	__be16	usb_usber;
++	u8	res3[2];
++	__be16	usb_usbmr;
++	u8	res4[1];
++	u8	usb_usbs;
++	__be16	usb_ussft;
++	u8	res5[2];
++	__be16	usb_usfrn;
++	u8	res6[0x22];
++} __packed;
++
++/* MCC */
++struct qe_mcc {
++	__be32	mcce;		/* MCC event register */
++	__be32	mccm;		/* MCC mask register */
++	__be32	mccf;		/* MCC configuration register */
++	__be32	merl;		/* MCC emergency request level register */
++	u8	res0[0xF0];
++} __packed;
++
++/* QE UCC Slow */
++struct ucc_slow {
++	__be32	gumr_l;		/* UCCx general mode register (low) */
++	__be32	gumr_h;		/* UCCx general mode register (high) */
++	__be16	upsmr;		/* UCCx protocol-specific mode register */
++	u8	res0[0x2];
++	__be16	utodr;		/* UCCx transmit on demand register */
++	__be16	udsr;		/* UCCx data synchronization register */
++	__be16	ucce;		/* UCCx event register */
++	u8	res1[0x2];
++	__be16	uccm;		/* UCCx mask register */
++	u8	res2[0x1];
++	u8	uccs;		/* UCCx status register */
++	u8	res3[0x24];
++	__be16	utpt;
++	u8	res4[0x52];
++	u8	guemr;		/* UCC general extended mode register */
++} __packed;
++
++/* QE UCC Fast */
++struct ucc_fast {
++	__be32	gumr;		/* UCCx general mode register */
++	__be32	upsmr;		/* UCCx protocol-specific mode register */
++	__be16	utodr;		/* UCCx transmit on demand register */
++	u8	res0[0x2];
++	__be16	udsr;		/* UCCx data synchronization register */
++	u8	res1[0x2];
++	__be32	ucce;		/* UCCx event register */
++	__be32	uccm;		/* UCCx mask register */
++	u8	uccs;		/* UCCx status register */
++	u8	res2[0x7];
++	__be32	urfb;		/* UCC receive FIFO base */
++	__be16	urfs;		/* UCC receive FIFO size */
++	u8	res3[0x2];
++	__be16	urfet;		/* UCC receive FIFO emergency threshold */
++	__be16	urfset;		/* UCC receive FIFO special emergency
++				   threshold */
++	__be32	utfb;		/* UCC transmit FIFO base */
++	__be16	utfs;		/* UCC transmit FIFO size */
++	u8	res4[0x2];
++	__be16	utfet;		/* UCC transmit FIFO emergency threshold */
++	u8	res5[0x2];
++	__be16	utftt;		/* UCC transmit FIFO transmit threshold */
++	u8	res6[0x2];
++	__be16	utpt;		/* UCC transmit polling timer */
++	u8	res7[0x2];
++	__be32	urtry;		/* UCC retry counter register */
++	u8	res8[0x4C];
++	u8	guemr;		/* UCC general extended mode register */
++} __packed;
++
++struct ucc {
++	union {
++		struct	ucc_slow slow;
++		struct	ucc_fast fast;
++		u8	res[0x200];	/* UCC blocks are 512 bytes each */
++	};
++} __packed;
++
++/* MultiPHY UTOPIA POS Controllers (UPC) */
++struct upc {
++	__be32	upgcr;		/* UTOPIA/POS general configuration register */
++	__be32	uplpa;		/* UTOPIA/POS last PHY address */
++	__be32	uphec;		/* ATM HEC register */
++	__be32	upuc;		/* UTOPIA/POS UCC configuration */
++	__be32	updc1;		/* UTOPIA/POS device 1 configuration */
++	__be32	updc2;		/* UTOPIA/POS device 2 configuration */
++	__be32	updc3;		/* UTOPIA/POS device 3 configuration */
++	__be32	updc4;		/* UTOPIA/POS device 4 configuration */
++	__be32	upstpa;		/* UTOPIA/POS STPA threshold */
++	u8	res0[0xC];
++	__be32	updrs1_h;	/* UTOPIA/POS device 1 rate select */
++	__be32	updrs1_l;	/* UTOPIA/POS device 1 rate select */
++	__be32	updrs2_h;	/* UTOPIA/POS device 2 rate select */
++	__be32	updrs2_l;	/* UTOPIA/POS device 2 rate select */
++	__be32	updrs3_h;	/* UTOPIA/POS device 3 rate select */
++	__be32	updrs3_l;	/* UTOPIA/POS device 3 rate select */
++	__be32	updrs4_h;	/* UTOPIA/POS device 4 rate select */
++	__be32	updrs4_l;	/* UTOPIA/POS device 4 rate select */
++	__be32	updrp1;		/* UTOPIA/POS device 1 receive priority low */
++	__be32	updrp2;		/* UTOPIA/POS device 2 receive priority low */
++	__be32	updrp3;		/* UTOPIA/POS device 3 receive priority low */
++	__be32	updrp4;		/* UTOPIA/POS device 4 receive priority low */
++	__be32	upde1;		/* UTOPIA/POS device 1 event */
++	__be32	upde2;		/* UTOPIA/POS device 2 event */
++	__be32	upde3;		/* UTOPIA/POS device 3 event */
++	__be32	upde4;		/* UTOPIA/POS device 4 event */
++	__be16	uprp1;
++	__be16	uprp2;
++	__be16	uprp3;
++	__be16	uprp4;
++	u8	res1[0x8];
++	__be16	uptirr1_0;	/* Device 1 transmit internal rate 0 */
++	__be16	uptirr1_1;	/* Device 1 transmit internal rate 1 */
++	__be16	uptirr1_2;	/* Device 1 transmit internal rate 2 */
++	__be16	uptirr1_3;	/* Device 1 transmit internal rate 3 */
++	__be16	uptirr2_0;	/* Device 2 transmit internal rate 0 */
++	__be16	uptirr2_1;	/* Device 2 transmit internal rate 1 */
++	__be16	uptirr2_2;	/* Device 2 transmit internal rate 2 */
++	__be16	uptirr2_3;	/* Device 2 transmit internal rate 3 */
++	__be16	uptirr3_0;	/* Device 3 transmit internal rate 0 */
++	__be16	uptirr3_1;	/* Device 3 transmit internal rate 1 */
++	__be16	uptirr3_2;	/* Device 3 transmit internal rate 2 */
++	__be16	uptirr3_3;	/* Device 3 transmit internal rate 3 */
++	__be16	uptirr4_0;	/* Device 4 transmit internal rate 0 */
++	__be16	uptirr4_1;	/* Device 4 transmit internal rate 1 */
++	__be16	uptirr4_2;	/* Device 4 transmit internal rate 2 */
++	__be16	uptirr4_3;	/* Device 4 transmit internal rate 3 */
++	__be32	uper1;		/* Device 1 port enable register */
++	__be32	uper2;		/* Device 2 port enable register */
++	__be32	uper3;		/* Device 3 port enable register */
++	__be32	uper4;		/* Device 4 port enable register */
++	u8	res2[0x150];
++} __packed;
++
++/* SDMA */
++struct sdma {
++	__be32	sdsr;		/* Serial DMA status register */
++	__be32	sdmr;		/* Serial DMA mode register */
++	__be32	sdtr1;		/* SDMA system bus threshold register */
++	__be32	sdtr2;		/* SDMA secondary bus threshold register */
++	__be32	sdhy1;		/* SDMA system bus hysteresis register */
++	__be32	sdhy2;		/* SDMA secondary bus hysteresis register */
++	__be32	sdta1;		/* SDMA system bus address register */
++	__be32	sdta2;		/* SDMA secondary bus address register */
++	__be32	sdtm1;		/* SDMA system bus MSNUM register */
++	__be32	sdtm2;		/* SDMA secondary bus MSNUM register */
++	u8	res0[0x10];
++	__be32	sdaqr;		/* SDMA address bus qualify register */
++	__be32	sdaqmr;		/* SDMA address bus qualify mask register */
++	u8	res1[0x4];
++	__be32	sdebcr;		/* SDMA CAM entries base register */
++	u8	res2[0x38];
++} __packed;
++
++/* Debug Space */
++struct dbg {
++	__be32	bpdcr;		/* Breakpoint debug command register */
++	__be32	bpdsr;		/* Breakpoint debug status register */
++	__be32	bpdmr;		/* Breakpoint debug mask register */
++	__be32	bprmrr0;	/* Breakpoint request mode risc register 0 */
++	__be32	bprmrr1;	/* Breakpoint request mode risc register 1 */
++	u8	res0[0x8];
++	__be32	bprmtr0;	/* Breakpoint request mode trb register 0 */
++	__be32	bprmtr1;	/* Breakpoint request mode trb register 1 */
++	u8	res1[0x8];
++	__be32	bprmir;		/* Breakpoint request mode immediate register */
++	__be32	bprmsr;		/* Breakpoint request mode serial register */
++	__be32	bpemr;		/* Breakpoint exit mode register */
++	u8	res2[0x48];
++} __packed;
++
++/*
++ * RISC Special Registers (Trap and Breakpoint).  These are described in
++ * the QE Developer's Handbook.
++ */
++struct rsp {
++	__be32 tibcr[16];	/* Trap/instruction breakpoint control regs */
++	u8 res0[64];
++	__be32 ibcr0;
++	__be32 ibs0;
++	__be32 ibcnr0;
++	u8 res1[4];
++	__be32 ibcr1;
++	__be32 ibs1;
++	__be32 ibcnr1;
++	__be32 npcr;
++	__be32 dbcr;
++	__be32 dbar;
++	__be32 dbamr;
++	__be32 dbsr;
++	__be32 dbcnr;
++	u8 res2[12];
++	__be32 dbdr_h;
++	__be32 dbdr_l;
++	__be32 dbdmr_h;
++	__be32 dbdmr_l;
++	__be32 bsr;
++	__be32 bor;
++	__be32 bior;
++	u8 res3[4];
++	__be32 iatr[4];
++	__be32 eccr;		/* Exception control configuration register */
++	__be32 eicr;
++	u8 res4[0x100-0xf8];
++} __packed;
++
++struct qe_immap {
++	struct qe_iram		iram;		/* I-RAM */
++	struct qe_ic_regs	ic;		/* Interrupt Controller */
++	struct cp_qe		cp;		/* Communications Processor */
++	struct qe_mux		qmx;		/* QE Multiplexer */
++	struct qe_timers	qet;		/* QE Timers */
++	struct spi		spi[0x2];	/* spi */
++	struct qe_mcc		mcc;		/* mcc */
++	struct qe_brg		brg;		/* brg */
++	struct qe_usb_ctlr	usb;		/* USB */
++	struct si1		si1;		/* SI */
++	u8			res11[0x800];
++	struct sir		sir;		/* SI Routing Tables */
++	struct ucc		ucc1;		/* ucc1 */
++	struct ucc		ucc3;		/* ucc3 */
++	struct ucc		ucc5;		/* ucc5 */
++	struct ucc		ucc7;		/* ucc7 */
++	u8			res12[0x600];
++	struct upc		upc1;		/* MultiPHY UTOPIA POS Ctrlr 1*/
++	struct ucc		ucc2;		/* ucc2 */
++	struct ucc		ucc4;		/* ucc4 */
++	struct ucc		ucc6;		/* ucc6 */
++	struct ucc		ucc8;		/* ucc8 */
++	u8			res13[0x600];
++	struct upc		upc2;		/* MultiPHY UTOPIA POS Ctrlr 2*/
++	struct sdma		sdma;		/* SDMA */
++	struct dbg		dbg;		/* 0x104080 - 0x1040FF
++						   Debug Space */
++	struct rsp		rsp[0x2];	/* 0x104100 - 0x1042FF
++						   RISC Special Registers
++						   (Trap and Breakpoint) */
++	u8			res14[0x300];	/* 0x104300 - 0x1045FF */
++	u8			res15[0x3A00];	/* 0x104600 - 0x107FFF */
++	u8			res16[0x8000];	/* 0x108000 - 0x110000 */
++	u8			muram[0xC000];	/* 0x110000 - 0x11C000
++						   Multi-user RAM */
++	u8			res17[0x24000];	/* 0x11C000 - 0x140000 */
++	u8			res18[0xC0000];	/* 0x140000 - 0x200000 */
++} __packed;
++
++extern struct qe_immap __iomem *qe_immr;
++extern phys_addr_t get_qe_base(void);
++
++/*
++ * Returns the offset within the QE address space of the given pointer.
++ *
++ * Note that the QE does not support 36-bit physical addresses, so if
++ * get_qe_base() returns a number above 4GB, the caller will probably fail.
++ */
++static inline phys_addr_t immrbar_virt_to_phys(void *address)
++{
++	void *q = (void *)qe_immr;
++
++	/* Is it a MURAM address? */
++	if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
++		return get_qe_base() + (address - q);
++
++	/* It's an address returned by kmalloc */
++	return virt_to_phys(address);
++}
++
++#endif /* __KERNEL__ */
++#endif /* _ASM_POWERPC_IMMAP_QE_H */
+diff --git a/include/linux/fsl/qe.h b/include/linux/fsl/qe.h
+new file mode 100644
+index 0000000..ef4422c
+--- /dev/null
++++ b/include/linux/fsl/qe.h
+@@ -0,0 +1,810 @@
++/*
++ * Copyright (C) 2006, 2012 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Authors:	Shlomi Gridish <gridish at freescale.com>
++ *		Li Yang <leoli at freescale.com>
++ *
++ * Description:
++ * QUICC Engine (QE) external definitions and structure.
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef _ASM_POWERPC_QE_H
++#define _ASM_POWERPC_QE_H
++#ifdef __KERNEL__
++
++#include <linux/spinlock.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/fsl/immap_qe.h>
++
++#define QE_NUM_OF_SNUM	256	/* There are 256 serial number in QE */
++#define QE_NUM_OF_BRGS	16
++#define QE_NUM_OF_PORTS	1024
++
++/* Memory partitions
++*/
++#define MEM_PART_SYSTEM		0
++#define MEM_PART_SECONDARY	1
++#define MEM_PART_MURAM		2
++
++extern int siram_init_flag;
++
++/* Clocks and BRGs */
++enum qe_clock {
++	QE_CLK_NONE = 0,
++	QE_BRG1,		/* Baud Rate Generator 1 */
++	QE_BRG2,		/* Baud Rate Generator 2 */
++	QE_BRG3,		/* Baud Rate Generator 3 */
++	QE_BRG4,		/* Baud Rate Generator 4 */
++	QE_BRG5,		/* Baud Rate Generator 5 */
++	QE_BRG6,		/* Baud Rate Generator 6 */
++	QE_BRG7,		/* Baud Rate Generator 7 */
++	QE_BRG8,		/* Baud Rate Generator 8 */
++	QE_BRG9,		/* Baud Rate Generator 9 */
++	QE_BRG10,		/* Baud Rate Generator 10 */
++	QE_BRG11,		/* Baud Rate Generator 11 */
++	QE_BRG12,		/* Baud Rate Generator 12 */
++	QE_BRG13,		/* Baud Rate Generator 13 */
++	QE_BRG14,		/* Baud Rate Generator 14 */
++	QE_BRG15,		/* Baud Rate Generator 15 */
++	QE_BRG16,		/* Baud Rate Generator 16 */
++	QE_CLK1,		/* Clock 1 */
++	QE_CLK2,		/* Clock 2 */
++	QE_CLK3,		/* Clock 3 */
++	QE_CLK4,		/* Clock 4 */
++	QE_CLK5,		/* Clock 5 */
++	QE_CLK6,		/* Clock 6 */
++	QE_CLK7,		/* Clock 7 */
++	QE_CLK8,		/* Clock 8 */
++	QE_CLK9,		/* Clock 9 */
++	QE_CLK10,		/* Clock 10 */
++	QE_CLK11,		/* Clock 11 */
++	QE_CLK12,		/* Clock 12 */
++	QE_CLK13,		/* Clock 13 */
++	QE_CLK14,		/* Clock 14 */
++	QE_CLK15,		/* Clock 15 */
++	QE_CLK16,		/* Clock 16 */
++	QE_CLK17,		/* Clock 17 */
++	QE_CLK18,		/* Clock 18 */
++	QE_CLK19,		/* Clock 19 */
++	QE_CLK20,		/* Clock 20 */
++	QE_CLK21,		/* Clock 21 */
++	QE_CLK22,		/* Clock 22 */
++	QE_CLK23,		/* Clock 23 */
++	QE_CLK24,		/* Clock 24 */
++	QE_RSYNC_PIN,		/* RSYNC from pin */
++	QE_TSYNC_PIN,		/* TSYNC from pin */
++	QE_CLK_DUMMY
++};
++
++static inline bool qe_clock_is_brg(enum qe_clock clk)
++{
++	return clk >= QE_BRG1 && clk <= QE_BRG16;
++}
++
++extern spinlock_t cmxgcr_lock;
++
++/* Export QE common operations */
++#ifdef CONFIG_QUICC_ENGINE
++extern void qe_reset(void);
++#else
++static inline void qe_reset(void) {}
++#endif
++
++/* QE PIO */
++#define QE_PIO_PINS 32
++
++struct qe_pio_regs {
++	__be32	cpodr;		/* Open drain register */
++	__be32	cpdata;		/* Data register */
++	__be32	cpdir1;		/* Direction register */
++	__be32	cpdir2;		/* Direction register */
++	__be32	cppar1;		/* Pin assignment register */
++	__be32	cppar2;		/* Pin assignment register */
++#ifdef CONFIG_PPC_85xx
++	u8	pad[8];
++#endif
++};
++
++#define QE_PIO_DIR_IN	2
++#define QE_PIO_DIR_OUT	1
++extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
++				int dir, int open_drain, int assignment,
++				int has_irq);
++#ifdef CONFIG_QUICC_ENGINE
++extern int par_io_init(struct device_node *np);
++extern int par_io_of_config(struct device_node *np);
++extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
++			     int assignment, int has_irq);
++extern int par_io_data_set(u8 port, u8 pin, u8 val);
++#else
++static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
++static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
++static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
++		int assignment, int has_irq) { return -ENOSYS; }
++static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
++#endif /* CONFIG_QUICC_ENGINE */
++
++/*
++ * Pin multiplexing functions.
++ */
++struct qe_pin;
++#ifdef CONFIG_QE_GPIO
++extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
++extern void qe_pin_free(struct qe_pin *qe_pin);
++extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
++extern void qe_pin_set_dedicated(struct qe_pin *pin);
++#else
++static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
++{
++	return ERR_PTR(-ENOSYS);
++}
++static inline void qe_pin_free(struct qe_pin *qe_pin) {}
++static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
++static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
++#endif /* CONFIG_QE_GPIO */
++
++#ifdef CONFIG_QUICC_ENGINE
++int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
++#else
++static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
++			       u32 cmd_input)
++{
++	return -ENOSYS;
++}
++#endif /* CONFIG_QUICC_ENGINE */
++
++/* QE internal API */
++enum qe_clock qe_clock_source(const char *source);
++unsigned int qe_get_brg_clk(void);
++int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
++int qe_get_snum(void);
++void qe_put_snum(u8 snum);
++unsigned int qe_get_num_of_risc(void);
++unsigned int qe_get_num_of_snums(void);
++
++static inline int qe_alive_during_sleep(void)
++{
++	/*
++	 * MPC8568E reference manual says:
++	 *
++	 * "...power down sequence waits for all I/O interfaces to become idle.
++	 *  In some applications this may happen eventually without actively
++	 *  shutting down interfaces, but most likely, software will have to
++	 *  take steps to shut down the eTSEC, QUICC Engine Block, and PCI
++	 *  interfaces before issuing the command (either the write to the core
++	 *  MSR[WE] as described above or writing to POWMGTCSR) to put the
++	 *  device into sleep state."
++	 *
++	 * MPC8569E reference manual has a similar paragraph.
++	 */
++#ifdef CONFIG_PPC_85xx
++	return 0;
++#else
++	return 1;
++#endif
++}
++
++int qe_muram_init(void);
++
++#if defined(CONFIG_QUICC_ENGINE)
++unsigned long qe_muram_alloc(unsigned long size, unsigned long align);
++int qe_muram_free(unsigned long offset);
++unsigned long qe_muram_alloc_fixed(unsigned long offset, unsigned long size);
++void __iomem *qe_muram_addr(unsigned long offset);
++unsigned long qe_muram_offset(void __iomem *addr);
++dma_addr_t qe_muram_dma(void __iomem *addr);
++#else
++static inline unsigned long qe_muram_alloc(unsigned long size,
++					    unsigned long align)
++{
++	return -ENOSYS;
++}
++
++static inline int qe_muram_free(unsigned long offset)
++{
++	return -ENOSYS;
++}
++
++static inline unsigned long qe_muram_alloc_fixed(unsigned long offset,
++						  unsigned long size)
++{
++	return -ENOSYS;
++}
++
++static inline void __iomem *qe_muram_addr(unsigned long offset)
++{
++	return NULL;
++}
++
++static inline unsigned long qe_muram_offset(void __iomem *addr)
++{
++	return -ENOSYS;
++}
++
++static inline dma_addr_t qe_muram_dma(void __iomem *addr)
++{
++	return 0;
++}
++#endif /* defined(CONFIG_QUICC_ENGINE) */
++
++/* Structure that defines QE firmware binary files.
++ *
++ * See Documentation/powerpc/qe_firmware.txt for a description of these
++ * fields.
++ */
++struct qe_firmware {
++	struct qe_header {
++		__be32 length;  /* Length of the entire structure, in bytes */
++		u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
++		u8 version;     /* Version of this layout. First ver is '1' */
++	} header;
++	u8 id[62];      /* Null-terminated identifier string */
++	u8 split;	/* 0 = shared I-RAM, 1 = split I-RAM */
++	u8 count;       /* Number of microcode[] structures */
++	struct {
++		__be16 model;		/* The SOC model  */
++		u8 major;		/* The SOC revision major */
++		u8 minor;		/* The SOC revision minor */
++	} __packed soc;
++	u8 padding[4];			/* Reserved, for alignment */
++	__be64 extended_modes;		/* Extended modes */
++	__be32 vtraps[8];		/* Virtual trap addresses */
++	u8 reserved[4];			/* Reserved, for future expansion */
++	struct qe_microcode {
++		u8 id[32];		/* Null-terminated identifier */
++		__be32 traps[16];       /* Trap addresses, 0 == ignore */
++		__be32 eccr;		/* The value for the ECCR register */
++		__be32 iram_offset;     /* Offset into I-RAM for the code */
++		__be32 count;		/* Number of 32-bit words of the code */
++		__be32 code_offset;     /* Offset of the actual microcode */
++		u8 major;		/* The microcode version major */
++		u8 minor;		/* The microcode version minor */
++		u8 revision;		/* The microcode version revision */
++		u8 padding;		/* Reserved, for alignment */
++		u8 reserved[4];		/* Reserved, for future expansion */
++	} __packed microcode[1];
++	/* All microcode binaries should be located here */
++	/* CRC32 should be located here, after the microcode binaries */
++} __packed;
++
++struct qe_firmware_info {
++	char id[64];		/* Firmware name */
++	u32 vtraps[8];		/* Virtual trap addresses */
++	u64 extended_modes;	/* Extended modes */
++};
++
++#ifdef CONFIG_QUICC_ENGINE
++/* Upload a firmware to the QE */
++int qe_upload_firmware(const struct qe_firmware *firmware);
++#else
++static inline int qe_upload_firmware(const struct qe_firmware *firmware)
++{
++	return -ENOSYS;
++}
++#endif /* CONFIG_QUICC_ENGINE */
++
++/* Obtain information on the uploaded firmware */
++struct qe_firmware_info *qe_get_firmware_info(void);
++
++/* QE USB */
++int qe_usb_clock_set(enum qe_clock clk, int rate);
++
++/* Buffer descriptors */
++struct qe_bd {
++	__be16 status;
++	__be16 length;
++	__be32 buf;
++} __packed;
++
++#define BD_STATUS_MASK	0xffff0000
++#define BD_LENGTH_MASK	0x0000ffff
++
++/* Buffer descriptor control/status used by serial
++ */
++
++#define BD_SC_EMPTY	(0x8000)	/* Receive is empty */
++#define BD_SC_READY	(0x8000)	/* Transmit is ready */
++#define BD_SC_WRAP	(0x2000)	/* Last buffer descriptor */
++#define BD_SC_INTRPT	(0x1000)	/* Interrupt on change */
++#define BD_SC_LAST	(0x0800)	/* Last buffer in frame */
++#define BD_SC_TC	(0x0400)	/* Transmit CRC */
++#define BD_SC_CM	(0x0200)	/* Continuous mode */
++#define BD_SC_ID	(0x0100)	/* Rec'd too many idles */
++#define BD_SC_P		(0x0100)	/* xmt preamble */
++#define BD_SC_BR	(0x0020)	/* Break received */
++#define BD_SC_FR	(0x0010)	/* Framing error */
++#define BD_SC_PR	(0x0008)	/* Parity error */
++#define BD_SC_NAK	(0x0004)	/* NAK - did not respond */
++#define BD_SC_OV	(0x0002)	/* Overrun */
++#define BD_SC_UN	(0x0002)	/* Underrun */
++#define BD_SC_CD	(0x0001)	/* */
++#define BD_SC_CL	(0x0001)	/* Collision */
++
++/* Alignment */
++#define QE_INTR_TABLE_ALIGN	16	/* ??? */
++#define QE_ALIGNMENT_OF_BD	8
++#define QE_ALIGNMENT_OF_PRAM	64
++
++/* RISC allocation */
++#define QE_RISC_ALLOCATION_RISC1	0x1  /* RISC 1 */
++#define QE_RISC_ALLOCATION_RISC2	0x2  /* RISC 2 */
++#define QE_RISC_ALLOCATION_RISC3	0x4  /* RISC 3 */
++#define QE_RISC_ALLOCATION_RISC4	0x8  /* RISC 4 */
++#define QE_RISC_ALLOCATION_RISC1_AND_RISC2	(QE_RISC_ALLOCATION_RISC1 | \
++						 QE_RISC_ALLOCATION_RISC2)
++#define QE_RISC_ALLOCATION_FOUR_RISCS	(QE_RISC_ALLOCATION_RISC1 | \
++					 QE_RISC_ALLOCATION_RISC2 | \
++					 QE_RISC_ALLOCATION_RISC3 | \
++					 QE_RISC_ALLOCATION_RISC4)
++
++/* QE extended filtering Table Lookup Key Size */
++enum qe_fltr_tbl_lookup_key_size {
++	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
++		= 0x3f,		/* LookupKey parsed by the Generate LookupKey
++				   CMD is truncated to 8 bytes */
++	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
++		= 0x5f,		/* LookupKey parsed by the Generate LookupKey
++				   CMD is truncated to 16 bytes */
++};
++
++/* QE FLTR extended filtering Largest External Table Lookup Key Size */
++enum qe_fltr_largest_external_tbl_lookup_key_size {
++	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
++		= 0x0,/* not used */
++	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
++		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,	/* 8 bytes */
++	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
++		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,	/* 16 bytes */
++};
++
++/* structure representing QE parameter RAM */
++struct qe_timer_tables {
++	u16 tm_base;		/* QE timer table base adr */
++	u16 tm_ptr;		/* QE timer table pointer */
++	u16 r_tmr;		/* QE timer mode register */
++	u16 r_tmv;		/* QE timer valid register */
++	u32 tm_cmd;		/* QE timer cmd register */
++	u32 tm_cnt;		/* QE timer internal cnt */
++} __packed;
++
++#define QE_FLTR_TAD_SIZE	8
++
++/* QE extended filtering Termination Action Descriptor (TAD) */
++struct qe_fltr_tad {
++	u8 serialized[QE_FLTR_TAD_SIZE];
++} __packed;
++
++/* Communication Direction */
++enum comm_dir {
++	COMM_DIR_NONE = 0,
++	COMM_DIR_RX = 1,
++	COMM_DIR_TX = 2,
++	COMM_DIR_RX_AND_TX = 3
++};
++
++/* QE CMXUCR Registers.
++ * There are two UCCs represented in each of the four CMXUCR registers.
++ * These values are for the UCC in the LSBs
++ */
++#define QE_CMXUCR_MII_ENET_MNG		0x00007000
++#define QE_CMXUCR_MII_ENET_MNG_SHIFT	12
++#define QE_CMXUCR_GRANT			0x00008000
++#define QE_CMXUCR_TSA			0x00004000
++#define QE_CMXUCR_BKPT			0x00000100
++#define QE_CMXUCR_TX_CLK_SRC_MASK	0x0000000F
++
++/* QE CMXGCR Registers.
++*/
++#define QE_CMXGCR_MII_ENET_MNG		0x00007000
++#define QE_CMXGCR_MII_ENET_MNG_SHIFT	12
++#define QE_CMXGCR_USBCS			0x0000000f
++#define QE_CMXGCR_USBCS_CLK3		0x1
++#define QE_CMXGCR_USBCS_CLK5		0x2
++#define QE_CMXGCR_USBCS_CLK7		0x3
++#define QE_CMXGCR_USBCS_CLK9		0x4
++#define QE_CMXGCR_USBCS_CLK13		0x5
++#define QE_CMXGCR_USBCS_CLK17		0x6
++#define QE_CMXGCR_USBCS_CLK19		0x7
++#define QE_CMXGCR_USBCS_CLK21		0x8
++#define QE_CMXGCR_USBCS_BRG9		0x9
++#define QE_CMXGCR_USBCS_BRG10		0xa
++
++/* QE CECR Commands.
++*/
++#define QE_CR_FLG			0x00010000
++#define QE_RESET			0x80000000
++#define QE_INIT_TX_RX			0x00000000
++#define QE_INIT_RX			0x00000001
++#define QE_INIT_TX			0x00000002
++#define QE_ENTER_HUNT_MODE		0x00000003
++#define QE_STOP_TX			0x00000004
++#define QE_GRACEFUL_STOP_TX		0x00000005
++#define QE_RESTART_TX			0x00000006
++#define QE_CLOSE_RX_BD			0x00000007
++#define QE_SWITCH_COMMAND		0x00000007
++#define QE_SET_GROUP_ADDRESS		0x00000008
++#define QE_START_IDMA			0x00000009
++#define QE_MCC_STOP_RX			0x00000009
++#define QE_ATM_TRANSMIT			0x0000000a
++#define QE_HPAC_CLEAR_ALL		0x0000000b
++#define QE_GRACEFUL_STOP_RX		0x0000001a
++#define QE_RESTART_RX			0x0000001b
++#define QE_HPAC_SET_PRIORITY		0x0000010b
++#define QE_HPAC_STOP_TX			0x0000020b
++#define QE_HPAC_STOP_RX			0x0000030b
++#define QE_HPAC_GRACEFUL_STOP_TX	0x0000040b
++#define QE_HPAC_GRACEFUL_STOP_RX	0x0000050b
++#define QE_HPAC_START_TX		0x0000060b
++#define QE_HPAC_START_RX		0x0000070b
++#define QE_USB_STOP_TX			0x0000000a
++#define QE_USB_RESTART_TX		0x0000000c
++#define QE_QMC_STOP_TX			0x0000000c
++#define QE_QMC_STOP_RX			0x0000000d
++#define QE_SS7_SU_FIL_RESET		0x0000000e
++/* jonathbr added from here down for 83xx */
++#define QE_RESET_BCS			0x0000000a
++#define QE_MCC_INIT_TX_RX_16		0x00000003
++#define QE_MCC_STOP_TX			0x00000004
++#define QE_MCC_INIT_TX_1		0x00000005
++#define QE_MCC_INIT_RX_1		0x00000006
++#define QE_MCC_RESET			0x00000007
++#define QE_SET_TIMER			0x00000008
++#define QE_RANDOM_NUMBER		0x0000000c
++#define QE_ATM_MULTI_THREAD_INIT	0x00000011
++#define QE_ASSIGN_PAGE			0x00000012
++#define QE_ADD_REMOVE_HASH_ENTRY	0x00000013
++#define QE_START_FLOW_CONTROL		0x00000014
++#define QE_STOP_FLOW_CONTROL		0x00000015
++#define QE_ASSIGN_PAGE_TO_DEVICE	0x00000016
++
++#define QE_ASSIGN_RISC			0x00000010
++#define QE_CR_MCN_NORMAL_SHIFT		6
++#define QE_CR_MCN_USB_SHIFT		4
++#define QE_CR_MCN_RISC_ASSIGN_SHIFT	8
++#define QE_CR_SNUM_SHIFT		17
++
++/* QE CECR Sub Block - sub block of QE command.
++*/
++#define QE_CR_SUBBLOCK_INVALID		0x00000000
++#define QE_CR_SUBBLOCK_USB		0x03200000
++#define QE_CR_SUBBLOCK_UCCFAST1		0x02000000
++#define QE_CR_SUBBLOCK_UCCFAST2		0x02200000
++#define QE_CR_SUBBLOCK_UCCFAST3		0x02400000
++#define QE_CR_SUBBLOCK_UCCFAST4		0x02600000
++#define QE_CR_SUBBLOCK_UCCFAST5		0x02800000
++#define QE_CR_SUBBLOCK_UCCFAST6		0x02a00000
++#define QE_CR_SUBBLOCK_UCCFAST7		0x02c00000
++#define QE_CR_SUBBLOCK_UCCFAST8		0x02e00000
++#define QE_CR_SUBBLOCK_UCCSLOW1		0x00000000
++#define QE_CR_SUBBLOCK_UCCSLOW2		0x00200000
++#define QE_CR_SUBBLOCK_UCCSLOW3		0x00400000
++#define QE_CR_SUBBLOCK_UCCSLOW4		0x00600000
++#define QE_CR_SUBBLOCK_UCCSLOW5		0x00800000
++#define QE_CR_SUBBLOCK_UCCSLOW6		0x00a00000
++#define QE_CR_SUBBLOCK_UCCSLOW7		0x00c00000
++#define QE_CR_SUBBLOCK_UCCSLOW8		0x00e00000
++#define QE_CR_SUBBLOCK_MCC1		0x03800000
++#define QE_CR_SUBBLOCK_MCC2		0x03a00000
++#define QE_CR_SUBBLOCK_MCC3		0x03000000
++#define QE_CR_SUBBLOCK_IDMA1		0x02800000
++#define QE_CR_SUBBLOCK_IDMA2		0x02a00000
++#define QE_CR_SUBBLOCK_IDMA3		0x02c00000
++#define QE_CR_SUBBLOCK_IDMA4		0x02e00000
++#define QE_CR_SUBBLOCK_HPAC		0x01e00000
++#define QE_CR_SUBBLOCK_SPI1		0x01400000
++#define QE_CR_SUBBLOCK_SPI2		0x01600000
++#define QE_CR_SUBBLOCK_RAND		0x01c00000
++#define QE_CR_SUBBLOCK_TIMER		0x01e00000
++#define QE_CR_SUBBLOCK_GENERAL		0x03c00000
++
++/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
++#define QE_CR_PROTOCOL_UNSPECIFIED	0x00	/* For all other protocols */
++#define QE_CR_PROTOCOL_HDLC_TRANSPARENT	0x00
++#define QE_CR_PROTOCOL_QMC		0x02
++#define QE_CR_PROTOCOL_UART		0x04
++#define QE_CR_PROTOCOL_ATM_POS		0x0A
++#define QE_CR_PROTOCOL_ETHERNET		0x0C
++#define QE_CR_PROTOCOL_L2_SWITCH	0x0D
++
++/* BRG configuration register */
++#define QE_BRGC_ENABLE		0x00010000
++#define QE_BRGC_DIVISOR_SHIFT	1
++#define QE_BRGC_DIVISOR_MAX	0xFFF
++#define QE_BRGC_DIV16		1
++
++/* QE Timers registers */
++#define QE_GTCFR1_PCAS	0x80
++#define QE_GTCFR1_STP2	0x20
++#define QE_GTCFR1_RST2	0x10
++#define QE_GTCFR1_GM2	0x08
++#define QE_GTCFR1_GM1	0x04
++#define QE_GTCFR1_STP1	0x02
++#define QE_GTCFR1_RST1	0x01
++
++/* SDMA registers */
++#define QE_SDSR_BER1	0x02000000
++#define QE_SDSR_BER2	0x01000000
++
++#define QE_SDMR_GLB_1_MSK	0x80000000
++#define QE_SDMR_ADR_SEL		0x20000000
++#define QE_SDMR_BER1_MSK	0x02000000
++#define QE_SDMR_BER2_MSK	0x01000000
++#define QE_SDMR_EB1_MSK		0x00800000
++#define QE_SDMR_ER1_MSK		0x00080000
++#define QE_SDMR_ER2_MSK		0x00040000
++#define QE_SDMR_CEN_MASK	0x0000E000
++#define QE_SDMR_SBER_1		0x00000200
++#define QE_SDMR_SBER_2		0x00000200
++#define QE_SDMR_EB1_PR_MASK	0x000000C0
++#define QE_SDMR_ER1_PR		0x00000008
++
++#define QE_SDMR_CEN_SHIFT	13
++#define QE_SDMR_EB1_PR_SHIFT	6
++
++#define QE_SDTM_MSNUM_SHIFT	24
++
++#define QE_SDEBCR_BA_MASK	0x01FFFFFF
++
++/* Communication Processor */
++#define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
++#define QE_CP_CERCR_IEE		0x4000	/* Instruction RAM ECC enable */
++#define QE_CP_CERCR_CIR		0x0800	/* Common instruction RAM */
++
++/* I-RAM */
++#define QE_IRAM_IADD_AIE	0x80000000	/* Auto Increment Enable */
++#define QE_IRAM_IADD_BADDR	0x00080000	/* Base Address */
++#define QE_IRAM_READY           0x80000000      /* Ready */
++
++/* UPC */
++#define UPGCR_PROTOCOL	0x80000000	/* protocol ul2 or pl2 */
++#define UPGCR_TMS	0x40000000	/* Transmit master/slave mode */
++#define UPGCR_RMS	0x20000000	/* Receive master/slave mode */
++#define UPGCR_ADDR	0x10000000	/* Master MPHY Addr multiplexing */
++#define UPGCR_DIAG	0x01000000	/* Diagnostic mode */
++
++/* UCC GUEMR register */
++#define UCC_GUEMR_MODE_MASK_RX	0x02
++#define UCC_GUEMR_MODE_FAST_RX	0x02
++#define UCC_GUEMR_MODE_SLOW_RX	0x00
++#define UCC_GUEMR_MODE_MASK_TX	0x01
++#define UCC_GUEMR_MODE_FAST_TX	0x01
++#define UCC_GUEMR_MODE_SLOW_TX	0x00
++#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
++#define UCC_GUEMR_SET_RESERVED3	0x10	/* Bit 3 in the guemr is reserved but
++					   must be set 1 */
++
++/* structure representing UCC SLOW parameter RAM */
++struct ucc_slow_pram {
++	__be16 rbase;		/* RX BD base address */
++	__be16 tbase;		/* TX BD base address */
++	u8 rbmr;		/* RX bus mode register (same as CPM's RFCR) */
++	u8 tbmr;		/* TX bus mode register (same as CPM's TFCR) */
++	__be16 mrblr;		/* Rx buffer length */
++	__be32 rstate;		/* Rx internal state */
++	__be32 rptr;		/* Rx internal data pointer */
++	__be16 rbptr;		/* rb BD Pointer */
++	__be16 rcount;		/* Rx internal byte count */
++	__be32 rtemp;		/* Rx temp */
++	__be32 tstate;		/* Tx internal state */
++	__be32 tptr;		/* Tx internal data pointer */
++	__be16 tbptr;		/* Tx BD pointer */
++	__be16 tcount;		/* Tx byte count */
++	__be32 ttemp;		/* Tx temp */
++	__be32 rcrc;		/* temp receive CRC */
++	__be32 tcrc;		/* temp transmit CRC */
++} __packed;
++
++/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
++#define UCC_SLOW_GUMR_H_SAM_QMC		0x00000000
++#define UCC_SLOW_GUMR_H_SAM_SATM	0x00008000
++#define UCC_SLOW_GUMR_H_REVD		0x00002000
++#define UCC_SLOW_GUMR_H_TRX		0x00001000
++#define UCC_SLOW_GUMR_H_TTX		0x00000800
++#define UCC_SLOW_GUMR_H_CDP		0x00000400
++#define UCC_SLOW_GUMR_H_CTSP		0x00000200
++#define UCC_SLOW_GUMR_H_CDS		0x00000100
++#define UCC_SLOW_GUMR_H_CTSS		0x00000080
++#define UCC_SLOW_GUMR_H_TFL		0x00000040
++#define UCC_SLOW_GUMR_H_RFW		0x00000020
++#define UCC_SLOW_GUMR_H_TXSY		0x00000010
++#define UCC_SLOW_GUMR_H_4SYNC		0x00000004
++#define UCC_SLOW_GUMR_H_8SYNC		0x00000008
++#define UCC_SLOW_GUMR_H_16SYNC		0x0000000c
++#define UCC_SLOW_GUMR_H_RTSM		0x00000002
++#define UCC_SLOW_GUMR_H_RSYN		0x00000001
++
++#define UCC_SLOW_GUMR_L_TCI		0x10000000
++#define UCC_SLOW_GUMR_L_RINV		0x02000000
++#define UCC_SLOW_GUMR_L_TINV		0x01000000
++#define UCC_SLOW_GUMR_L_TEND		0x00040000
++#define UCC_SLOW_GUMR_L_TDCR_MASK	0x00030000
++#define UCC_SLOW_GUMR_L_TDCR_32	        0x00030000
++#define UCC_SLOW_GUMR_L_TDCR_16	        0x00020000
++#define UCC_SLOW_GUMR_L_TDCR_8	        0x00010000
++#define UCC_SLOW_GUMR_L_TDCR_1	        0x00000000
++#define UCC_SLOW_GUMR_L_RDCR_MASK	0x0000c000
++#define UCC_SLOW_GUMR_L_RDCR_32		0x0000c000
++#define UCC_SLOW_GUMR_L_RDCR_16	        0x00008000
++#define UCC_SLOW_GUMR_L_RDCR_8	        0x00004000
++#define UCC_SLOW_GUMR_L_RDCR_1		0x00000000
++#define UCC_SLOW_GUMR_L_RENC_NRZI	0x00000800
++#define UCC_SLOW_GUMR_L_RENC_NRZ	0x00000000
++#define UCC_SLOW_GUMR_L_TENC_NRZI	0x00000100
++#define UCC_SLOW_GUMR_L_TENC_NRZ	0x00000000
++#define UCC_SLOW_GUMR_L_DIAG_MASK	0x000000c0
++#define UCC_SLOW_GUMR_L_DIAG_LE	        0x000000c0
++#define UCC_SLOW_GUMR_L_DIAG_ECHO	0x00000080
++#define UCC_SLOW_GUMR_L_DIAG_LOOP	0x00000040
++#define UCC_SLOW_GUMR_L_DIAG_NORM	0x00000000
++#define UCC_SLOW_GUMR_L_ENR		0x00000020
++#define UCC_SLOW_GUMR_L_ENT		0x00000010
++#define UCC_SLOW_GUMR_L_MODE_MASK	0x0000000F
++#define UCC_SLOW_GUMR_L_MODE_BISYNC	0x00000008
++#define UCC_SLOW_GUMR_L_MODE_AHDLC	0x00000006
++#define UCC_SLOW_GUMR_L_MODE_UART	0x00000004
++#define UCC_SLOW_GUMR_L_MODE_QMC	0x00000002
++
++/* General UCC FAST Mode Register */
++#define UCC_FAST_GUMR_TCI	0x20000000
++#define UCC_FAST_GUMR_TRX	0x10000000
++#define UCC_FAST_GUMR_TTX	0x08000000
++#define UCC_FAST_GUMR_CDP	0x04000000
++#define UCC_FAST_GUMR_CTSP	0x02000000
++#define UCC_FAST_GUMR_CDS	0x01000000
++#define UCC_FAST_GUMR_CTSS	0x00800000
++#define UCC_FAST_GUMR_TXSY	0x00020000
++#define UCC_FAST_GUMR_RSYN	0x00010000
++#define UCC_FAST_GUMR_RTSM	0x00002000
++#define UCC_FAST_GUMR_REVD	0x00000400
++#define UCC_FAST_GUMR_ENR	0x00000020
++#define UCC_FAST_GUMR_ENT	0x00000010
++
++/* UART Slow UCC Event Register (UCCE) */
++#define UCC_UART_UCCE_AB	0x0200
++#define UCC_UART_UCCE_IDLE	0x0100
++#define UCC_UART_UCCE_GRA	0x0080
++#define UCC_UART_UCCE_BRKE	0x0040
++#define UCC_UART_UCCE_BRKS	0x0020
++#define UCC_UART_UCCE_CCR	0x0008
++#define UCC_UART_UCCE_BSY	0x0004
++#define UCC_UART_UCCE_TX	0x0002
++#define UCC_UART_UCCE_RX	0x0001
++
++/* HDLC Slow UCC Event Register (UCCE) */
++#define UCC_HDLC_UCCE_GLR	0x1000
++#define UCC_HDLC_UCCE_GLT	0x0800
++#define UCC_HDLC_UCCE_IDLE	0x0100
++#define UCC_HDLC_UCCE_BRKE	0x0040
++#define UCC_HDLC_UCCE_BRKS	0x0020
++#define UCC_HDLC_UCCE_TXE	0x0010
++#define UCC_HDLC_UCCE_RXF	0x0008
++#define UCC_HDLC_UCCE_BSY	0x0004
++#define UCC_HDLC_UCCE_TXB	0x0002
++#define UCC_HDLC_UCCE_RXB	0x0001
++
++/* BISYNC Slow UCC Event Register (UCCE) */
++#define UCC_BISYNC_UCCE_GRA	0x0080
++#define UCC_BISYNC_UCCE_TXE	0x0010
++#define UCC_BISYNC_UCCE_RCH	0x0008
++#define UCC_BISYNC_UCCE_BSY	0x0004
++#define UCC_BISYNC_UCCE_TXB	0x0002
++#define UCC_BISYNC_UCCE_RXB	0x0001
++
++/* Transparent UCC Event Register (UCCE) */
++#define UCC_TRANS_UCCE_GRA	0x0080
++#define UCC_TRANS_UCCE_TXE	0x0010
++#define UCC_TRANS_UCCE_RXF	0x0008
++#define UCC_TRANS_UCCE_BSY	0x0004
++#define UCC_TRANS_UCCE_TXB	0x0002
++#define UCC_TRANS_UCCE_RXB	0x0001
++
++
++/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
++#define UCC_GETH_UCCE_MPD       0x80000000
++#define UCC_GETH_UCCE_SCAR      0x40000000
++#define UCC_GETH_UCCE_GRA       0x20000000
++#define UCC_GETH_UCCE_CBPR      0x10000000
++#define UCC_GETH_UCCE_BSY       0x08000000
++#define UCC_GETH_UCCE_RXC       0x04000000
++#define UCC_GETH_UCCE_TXC       0x02000000
++#define UCC_GETH_UCCE_TXE       0x01000000
++#define UCC_GETH_UCCE_TXB7      0x00800000
++#define UCC_GETH_UCCE_TXB6      0x00400000
++#define UCC_GETH_UCCE_TXB5      0x00200000
++#define UCC_GETH_UCCE_TXB4      0x00100000
++#define UCC_GETH_UCCE_TXB3      0x00080000
++#define UCC_GETH_UCCE_TXB2      0x00040000
++#define UCC_GETH_UCCE_TXB1      0x00020000
++#define UCC_GETH_UCCE_TXB0      0x00010000
++#define UCC_GETH_UCCE_RXB7      0x00008000
++#define UCC_GETH_UCCE_RXB6      0x00004000
++#define UCC_GETH_UCCE_RXB5      0x00002000
++#define UCC_GETH_UCCE_RXB4      0x00001000
++#define UCC_GETH_UCCE_RXB3      0x00000800
++#define UCC_GETH_UCCE_RXB2      0x00000400
++#define UCC_GETH_UCCE_RXB1      0x00000200
++#define UCC_GETH_UCCE_RXB0      0x00000100
++#define UCC_GETH_UCCE_RXF7      0x00000080
++#define UCC_GETH_UCCE_RXF6      0x00000040
++#define UCC_GETH_UCCE_RXF5      0x00000020
++#define UCC_GETH_UCCE_RXF4      0x00000010
++#define UCC_GETH_UCCE_RXF3      0x00000008
++#define UCC_GETH_UCCE_RXF2      0x00000004
++#define UCC_GETH_UCCE_RXF1      0x00000002
++#define UCC_GETH_UCCE_RXF0      0x00000001
++
++/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
++#define UCC_UART_UPSMR_FLC		0x8000
++#define UCC_UART_UPSMR_SL		0x4000
++#define UCC_UART_UPSMR_CL_MASK		0x3000
++#define UCC_UART_UPSMR_CL_8		0x3000
++#define UCC_UART_UPSMR_CL_7		0x2000
++#define UCC_UART_UPSMR_CL_6		0x1000
++#define UCC_UART_UPSMR_CL_5		0x0000
++#define UCC_UART_UPSMR_UM_MASK		0x0c00
++#define UCC_UART_UPSMR_UM_NORMAL	0x0000
++#define UCC_UART_UPSMR_UM_MAN_MULTI	0x0400
++#define UCC_UART_UPSMR_UM_AUTO_MULTI	0x0c00
++#define UCC_UART_UPSMR_FRZ		0x0200
++#define UCC_UART_UPSMR_RZS		0x0100
++#define UCC_UART_UPSMR_SYN		0x0080
++#define UCC_UART_UPSMR_DRT		0x0040
++#define UCC_UART_UPSMR_PEN		0x0010
++#define UCC_UART_UPSMR_RPM_MASK		0x000c
++#define UCC_UART_UPSMR_RPM_ODD		0x0000
++#define UCC_UART_UPSMR_RPM_LOW		0x0004
++#define UCC_UART_UPSMR_RPM_EVEN		0x0008
++#define UCC_UART_UPSMR_RPM_HIGH		0x000C
++#define UCC_UART_UPSMR_TPM_MASK		0x0003
++#define UCC_UART_UPSMR_TPM_ODD		0x0000
++#define UCC_UART_UPSMR_TPM_LOW		0x0001
++#define UCC_UART_UPSMR_TPM_EVEN		0x0002
++#define UCC_UART_UPSMR_TPM_HIGH		0x0003
++
++/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
++#define UCC_GETH_UPSMR_FTFE     0x80000000
++#define UCC_GETH_UPSMR_PTPE     0x40000000
++#define UCC_GETH_UPSMR_ECM      0x04000000
++#define UCC_GETH_UPSMR_HSE      0x02000000
++#define UCC_GETH_UPSMR_PRO      0x00400000
++#define UCC_GETH_UPSMR_CAP      0x00200000
++#define UCC_GETH_UPSMR_RSH      0x00100000
++#define UCC_GETH_UPSMR_RPM      0x00080000
++#define UCC_GETH_UPSMR_R10M     0x00040000
++#define UCC_GETH_UPSMR_RLPB     0x00020000
++#define UCC_GETH_UPSMR_TBIM     0x00010000
++#define UCC_GETH_UPSMR_RES1     0x00002000
++#define UCC_GETH_UPSMR_RMM      0x00001000
++#define UCC_GETH_UPSMR_CAM      0x00000400
++#define UCC_GETH_UPSMR_BRO      0x00000200
++#define UCC_GETH_UPSMR_SMM	0x00000080
++#define UCC_GETH_UPSMR_SGMM	0x00000020
++
++/* UCC Transmit On Demand Register (UTODR) */
++#define UCC_SLOW_TOD	0x8000
++#define UCC_FAST_TOD	0x8000
++
++/* UCC Bus Mode Register masks */
++/* Not to be confused with the Bundle Mode Register */
++#define UCC_BMR_GBL		0x20
++#define UCC_BMR_BO_BE		0x10
++#define UCC_BMR_CETM		0x04
++#define UCC_BMR_DTB		0x02
++#define UCC_BMR_BDB		0x01
++
++/* Function code masks */
++#define FC_GBL				0x20
++#define FC_DTB_LCL			0x02
++#define UCC_FAST_FUNCTION_CODE_GBL	0x20
++#define UCC_FAST_FUNCTION_CODE_DTB_LCL	0x02
++#define UCC_FAST_FUNCTION_CODE_BDB_LCL	0x01
++
++#endif /* __KERNEL__ */
++#endif /* _ASM_POWERPC_QE_H */
+-- 
+2.1.0.27.g96db324
+
diff --git a/target/linux/layerscape-64b/patches-4.1/0019-fmd-add-SDK1.9-codebase.patch b/target/linux/layerscape-64b/patches-4.1/0019-fmd-add-SDK1.9-codebase.patch
new file mode 100644
index 0000000..7221a56
--- /dev/null
+++ b/target/linux/layerscape-64b/patches-4.1/0019-fmd-add-SDK1.9-codebase.patch
@@ -0,0 +1,115016 @@
+From 47d8021852df758e17bb3e0d6840468c2f68facc Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur at freescale.com>
+Date: Wed, 16 Dec 2015 21:46:52 +0200
+Subject: [PATCH 019/151] fmd: add SDK1.9 codebase
+
+Moved to the sdk_fman folder and renamed Kconfig option to FSL_SDK_FMAN to
+allow for the upstreamable FMan driver to be added in the same tree.
+Added changes needed to adapt to the new kernel.
+
+Signed-off-by: Mandy Lavi <mandy.lavi at freescale.com>
+Signed-off-by: Madalin Bucur <madalin.bucur at freescale.com>
+---
+ drivers/net/ethernet/freescale/Kconfig             |    1 +
+ drivers/net/ethernet/freescale/Makefile            |    1 +
+ drivers/net/ethernet/freescale/sdk_fman/Kconfig    |  146 +
+ drivers/net/ethernet/freescale/sdk_fman/Makefile   |   11 +
+ .../freescale/sdk_fman/Peripherals/FM/HC/Makefile  |   15 +
+ .../freescale/sdk_fman/Peripherals/FM/HC/hc.c      | 1232 ++++
+ .../freescale/sdk_fman/Peripherals/FM/MAC/Makefile |   25 +
+ .../freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c  | 1463 ++++
+ .../freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h  |  228 +
+ .../sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c    |   97 +
+ .../sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h    |   42 +
+ .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c |  646 ++
+ .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h |  224 +
+ .../sdk_fman/Peripherals/FM/MAC/fman_crc32.c       |  119 +
+ .../sdk_fman/Peripherals/FM/MAC/fman_crc32.h       |   43 +
+ .../sdk_fman/Peripherals/FM/MAC/fman_dtsec.c       |  845 +++
+ .../Peripherals/FM/MAC/fman_dtsec_mii_acc.c        |  163 +
+ .../sdk_fman/Peripherals/FM/MAC/fman_memac.c       |  511 ++
+ .../Peripherals/FM/MAC/fman_memac_mii_acc.c        |  213 +
+ .../sdk_fman/Peripherals/FM/MAC/fman_tgec.c        |  367 +
+ .../freescale/sdk_fman/Peripherals/FM/MAC/memac.c  | 1088 +++
+ .../freescale/sdk_fman/Peripherals/FM/MAC/memac.h  |  110 +
+ .../sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c    |   78 +
+ .../sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h    |   73 +
+ .../freescale/sdk_fman/Peripherals/FM/MAC/tgec.c   |  974 +++
+ .../freescale/sdk_fman/Peripherals/FM/MAC/tgec.h   |  151 +
+ .../sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c     |  139 +
+ .../sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h     |   80 +
+ .../sdk_fman/Peripherals/FM/MACSEC/Makefile        |   15 +
+ .../sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c     |  237 +
+ .../sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h     |  203 +
+ .../Peripherals/FM/MACSEC/fm_macsec_guest.c        |   59 +
+ .../Peripherals/FM/MACSEC/fm_macsec_master.c       | 1031 +++
+ .../Peripherals/FM/MACSEC/fm_macsec_master.h       |  479 ++
+ .../Peripherals/FM/MACSEC/fm_macsec_secy.c         |  883 +++
+ .../Peripherals/FM/MACSEC/fm_macsec_secy.h         |  144 +
+ .../freescale/sdk_fman/Peripherals/FM/Makefile     |   23 +
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/Makefile |   23 +
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h  |  360 +
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c  | 7533 ++++++++++++++++++++
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.h  |  399 ++
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.c  | 3242 +++++++++
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.h  |  206 +
+ .../sdk_fman/Peripherals/FM/Pcd/fm_manip.c         | 5564 +++++++++++++++
+ .../sdk_fman/Peripherals/FM/Pcd/fm_manip.h         |  553 ++
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.c | 2094 ++++++
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.h |  543 ++
+ .../sdk_fman/Peripherals/FM/Pcd/fm_pcd_ipc.h       |  280 +
+ .../sdk_fman/Peripherals/FM/Pcd/fm_plcr.c          | 1846 +++++
+ .../sdk_fman/Peripherals/FM/Pcd/fm_plcr.h          |  165 +
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c |  420 ++
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.h |  316 +
+ .../sdk_fman/Peripherals/FM/Pcd/fm_replic.c        |  984 +++
+ .../sdk_fman/Peripherals/FM/Pcd/fm_replic.h        |  101 +
+ .../sdk_fman/Peripherals/FM/Pcd/fman_kg.c          |  888 +++
+ .../sdk_fman/Peripherals/FM/Pcd/fman_prs.c         |  129 +
+ .../sdk_fman/Peripherals/FM/Port/Makefile          |   15 +
+ .../sdk_fman/Peripherals/FM/Port/fm_port.c         | 6436 +++++++++++++++++
+ .../sdk_fman/Peripherals/FM/Port/fm_port.h         |  999 +++
+ .../sdk_fman/Peripherals/FM/Port/fm_port_dsar.h    |  494 ++
+ .../sdk_fman/Peripherals/FM/Port/fm_port_im.c      |  753 ++
+ .../sdk_fman/Peripherals/FM/Port/fman_port.c       | 1568 ++++
+ .../freescale/sdk_fman/Peripherals/FM/Rtc/Makefile |   15 +
+ .../freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c |  692 ++
+ .../freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.h |   96 +
+ .../sdk_fman/Peripherals/FM/Rtc/fman_rtc.c         |  334 +
+ .../freescale/sdk_fman/Peripherals/FM/SP/Makefile  |   15 +
+ .../freescale/sdk_fman/Peripherals/FM/SP/fm_sp.c   |  757 ++
+ .../freescale/sdk_fman/Peripherals/FM/SP/fm_sp.h   |   85 +
+ .../freescale/sdk_fman/Peripherals/FM/SP/fman_sp.c |  197 +
+ .../freescale/sdk_fman/Peripherals/FM/fm.c         | 5191 ++++++++++++++
+ .../freescale/sdk_fman/Peripherals/FM/fm.h         |  646 ++
+ .../freescale/sdk_fman/Peripherals/FM/fm_ipc.h     |  465 ++
+ .../freescale/sdk_fman/Peripherals/FM/fm_muram.c   |  174 +
+ .../freescale/sdk_fman/Peripherals/FM/fman.c       | 1399 ++++
+ .../sdk_fman/Peripherals/FM/inc/fm_common.h        | 1203 ++++
+ .../freescale/sdk_fman/Peripherals/FM/inc/fm_hc.h  |   93 +
+ .../sdk_fman/Peripherals/FM/inc/fm_sp_common.h     |  117 +
+ .../net/ethernet/freescale/sdk_fman/etc/Makefile   |   12 +
+ .../net/ethernet/freescale/sdk_fman/etc/error.c    |   95 +
+ drivers/net/ethernet/freescale/sdk_fman/etc/list.c |   71 +
+ .../net/ethernet/freescale/sdk_fman/etc/memcpy.c   |  601 ++
+ drivers/net/ethernet/freescale/sdk_fman/etc/mm.c   | 1155 +++
+ drivers/net/ethernet/freescale/sdk_fman/etc/mm.h   |  105 +
+ .../net/ethernet/freescale/sdk_fman/etc/sprint.c   |   81 +
+ .../ethernet/freescale/sdk_fman/fmanv3h_dflags.h   |   57 +
+ .../ethernet/freescale/sdk_fman/fmanv3l_dflags.h   |   56 +
+ .../sdk_fman/inc/Peripherals/crc_mac_addr_ext.h    |  364 +
+ .../freescale/sdk_fman/inc/Peripherals/dpaa_ext.h  |  207 +
+ .../freescale/sdk_fman/inc/Peripherals/fm_ext.h    | 1705 +++++
+ .../sdk_fman/inc/Peripherals/fm_mac_ext.h          |  846 +++
+ .../sdk_fman/inc/Peripherals/fm_macsec_ext.h       | 1271 ++++
+ .../sdk_fman/inc/Peripherals/fm_muram_ext.h        |  170 +
+ .../sdk_fman/inc/Peripherals/fm_pcd_ext.h          | 3972 +++++++++++
+ .../sdk_fman/inc/Peripherals/fm_port_ext.h         | 2608 +++++++
+ .../sdk_fman/inc/Peripherals/fm_rtc_ext.h          |  619 ++
+ .../sdk_fman/inc/Peripherals/fm_vsp_ext.h          |  411 ++
+ .../sdk_fman/inc/Peripherals/mii_acc_ext.h         |   76 +
+ .../net/ethernet/freescale/sdk_fman/inc/core_ext.h |   86 +
+ .../freescale/sdk_fman/inc/cores/e500v2_ext.h      |  476 ++
+ .../freescale/sdk_fman/inc/cores/ppc_ext.h         |  141 +
+ .../ethernet/freescale/sdk_fman/inc/ddr_std_ext.h  |   77 +
+ .../ethernet/freescale/sdk_fman/inc/debug_ext.h    |  233 +
+ .../ethernet/freescale/sdk_fman/inc/endian_ext.h   |  447 ++
+ .../net/ethernet/freescale/sdk_fman/inc/enet_ext.h |  205 +
+ .../ethernet/freescale/sdk_fman/inc/error_ext.h    |  529 ++
+ .../ethernet/freescale/sdk_fman/inc/etc/list_ext.h |  358 +
+ .../ethernet/freescale/sdk_fman/inc/etc/mem_ext.h  |  318 +
+ .../freescale/sdk_fman/inc/etc/memcpy_ext.h        |  174 +
+ .../ethernet/freescale/sdk_fman/inc/etc/mm_ext.h   |  310 +
+ .../freescale/sdk_fman/inc/etc/sprint_ext.h        |  118 +
+ .../sdk_fman/inc/flib/common/arch/ppc_access.h     |   37 +
+ .../freescale/sdk_fman/inc/flib/common/general.h   |   51 +
+ .../freescale/sdk_fman/inc/flib/fman_common.h      |   78 +
+ .../freescale/sdk_fman/inc/flib/fsl_enet.h         |  273 +
+ .../freescale/sdk_fman/inc/flib/fsl_fman.h         |  825 +++
+ .../freescale/sdk_fman/inc/flib/fsl_fman_dtsec.h   | 1096 +++
+ .../sdk_fman/inc/flib/fsl_fman_dtsec_mii_acc.h     |  107 +
+ .../freescale/sdk_fman/inc/flib/fsl_fman_kg.h      |  514 ++
+ .../freescale/sdk_fman/inc/flib/fsl_fman_memac.h   |  427 ++
+ .../sdk_fman/inc/flib/fsl_fman_memac_mii_acc.h     |   78 +
+ .../freescale/sdk_fman/inc/flib/fsl_fman_port.h    |  593 ++
+ .../freescale/sdk_fman/inc/flib/fsl_fman_prs.h     |  102 +
+ .../freescale/sdk_fman/inc/flib/fsl_fman_rtc.h     |  449 ++
+ .../freescale/sdk_fman/inc/flib/fsl_fman_sp.h      |  138 +
+ .../freescale/sdk_fman/inc/flib/fsl_fman_tgec.h    |  479 ++
+ .../integrations/FMANV3H/dpaa_integration_ext.h    |  290 +
+ .../sdk_fman/inc/integrations/FMANV3H/part_ext.h   |   71 +
+ .../integrations/FMANV3H/part_integration_ext.h    |  304 +
+ .../integrations/FMANV3L/dpaa_integration_ext.h    |  292 +
+ .../sdk_fman/inc/integrations/FMANV3L/part_ext.h   |   59 +
+ .../integrations/FMANV3L/part_integration_ext.h    |  304 +
+ .../inc/integrations/P1023/dpaa_integration_ext.h  |  213 +
+ .../sdk_fman/inc/integrations/P1023/part_ext.h     |   82 +
+ .../inc/integrations/P1023/part_integration_ext.h  |  635 ++
+ .../P3040_P4080_P5020/dpaa_integration_ext.h       |  276 +
+ .../inc/integrations/P3040_P4080_P5020/part_ext.h  |   83 +
+ .../P3040_P4080_P5020/part_integration_ext.h       |  336 +
+ .../net/ethernet/freescale/sdk_fman/inc/math_ext.h |   99 +
+ .../net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h |  435 ++
+ .../net/ethernet/freescale/sdk_fman/inc/net_ext.h  |  430 ++
+ .../net/ethernet/freescale/sdk_fman/inc/std_ext.h  |   48 +
+ .../ethernet/freescale/sdk_fman/inc/stdarg_ext.h   |   49 +
+ .../ethernet/freescale/sdk_fman/inc/stdlib_ext.h   |  162 +
+ .../ethernet/freescale/sdk_fman/inc/string_ext.h   |   56 +
+ .../ethernet/freescale/sdk_fman/inc/types_ext.h    |  104 +
+ .../ethernet/freescale/sdk_fman/inc/xx_common.h    |   56 +
+ .../net/ethernet/freescale/sdk_fman/inc/xx_ext.h   |  791 ++
+ .../net/ethernet/freescale/sdk_fman/ncsw_config.mk |   47 +
+ .../net/ethernet/freescale/sdk_fman/p1023_dflags.h |   65 +
+ .../freescale/sdk_fman/p3040_4080_5020_dflags.h    |   62 +
+ .../net/ethernet/freescale/sdk_fman/src/Makefile   |   11 +
+ .../freescale/sdk_fman/src/inc/system/sys_ext.h    |  118 +
+ .../freescale/sdk_fman/src/inc/system/sys_io_ext.h |   46 +
+ .../freescale/sdk_fman/src/inc/types_linux.h       |  200 +
+ .../sdk_fman/src/inc/wrapper/fsl_fman_test.h       |   84 +
+ .../sdk_fman/src/inc/wrapper/lnxwrp_exp_sym.h      |  127 +
+ .../sdk_fman/src/inc/wrapper/lnxwrp_fm_ext.h       |  163 +
+ .../sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h     |  919 +++
+ .../ethernet/freescale/sdk_fman/src/inc/xx/xx.h    |   50 +
+ .../freescale/sdk_fman/src/system/Makefile         |   10 +
+ .../freescale/sdk_fman/src/system/sys_io.c         |  171 +
+ .../freescale/sdk_fman/src/wrapper/Makefile        |   19 +
+ .../freescale/sdk_fman/src/wrapper/fman_test.c     | 1665 +++++
+ .../freescale/sdk_fman/src/wrapper/lnxwrp_fm.c     | 2753 +++++++
+ .../freescale/sdk_fman/src/wrapper/lnxwrp_fm.h     |  294 +
+ .../sdk_fman/src/wrapper/lnxwrp_fm_port.c          | 1424 ++++
+ .../sdk_fman/src/wrapper/lnxwrp_ioctls_fm.c        | 4799 +++++++++++++
+ .../sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.c | 1296 ++++
+ .../sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.h |  755 ++
+ .../sdk_fman/src/wrapper/lnxwrp_resources.h        |  121 +
+ .../sdk_fman/src/wrapper/lnxwrp_resources_ut.c     |  191 +
+ .../sdk_fman/src/wrapper/lnxwrp_resources_ut.h     |  144 +
+ .../sdk_fman/src/wrapper/lnxwrp_resources_ut.make  |   28 +
+ .../freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.c  |   60 +
+ .../freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.h  |   60 +
+ .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm.c         | 1855 +++++
+ .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm.h         |  136 +
+ .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.c    | 1255 ++++
+ .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.h    |   56 +
+ .../ethernet/freescale/sdk_fman/src/xx/Makefile    |   11 +
+ .../freescale/sdk_fman/src/xx/module_strings.c     |   45 +
+ .../ethernet/freescale/sdk_fman/src/xx/udivdi3.c   |  132 +
+ .../ethernet/freescale/sdk_fman/src/xx/xx_linux.c  |  887 +++
+ include/uapi/linux/fmd/Kbuild                      |    5 +
+ include/uapi/linux/fmd/Peripherals/Kbuild          |    4 +
+ include/uapi/linux/fmd/Peripherals/fm_ioctls.h     |  628 ++
+ include/uapi/linux/fmd/Peripherals/fm_pcd_ioctls.h | 3084 ++++++++
+ .../uapi/linux/fmd/Peripherals/fm_port_ioctls.h    |  948 +++
+ .../uapi/linux/fmd/Peripherals/fm_test_ioctls.h    |  208 +
+ include/uapi/linux/fmd/integrations/Kbuild         |    1 +
+ .../linux/fmd/integrations/integration_ioctls.h    |   56 +
+ include/uapi/linux/fmd/ioctls.h                    |   96 +
+ include/uapi/linux/fmd/net_ioctls.h                |  430 ++
+ 194 files changed, 113444 insertions(+)
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Kconfig
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/hc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac.c
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_tgec.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_guest.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_manip.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_manip.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd_ipc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_replic.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_replic.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_kg.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_prs.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_dsar.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_im.c
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fman_port.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fman_rtc.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fm_sp.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fm_sp.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fman_sp.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm_ipc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm_muram.c
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_common.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_hc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_sp_common.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/error.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/list.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/memcpy.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/mm.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/mm.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/sprint.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/fmanv3h_dflags.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/fmanv3l_dflags.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/crc_mac_addr_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/dpaa_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_mac_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_macsec_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_muram_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_pcd_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_port_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_rtc_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_vsp_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/mii_acc_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/core_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/cores/e500v2_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/cores/ppc_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/ddr_std_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/debug_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/endian_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/enet_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/error_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/list_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/mem_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/memcpy_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/mm_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/sprint_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/common/arch/ppc_access.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/common/general.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fman_common.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_enet.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_dtsec.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_dtsec_mii_acc.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_kg.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_memac.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_memac_mii_acc.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_port.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_prs.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_rtc.h
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_sp.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_tgec.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/dpaa_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/part_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/part_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/dpaa_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/part_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/part_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/dpaa_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/part_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/part_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/dpaa_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/part_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/part_integration_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/math_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/net_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/std_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/stdarg_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/stdlib_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/string_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/types_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/xx_common.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/xx_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/p1023_dflags.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/p3040_4080_5020_dflags.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/system/sys_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/system/sys_io_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/types_linux.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/fsl_fman_test.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_exp_sym.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fm_ext.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/xx/xx.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/system/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/system/sys_io.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/fman_test.c
+ create mode 100755 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm_port.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.make
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.h
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/Makefile
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/module_strings.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/udivdi3.c
+ create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/xx_linux.c
+ create mode 100644 include/uapi/linux/fmd/Kbuild
+ create mode 100644 include/uapi/linux/fmd/Peripherals/Kbuild
+ create mode 100644 include/uapi/linux/fmd/Peripherals/fm_ioctls.h
+ create mode 100644 include/uapi/linux/fmd/Peripherals/fm_pcd_ioctls.h
+ create mode 100644 include/uapi/linux/fmd/Peripherals/fm_port_ioctls.h
+ create mode 100644 include/uapi/linux/fmd/Peripherals/fm_test_ioctls.h
+ create mode 100644 include/uapi/linux/fmd/integrations/Kbuild
+ create mode 100644 include/uapi/linux/fmd/integrations/integration_ioctls.h
+ create mode 100644 include/uapi/linux/fmd/ioctls.h
+ create mode 100644 include/uapi/linux/fmd/net_ioctls.h
+
+diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
+index e383dba..536662c 100644
+--- a/drivers/net/ethernet/freescale/Kconfig
++++ b/drivers/net/ethernet/freescale/Kconfig
+@@ -93,4 +93,5 @@ config GIANFAR
+ 	  and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
+ 	  on the 8540.
+ 
++source "drivers/net/ethernet/freescale/sdk_fman/Kconfig"
+ endif # NET_VENDOR_FREESCALE
+diff --git a/drivers/net/ethernet/freescale/Makefile b/drivers/net/ethernet/freescale/Makefile
+index 71debd1..aa64c4e 100644
+--- a/drivers/net/ethernet/freescale/Makefile
++++ b/drivers/net/ethernet/freescale/Makefile
+@@ -17,3 +17,4 @@ gianfar_driver-objs := gianfar.o \
+ 		gianfar_ethtool.o
+ obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
+ ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
++obj-$(if $(CONFIG_FSL_SDK_FMAN),y) += sdk_fman/
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Kconfig b/drivers/net/ethernet/freescale/sdk_fman/Kconfig
+new file mode 100644
+index 0000000..e56e3ec
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Kconfig
+@@ -0,0 +1,146 @@
++menu "Frame Manager support"
++
++menuconfig FSL_SDK_FMAN
++	bool "Freescale Frame Manager (datapath) support - SDK driver"
++	depends on FSL_SOC && FSL_BMAN && FSL_QMAN
++	default y
++	---help---
++		If unsure, say Y.
++
++if FSL_SDK_FMAN
++
++config FSL_SDK_FMAN_TEST
++	bool "FMan test module"
++	default n
++	select FSL_DPAA_HOOKS
++	---help---
++		This option compiles test code for FMan.
++
++menu "FMAN Processor support"
++choice
++	depends on FSL_SDK_FMAN
++	prompt "Processor Type"
++
++config FMAN_P3040_P4080_P5020
++	bool "P3040 P4080 5020"
++
++config FMAN_P1023
++	bool "P1023"
++
++config FMAN_V3H
++	bool "FmanV3H"
++	---help---
++	  Choose "FmanV3H" for Fman rev3H:
++	  B4860, T4240, T4160, etc
++
++config FMAN_V3L
++	bool "FmanV3L"
++	---help---
++	  Choose "FmanV3L" for Fman rev3L:
++	  T1040, T1042, T1020, T1022, T1023, T1024, etc
++
++endchoice
++endmenu
++
++config FMAN_MIB_CNT_OVF_IRQ_EN
++	bool "Enable the dTSEC MIB counters overflow interrupt"
++	default n
++	---help---
++		Enable the dTSEC MIB counters overflow interrupt to get
++		accurate MIB counters values. Enabled it compensates
++		for the counters overflow but reduces performance and
++		triggers error messages in HV setups.
++
++config FSL_FM_MAX_FRAME_SIZE
++	int "Maximum L2 frame size"
++	depends on FSL_SDK_FMAN
++	range 64 9600
++	default "1522"
++	help
++		Configure this in relation to the maximum possible MTU of your
++		network configuration. In particular, one would need to
++		increase this value in order to use jumbo frames.
++		FSL_FM_MAX_FRAME_SIZE must accommodate the Ethernet FCS (4 bytes)
++		and one ETH+VLAN header (18 bytes), to a total of 22 bytes in
++		excess of the desired L3 MTU.
++
++		Note that having too large a FSL_FM_MAX_FRAME_SIZE (much larger
++		than the actual MTU) may lead to buffer exhaustion, especially
++		in the case of badly fragmented datagrams on the Rx path.
++		Conversely, having a FSL_FM_MAX_FRAME_SIZE smaller than the actual
++		MTU will lead to frames being dropped.
++
++		This can be overridden by specifying "fsl_fm_max_frm" in
++		the kernel bootargs:
++		 * in Hypervisor-based scenarios, by adding a "chosen" node
++		with the "bootargs" property specifying
++		"fsl_fm_max_frm=<YourValue>";
++		 * in non-Hypervisor-based scenarios, via u-boot's env, by
++		modifying the "bootargs" env variable.
++
++config FSL_FM_RX_EXTRA_HEADROOM
++	int "Add extra headroom at beginning of data buffers"
++	depends on FSL_SDK_FMAN
++	range 16 384
++	default "64"
++	help
++		Configure this to tell the Frame Manager to reserve some extra
++		space at the beginning of a data buffer on the receive path,
++		before Internal Context fields are copied. This is in addition
++		to the private data area already reserved for driver internal
++		use. The provided value must be a multiple of 16.
++
++		This setting can be overridden by specifying
++		"fsl_fm_rx_extra_headroom" in the kernel bootargs:
++		 * in Hypervisor-based scenarios, by adding a "chosen" node
++		with the "bootargs" property specifying
++		"fsl_fm_rx_extra_headroom=<YourValue>";
++		 * in non-Hypervisor-based scenarios, via u-boot's env, by
++		modifying the "bootargs" env variable.
++
++config FMAN_PFC
++	bool "FMan PFC support (EXPERIMENTAL)"
++	depends on ( FMAN_V3H || FMAN_V3L ) && FSL_SDK_FMAN
++	default n
++	---help---
++	  This option enables PFC support on FMan v3 ports.
++	  Data Center Bridging defines Classes of Service that are
++	  flow-controlled using PFC pause frames.
++
++if FMAN_PFC
++config FMAN_PFC_COS_COUNT
++	int "Number of PFC Classes of Service"
++	depends on FMAN_PFC && FSL_SDK_FMAN
++	range 1 4
++	default "3"
++	---help ---
++	  The number of Classes of Service controlled by PFC.
++
++config FMAN_PFC_QUANTA_0
++	int "The pause quanta for PFC CoS 0"
++	depends on FMAN_PFC && FSL_SDK_FMAN
++	range 0 65535
++	default "65535"
++
++config FMAN_PFC_QUANTA_1
++	int "The pause quanta for PFC CoS 1"
++	depends on FMAN_PFC && FSL_SDK_FMAN
++	range 0 65535
++	default "65535"
++
++config FMAN_PFC_QUANTA_2
++	int "The pause quanta for PFC CoS 2"
++	depends on FMAN_PFC && FSL_SDK_FMAN
++	range 0 65535
++	default "65535"
++
++config FMAN_PFC_QUANTA_3
++	int "The pause quanta for PFC CoS 3"
++	depends on FMAN_PFC && FSL_SDK_FMAN
++	range 0 65535
++	default "65535"
++endif
++
++endif # FSL_SDK_FMAN
++
++endmenu
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Makefile b/drivers/net/ethernet/freescale/sdk_fman/Makefile
+new file mode 100644
+index 0000000..25ce7e6
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Makefile
+@@ -0,0 +1,11 @@
++#
++# Makefile for the Freescale Ethernet controllers
++#
++ccflags-y           += -DVERSION=\"\"
++#
++#Include netcomm SW specific definitions
++include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
++#
++obj-y		+= etc/
++obj-y		+= Peripherals/FM/
++obj-y		+= src/
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/Makefile b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/Makefile
+new file mode 100644
+index 0000000..d0e7672
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/Makefile
+@@ -0,0 +1,15 @@
++#
++# Makefile for the Freescale Ethernet controllers
++#
++ccflags-y           += -DVERSION=\"\"
++#
++#Include netcomm SW specific definitions
++include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
++
++NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
++
++ccflags-y += -I$(NCSW_FM_INC)
++
++obj-y		+= fsl-ncsw-Hc.o
++
++fsl-ncsw-Hc-objs	:=   hc.o
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/hc.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/hc.c
+new file mode 100644
+index 0000000..363c8f9
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/hc.c
+@@ -0,0 +1,1232 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "sprint_ext.h"
++#include "string_ext.h"
++
++#include "fm_common.h"
++#include "fm_hc.h"
++
++
++/**************************************************************************//**
++ @Description       defaults
++*//***************************************************************************/
++#define DEFAULT_dataMemId                                       0
++
++#define HC_HCOR_OPCODE_PLCR_PRFL                                0x0
++#define HC_HCOR_OPCODE_KG_SCM                                   0x1
++#define HC_HCOR_OPCODE_SYNC                                     0x2
++#define HC_HCOR_OPCODE_CC                                       0x3
++#define HC_HCOR_OPCODE_CC_AGE_MASK                              0x4
++#define HC_HCOR_OPCODE_CC_CAPWAP_REASSM_TIMEOUT                 0x5
++#define HC_HCOR_OPCODE_CC_REASSM_TIMEOUT                        0x10
++#define HC_HCOR_OPCODE_CC_IP_FRAG_INITIALIZATION                0x11
++#define HC_HCOR_OPCODE_CC_UPDATE_WITH_AGING                     0x13
++#define HC_HCOR_ACTION_REG_REASSM_TIMEOUT_ACTIVE_SHIFT          24
++#define HC_HCOR_EXTRA_REG_REASSM_TIMEOUT_TSBS_SHIFT             24
++#define HC_HCOR_EXTRA_REG_CC_AGING_ADD                          0x80000000
++#define HC_HCOR_EXTRA_REG_CC_AGING_REMOVE                       0x40000000
++#define HC_HCOR_EXTRA_REG_CC_AGING_CHANGE_MASK                  0xC0000000
++#define HC_HCOR_EXTRA_REG_CC_REMOVE_INDX_SHIFT                  24
++#define HC_HCOR_EXTRA_REG_CC_REMOVE_INDX_MASK                   0x1F000000
++#define HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_SHIFT             16
++#define HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_MASK              0xF
++#define HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_CMD_SHIFT       24
++#define HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_BPID            16
++
++#define HC_HCOR_GBL                         0x20000000
++
++#define HC_HCOR_KG_SCHEME_COUNTER           0x00000400
++
++#if (DPAA_VERSION == 10)
++#define HC_HCOR_KG_SCHEME_REGS_MASK         0xFFFFF800
++#else
++#define HC_HCOR_KG_SCHEME_REGS_MASK         0xFFFFFE00
++#endif /* (DPAA_VERSION == 10) */
++
++#define SIZE_OF_HC_FRAME_PORT_REGS          (sizeof(t_HcFrame)-sizeof(struct fman_kg_scheme_regs)+sizeof(t_FmPcdKgPortRegs))
++#define SIZE_OF_HC_FRAME_SCHEME_REGS        sizeof(t_HcFrame)
++#define SIZE_OF_HC_FRAME_PROFILES_REGS      (sizeof(t_HcFrame)-sizeof(struct fman_kg_scheme_regs)+sizeof(t_FmPcdPlcrProfileRegs))
++#define SIZE_OF_HC_FRAME_PROFILE_CNT        (sizeof(t_HcFrame)-sizeof(t_FmPcdPlcrProfileRegs)+sizeof(uint32_t))
++#define SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC 16
++
++#define HC_CMD_POOL_SIZE                    (INTG_MAX_NUM_OF_CORES)
++
++#define BUILD_FD(len)                     \
++do {                                      \
++    memset(&fmFd, 0, sizeof(t_DpaaFD));   \
++    DPAA_FD_SET_ADDR(&fmFd, p_HcFrame);   \
++    DPAA_FD_SET_OFFSET(&fmFd, 0);         \
++    DPAA_FD_SET_LENGTH(&fmFd, len);       \
++} while (0)
++
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(push,1)
++#endif /* defined(__MWERKS__) && ... */
++
++typedef struct t_FmPcdKgPortRegs {
++    volatile uint32_t                       spReg;
++    volatile uint32_t                       cppReg;
++} t_FmPcdKgPortRegs;
++
++typedef struct t_HcFrame {
++    volatile uint32_t                           opcode;
++    volatile uint32_t                           actionReg;
++    volatile uint32_t                           extraReg;
++    volatile uint32_t                           commandSequence;
++    union {
++        struct fman_kg_scheme_regs              schemeRegs;
++        struct fman_kg_scheme_regs              schemeRegsWithoutCounter;
++        t_FmPcdPlcrProfileRegs                  profileRegs;
++        volatile uint32_t                       singleRegForWrite;    /* for writing SP, CPP, profile counter */
++        t_FmPcdKgPortRegs                       portRegsForRead;
++        volatile uint32_t                       clsPlanEntries[CLS_PLAN_NUM_PER_GRP];
++        t_FmPcdCcCapwapReassmTimeoutParams      ccCapwapReassmTimeout;
++        t_FmPcdCcReassmTimeoutParams            ccReassmTimeout;
++    } hcSpecificData;
++} t_HcFrame;
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(pop)
++#endif /* defined(__MWERKS__) && ... */
++
++
++typedef struct t_FmHc {
++    t_Handle                    h_FmPcd;
++    t_Handle                    h_HcPortDev;
++    t_FmPcdQmEnqueueCallback    *f_QmEnqueue;     /**< A callback for enqueuing frames to the QM */
++    t_Handle                    h_QmArg;          /**< A handle to the QM module */
++    uint8_t                     dataMemId;        /**< Memory partition ID for data buffers */
++
++    uint32_t                    seqNum[HC_CMD_POOL_SIZE];   /* FIFO of seqNum to use when
++                                                               taking buffer */
++    uint32_t                    nextSeqNumLocation;         /* seqNum location in seqNum[] for next buffer */
++    volatile bool               enqueued[HC_CMD_POOL_SIZE]; /* HC is active - frame is enqueued
++                                                               and not confirmed yet */
++    t_HcFrame                   *p_Frm[HC_CMD_POOL_SIZE];
++} t_FmHc;
++
++
++static t_Error FillBufPool(t_FmHc *p_FmHc)
++{
++    uint32_t i;
++
++    ASSERT_COND(p_FmHc);
++
++    for (i = 0; i < HC_CMD_POOL_SIZE; i++)
++    {
++#ifdef FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004
++        p_FmHc->p_Frm[i] = (t_HcFrame *)XX_MallocSmart((sizeof(t_HcFrame) + (16 - (sizeof(t_FmHc) % 16))),
++                                                       p_FmHc->dataMemId,
++                                                       16);
++#else
++        p_FmHc->p_Frm[i] = (t_HcFrame *)XX_MallocSmart(sizeof(t_HcFrame),
++                                                       p_FmHc->dataMemId,
++                                                       16);
++#endif /* FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 */
++        if (!p_FmHc->p_Frm[i])
++            RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM HC frames!"));
++    }
++
++    /* Initialize FIFO of seqNum to use during GetBuf */
++    for (i = 0; i < HC_CMD_POOL_SIZE; i++)
++    {
++        p_FmHc->seqNum[i] = i;
++    }
++    p_FmHc->nextSeqNumLocation = 0;
++
++    return E_OK;
++}
++
++static __inline__ t_HcFrame * GetBuf(t_FmHc *p_FmHc, uint32_t *p_SeqNum)
++{
++    uint32_t    intFlags;
++
++    ASSERT_COND(p_FmHc);
++
++    intFlags = FmPcdLock(p_FmHc->h_FmPcd);
++
++    if (p_FmHc->nextSeqNumLocation == HC_CMD_POOL_SIZE)
++    {
++        /* No more buffers */
++        FmPcdUnlock(p_FmHc->h_FmPcd, intFlags);
++        return NULL;
++    }
++
++    *p_SeqNum = p_FmHc->seqNum[p_FmHc->nextSeqNumLocation];
++    p_FmHc->nextSeqNumLocation++;
++
++    FmPcdUnlock(p_FmHc->h_FmPcd, intFlags);
++    return p_FmHc->p_Frm[*p_SeqNum];
++}
++
++static __inline__ void PutBuf(t_FmHc *p_FmHc, t_HcFrame *p_Buf, uint32_t seqNum)
++{
++    uint32_t    intFlags;
++
++    UNUSED(p_Buf);
++
++    intFlags = FmPcdLock(p_FmHc->h_FmPcd);
++    ASSERT_COND(p_FmHc->nextSeqNumLocation);
++    p_FmHc->nextSeqNumLocation--;
++    p_FmHc->seqNum[p_FmHc->nextSeqNumLocation] = seqNum;
++    FmPcdUnlock(p_FmHc->h_FmPcd, intFlags);
++}
++
++static __inline__ t_Error EnQFrm(t_FmHc *p_FmHc, t_DpaaFD *p_FmFd, uint32_t seqNum)
++{
++    t_Error     err = E_OK;
++    uint32_t    intFlags;
++    uint32_t    timeout=100;
++
++    intFlags = FmPcdLock(p_FmHc->h_FmPcd);
++    ASSERT_COND(!p_FmHc->enqueued[seqNum]);
++    p_FmHc->enqueued[seqNum] = TRUE;
++    FmPcdUnlock(p_FmHc->h_FmPcd, intFlags);
++    DBG(TRACE, ("Send Hc, SeqNum %d, buff at 0x%x, fd offset 0x%x",
++                seqNum,
++                DPAA_FD_GET_ADDR(p_FmFd),
++                DPAA_FD_GET_OFFSET(p_FmFd)));
++    err = p_FmHc->f_QmEnqueue(p_FmHc->h_QmArg, (void *)p_FmFd);
++    if (err)
++        RETURN_ERROR(MINOR, err, ("HC enqueue failed"));
++
++    while (p_FmHc->enqueued[seqNum] && --timeout)
++        XX_UDelay(100);
++
++    if (!timeout)
++        RETURN_ERROR(MINOR, E_TIMEOUT, ("HC Callback, timeout exceeded"));
++
++    return err;
++}
++
++
++t_Handle FmHcConfigAndInit(t_FmHcParams *p_FmHcParams)
++{
++    t_FmHc          *p_FmHc;
++    t_FmPortParams  fmPortParam;
++    t_Error         err;
++
++    p_FmHc = (t_FmHc *)XX_Malloc(sizeof(t_FmHc));
++    if (!p_FmHc)
++    {
++        REPORT_ERROR(MINOR, E_NO_MEMORY, ("HC obj"));
++        return NULL;
++    }
++    memset(p_FmHc,0,sizeof(t_FmHc));
++
++    p_FmHc->h_FmPcd             = p_FmHcParams->h_FmPcd;
++    p_FmHc->f_QmEnqueue         = p_FmHcParams->params.f_QmEnqueue;
++    p_FmHc->h_QmArg             = p_FmHcParams->params.h_QmArg;
++    p_FmHc->dataMemId           = DEFAULT_dataMemId;
++
++    err = FillBufPool(p_FmHc);
++    if (err != E_OK)
++    {
++        REPORT_ERROR(MAJOR, err, NO_MSG);
++        FmHcFree(p_FmHc);
++        return NULL;
++    }
++
++    if (!FmIsMaster(p_FmHcParams->h_Fm))
++        return (t_Handle)p_FmHc;
++
++    memset(&fmPortParam, 0, sizeof(fmPortParam));
++    fmPortParam.baseAddr    = p_FmHcParams->params.portBaseAddr;
++    fmPortParam.portType    = e_FM_PORT_TYPE_OH_HOST_COMMAND;
++    fmPortParam.portId      = p_FmHcParams->params.portId;
++    fmPortParam.liodnBase   = p_FmHcParams->params.liodnBase;
++    fmPortParam.h_Fm        = p_FmHcParams->h_Fm;
++
++    fmPortParam.specificParams.nonRxParams.errFqid      = p_FmHcParams->params.errFqid;
++    fmPortParam.specificParams.nonRxParams.dfltFqid     = p_FmHcParams->params.confFqid;
++    fmPortParam.specificParams.nonRxParams.qmChannel    = p_FmHcParams->params.qmChannel;
++
++    p_FmHc->h_HcPortDev = FM_PORT_Config(&fmPortParam);
++    if (!p_FmHc->h_HcPortDev)
++    {
++        REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("FM HC port!"));
++        XX_Free(p_FmHc);
++        return NULL;
++    }
++
++    err = FM_PORT_ConfigMaxFrameLength(p_FmHc->h_HcPortDev,
++                                       (uint16_t)sizeof(t_HcFrame));
++
++    if (err != E_OK)
++    {
++        REPORT_ERROR(MAJOR, err, ("FM HC port init!"));
++        FmHcFree(p_FmHc);
++        return NULL;
++    }
++
++    /* final init */
++    err = FM_PORT_Init(p_FmHc->h_HcPortDev);
++    if (err != E_OK)
++    {
++        REPORT_ERROR(MAJOR, err, ("FM HC port init!"));
++        FmHcFree(p_FmHc);
++        return NULL;
++    }
++
++    err = FM_PORT_Enable(p_FmHc->h_HcPortDev);
++    if (err != E_OK)
++    {
++        REPORT_ERROR(MAJOR, err, ("FM HC port enable!"));
++        FmHcFree(p_FmHc);
++        return NULL;
++    }
++
++    return (t_Handle)p_FmHc;
++}
++
++void FmHcFree(t_Handle h_FmHc)
++{
++    t_FmHc  *p_FmHc = (t_FmHc*)h_FmHc;
++    int     i;
++
++    if (!p_FmHc)
++        return;
++
++    for (i=0; i<HC_CMD_POOL_SIZE; i++)
++        if (p_FmHc->p_Frm[i])
++            XX_FreeSmart(p_FmHc->p_Frm[i]);
++        else
++            break;
++
++    if (p_FmHc->h_HcPortDev)
++        FM_PORT_Free(p_FmHc->h_HcPortDev);
++
++    XX_Free(p_FmHc);
++}
++
++/*****************************************************************************/
++t_Error FmHcSetFramesDataMemory(t_Handle h_FmHc,
++                                uint8_t  memId)
++{
++    t_FmHc  *p_FmHc = (t_FmHc*)h_FmHc;
++    int     i;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmHc, E_INVALID_HANDLE);
++
++    p_FmHc->dataMemId            = memId;
++
++    for (i=0; i<HC_CMD_POOL_SIZE; i++)
++        if (p_FmHc->p_Frm[i])
++            XX_FreeSmart(p_FmHc->p_Frm[i]);
++
++    return FillBufPool(p_FmHc);
++}
++
++void FmHcTxConf(t_Handle h_FmHc, t_DpaaFD *p_Fd)
++{
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame   *p_HcFrame;
++    uint32_t    intFlags;
++
++    ASSERT_COND(p_FmHc);
++
++    intFlags = FmPcdLock(p_FmHc->h_FmPcd);
++    p_HcFrame  = (t_HcFrame *)PTR_MOVE(DPAA_FD_GET_ADDR(p_Fd), DPAA_FD_GET_OFFSET(p_Fd));
++
++    DBG(TRACE, ("Hc Conf, SeqNum %d, FD at 0x%x, fd offset 0x%x",
++                p_HcFrame->commandSequence, DPAA_FD_GET_ADDR(p_Fd), DPAA_FD_GET_OFFSET(p_Fd)));
++
++    if (!(p_FmHc->enqueued[p_HcFrame->commandSequence]))
++        REPORT_ERROR(MINOR, E_INVALID_FRAME, ("Not an Host-Command frame received!"));
++    else
++        p_FmHc->enqueued[p_HcFrame->commandSequence] = FALSE;
++    FmPcdUnlock(p_FmHc->h_FmPcd, intFlags);
++}
++
++t_Error FmHcPcdKgSetScheme(t_Handle                    h_FmHc,
++                           t_Handle                    h_Scheme,
++                           struct fman_kg_scheme_regs  *p_SchemeRegs,
++                           bool                        updateCounter)
++{
++    t_FmHc                              *p_FmHc = (t_FmHc*)h_FmHc;
++    t_Error                             err = E_OK;
++    t_HcFrame                           *p_HcFrame;
++    t_DpaaFD                            fmFd;
++    uint8_t                             physicalSchemeId;
++    uint32_t                            seqNum;
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++
++    physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme);
++
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++    p_HcFrame->actionReg  = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, updateCounter);
++    p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++    memcpy(&p_HcFrame->hcSpecificData.schemeRegs, p_SchemeRegs, sizeof(struct fman_kg_scheme_regs));
++    if (!updateCounter)
++    {
++        p_HcFrame->hcSpecificData.schemeRegs.kgse_dv0   = p_SchemeRegs->kgse_dv0;
++        p_HcFrame->hcSpecificData.schemeRegs.kgse_dv1   = p_SchemeRegs->kgse_dv1;
++        p_HcFrame->hcSpecificData.schemeRegs.kgse_ccbs  = p_SchemeRegs->kgse_ccbs;
++        p_HcFrame->hcSpecificData.schemeRegs.kgse_mv    = p_SchemeRegs->kgse_mv;
++    }
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Error FmHcPcdKgDeleteScheme(t_Handle h_FmHc, t_Handle h_Scheme)
++{
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    t_Error     err = E_OK;
++    t_HcFrame   *p_HcFrame;
++    t_DpaaFD    fmFd;
++    uint8_t     physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme);
++    uint32_t    seqNum;
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++    p_HcFrame->actionReg  = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, TRUE);
++    p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++    memset(&p_HcFrame->hcSpecificData.schemeRegs, 0, sizeof(struct fman_kg_scheme_regs));
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Error FmHcPcdKgCcGetSetParams(t_Handle h_FmHc, t_Handle  h_Scheme, uint32_t requiredAction, uint32_t value)
++{
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    t_Error     err = E_OK;
++    t_HcFrame   *p_HcFrame;
++    t_DpaaFD    fmFd;
++    uint8_t     relativeSchemeId;
++    uint8_t     physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme);
++    uint32_t    tmpReg32 = 0;
++    uint32_t    seqNum;
++
++    /* Scheme is locked by calling routine */
++    /* WARNING - this lock will not be efficient if other HC routine will attempt to change
++     * "kgse_mode" or "kgse_om" without locking scheme !
++     */
++
++    relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmHc->h_FmPcd, physicalSchemeId);
++    if ( relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES)
++        RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG);
++
++    if (!FmPcdKgGetRequiredActionFlag(p_FmHc->h_FmPcd, relativeSchemeId) ||
++       !(FmPcdKgGetRequiredAction(p_FmHc->h_FmPcd, relativeSchemeId) & requiredAction))
++    {
++        if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) &&
++            (FmPcdKgGetNextEngine(p_FmHc->h_FmPcd, relativeSchemeId) == e_FM_PCD_PLCR))
++            {
++                if ((FmPcdKgIsDirectPlcr(p_FmHc->h_FmPcd, relativeSchemeId) == FALSE) ||
++                    (FmPcdKgIsDistrOnPlcrProfile(p_FmHc->h_FmPcd, relativeSchemeId) == TRUE))
++                    RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("In this situation PP can not be with distribution and has to be shared"));
++                err = FmPcdPlcrCcGetSetParams(p_FmHc->h_FmPcd, FmPcdKgGetRelativeProfileId(p_FmHc->h_FmPcd, relativeSchemeId), requiredAction);
++                if (err)
++                    RETURN_ERROR(MAJOR, err, NO_MSG);
++            }
++        else /* From here we deal with KG-Schemes only */
++        {
++            /* Pre change general code */
++            p_HcFrame = GetBuf(p_FmHc, &seqNum);
++            if (!p_HcFrame)
++                RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++            memset(p_HcFrame, 0, sizeof(t_HcFrame));
++            p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++            p_HcFrame->actionReg  = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId);
++            p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++            p_HcFrame->commandSequence = seqNum;
++            BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC);
++            if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MINOR, err, NO_MSG);
++            }
++
++            /* specific change */
++            if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) &&
++                ((FmPcdKgGetNextEngine(p_FmHc->h_FmPcd, relativeSchemeId) == e_FM_PCD_DONE) &&
++                 (FmPcdKgGetDoneAction(p_FmHc->h_FmPcd, relativeSchemeId) ==  e_FM_PCD_ENQ_FRAME)))
++            {
++                tmpReg32 = p_HcFrame->hcSpecificData.schemeRegs.kgse_mode;
++                ASSERT_COND(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME));
++                p_HcFrame->hcSpecificData.schemeRegs.kgse_mode =  tmpReg32 | NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA;
++            }
++
++            if ((requiredAction & UPDATE_KG_NIA_CC_WA) &&
++                (FmPcdKgGetNextEngine(p_FmHc->h_FmPcd, relativeSchemeId) == e_FM_PCD_CC))
++            {
++                tmpReg32 = p_HcFrame->hcSpecificData.schemeRegs.kgse_mode;
++                ASSERT_COND(tmpReg32 & (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_CC));
++                tmpReg32 &= ~NIA_FM_CTL_AC_CC;
++                p_HcFrame->hcSpecificData.schemeRegs.kgse_mode =  tmpReg32 | NIA_FM_CTL_AC_PRE_CC;
++            }
++
++            if (requiredAction & UPDATE_KG_OPT_MODE)
++                p_HcFrame->hcSpecificData.schemeRegs.kgse_om = value;
++
++            if (requiredAction & UPDATE_KG_NIA)
++            {
++                tmpReg32 = p_HcFrame->hcSpecificData.schemeRegs.kgse_mode;
++                tmpReg32 &= ~(NIA_ENG_MASK | NIA_AC_MASK);
++                tmpReg32 |= value;
++                p_HcFrame->hcSpecificData.schemeRegs.kgse_mode = tmpReg32;
++            }
++
++            /* Post change general code */
++            p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++            p_HcFrame->actionReg  = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, FALSE);
++            p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++
++            BUILD_FD(sizeof(t_HcFrame));
++            err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++            PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++            if (err != E_OK)
++                RETURN_ERROR(MINOR, err, NO_MSG);
++        }
++    }
++
++    return E_OK;
++}
++
++uint32_t  FmHcPcdKgGetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme)
++{
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    t_Error     err;
++    t_HcFrame   *p_HcFrame;
++    t_DpaaFD    fmFd;
++    uint32_t    retVal;
++    uint8_t     relativeSchemeId;
++    uint8_t     physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme);
++    uint32_t    seqNum;
++
++    relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmHc->h_FmPcd, physicalSchemeId);
++    if ( relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES)
++    {
++        REPORT_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG);
++        return 0;
++    }
++
++    /* first read scheme and check that it is valid */
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++    {
++        REPORT_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++        return 0;
++    }
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++    p_HcFrame->actionReg  = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId);
++    p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC);
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++    if (err != E_OK)
++    {
++        PutBuf(p_FmHc, p_HcFrame, seqNum);
++        REPORT_ERROR(MINOR, err, NO_MSG);
++        return 0;
++    }
++
++    if (!FmPcdKgHwSchemeIsValid(p_HcFrame->hcSpecificData.schemeRegs.kgse_mode))
++    {
++        PutBuf(p_FmHc, p_HcFrame, seqNum);
++        REPORT_ERROR(MAJOR, E_ALREADY_EXISTS, ("Scheme is invalid"));
++        return 0;
++    }
++
++    retVal = p_HcFrame->hcSpecificData.schemeRegs.kgse_spc;
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    return retVal;
++}
++
++t_Error  FmHcPcdKgSetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t value)
++{
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    t_Error     err = E_OK;
++    t_HcFrame   *p_HcFrame;
++    t_DpaaFD    fmFd;
++    uint8_t     relativeSchemeId, physicalSchemeId;
++    uint32_t    seqNum;
++
++    physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme);
++    relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmHc->h_FmPcd, physicalSchemeId);
++    if ( relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES)
++        RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG);
++
++    /* first read scheme and check that it is valid */
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++    p_HcFrame->actionReg  = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, TRUE);
++    p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_COUNTER;
++    /* write counter */
++    p_HcFrame->hcSpecificData.singleRegForWrite = value;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++    return err;
++}
++
++t_Error FmHcPcdKgSetClsPlan(t_Handle h_FmHc, t_FmPcdKgInterModuleClsPlanSet *p_Set)
++{
++    t_FmHc                  *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame               *p_HcFrame;
++    t_DpaaFD                fmFd;
++    uint8_t                 i, idx;
++    uint32_t                seqNum;
++    t_Error                 err = E_OK;
++
++    ASSERT_COND(p_FmHc);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++
++    for (i = p_Set->baseEntry; i < (p_Set->baseEntry+p_Set->numOfClsPlanEntries); i+=8)
++    {
++        memset(p_HcFrame, 0, sizeof(t_HcFrame));
++        p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++        p_HcFrame->actionReg  = FmPcdKgBuildWriteClsPlanBlockActionReg((uint8_t)(i / CLS_PLAN_NUM_PER_GRP));
++        p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++
++        idx = (uint8_t)(i - p_Set->baseEntry);
++        ASSERT_COND(idx < FM_PCD_MAX_NUM_OF_CLS_PLANS);
++        memcpy(&p_HcFrame->hcSpecificData.clsPlanEntries, &p_Set->vectors[idx], CLS_PLAN_NUM_PER_GRP*sizeof(uint32_t));
++        p_HcFrame->commandSequence = seqNum;
++
++        BUILD_FD(sizeof(t_HcFrame));
++
++        if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++        {
++            PutBuf(p_FmHc, p_HcFrame, seqNum);
++            RETURN_ERROR(MINOR, err, NO_MSG);
++        }
++    }
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++    return err;
++}
++
++t_Error FmHcPcdKgDeleteClsPlan(t_Handle h_FmHc, uint8_t  grpId)
++{
++    t_FmHc                              *p_FmHc = (t_FmHc*)h_FmHc;
++    t_FmPcdKgInterModuleClsPlanSet      *p_ClsPlanSet;
++
++    p_ClsPlanSet = (t_FmPcdKgInterModuleClsPlanSet *)XX_Malloc(sizeof(t_FmPcdKgInterModuleClsPlanSet));
++    if (!p_ClsPlanSet)
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Classification plan set"));
++
++    memset(p_ClsPlanSet, 0, sizeof(t_FmPcdKgInterModuleClsPlanSet));
++
++    p_ClsPlanSet->baseEntry = FmPcdKgGetClsPlanGrpBase(p_FmHc->h_FmPcd, grpId);
++    p_ClsPlanSet->numOfClsPlanEntries = FmPcdKgGetClsPlanGrpSize(p_FmHc->h_FmPcd, grpId);
++    ASSERT_COND(p_ClsPlanSet->numOfClsPlanEntries <= FM_PCD_MAX_NUM_OF_CLS_PLANS);
++
++    if (FmHcPcdKgSetClsPlan(p_FmHc, p_ClsPlanSet) != E_OK)
++    {
++        XX_Free(p_ClsPlanSet);
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++    }
++
++    XX_Free(p_ClsPlanSet);
++    FmPcdKgDestroyClsPlanGrp(p_FmHc->h_FmPcd, grpId);
++
++    return E_OK;
++}
++
++t_Error FmHcPcdCcCapwapTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcCapwapReassmTimeoutParams *p_CcCapwapReassmTimeoutParams )
++{
++    t_FmHc                              *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame                           *p_HcFrame;
++    t_DpaaFD                            fmFd;
++    t_Error                             err;
++    uint32_t                            seqNum;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC_CAPWAP_REASSM_TIMEOUT);
++    memcpy(&p_HcFrame->hcSpecificData.ccCapwapReassmTimeout, p_CcCapwapReassmTimeoutParams, sizeof(t_FmPcdCcCapwapReassmTimeoutParams));
++    p_HcFrame->commandSequence = seqNum;
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++    return err;
++}
++
++t_Error FmHcPcdCcIpFragScratchPollCmd(t_Handle h_FmHc, bool fill, t_FmPcdCcFragScratchPoolCmdParams *p_FmPcdCcFragScratchPoolCmdParams)
++{
++    t_FmHc                              *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame                           *p_HcFrame;
++    t_DpaaFD                            fmFd;
++    t_Error                             err;
++    uint32_t                            seqNum;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++
++    p_HcFrame->opcode     = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC_IP_FRAG_INITIALIZATION);
++    p_HcFrame->actionReg  = (uint32_t)(((fill == TRUE) ? 0 : 1) << HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_CMD_SHIFT);
++    p_HcFrame->actionReg |= p_FmPcdCcFragScratchPoolCmdParams->bufferPoolId << HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_BPID;
++    if (fill == TRUE)
++    {
++        p_HcFrame->extraReg   = p_FmPcdCcFragScratchPoolCmdParams->numOfBuffers;
++    }
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++    if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++    {
++        PutBuf(p_FmHc, p_HcFrame, seqNum);
++        RETURN_ERROR(MINOR, err, NO_MSG);
++    }
++
++    p_FmPcdCcFragScratchPoolCmdParams->numOfBuffers = p_HcFrame->extraReg;
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++    return E_OK;
++}
++
++t_Error FmHcPcdCcTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcReassmTimeoutParams *p_CcReassmTimeoutParams, uint8_t *p_Result)
++{
++    t_FmHc                              *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame                           *p_HcFrame;
++    t_DpaaFD                            fmFd;
++    t_Error                             err;
++    uint32_t                            seqNum;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC_REASSM_TIMEOUT);
++    p_HcFrame->actionReg = (uint32_t)((p_CcReassmTimeoutParams->activate ? 0 : 1) << HC_HCOR_ACTION_REG_REASSM_TIMEOUT_ACTIVE_SHIFT);
++    p_HcFrame->extraReg = (p_CcReassmTimeoutParams->tsbs << HC_HCOR_EXTRA_REG_REASSM_TIMEOUT_TSBS_SHIFT) | p_CcReassmTimeoutParams->iprcpt;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++    if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++    {
++        PutBuf(p_FmHc, p_HcFrame, seqNum);
++        RETURN_ERROR(MINOR, err, NO_MSG);
++    }
++
++    *p_Result = (uint8_t)
++        ((p_HcFrame->actionReg >> HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_SHIFT) & HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_MASK);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++    return E_OK;
++}
++
++t_Error FmHcPcdPlcrCcGetSetParams(t_Handle h_FmHc,uint16_t absoluteProfileId, uint32_t requiredAction)
++{
++    t_FmHc              *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame           *p_HcFrame;
++    t_DpaaFD            fmFd;
++    t_Error             err;
++    uint32_t            tmpReg32 = 0;
++    uint32_t            requiredActionTmp, requiredActionFlag;
++    uint32_t            seqNum;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0);
++
++    /* Profile is locked by calling routine */
++    /* WARNING - this lock will not be efficient if other HC routine will attempt to change
++     * "fmpl_pegnia" "fmpl_peynia" or "fmpl_pernia" without locking Profile !
++     */
++
++    requiredActionTmp = FmPcdPlcrGetRequiredAction(p_FmHc->h_FmPcd, absoluteProfileId);
++    requiredActionFlag = FmPcdPlcrGetRequiredActionFlag(p_FmHc->h_FmPcd, absoluteProfileId);
++
++    if (!requiredActionFlag || !(requiredActionTmp & requiredAction))
++    {
++        if (requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA)
++        {
++            p_HcFrame = GetBuf(p_FmHc, &seqNum);
++            if (!p_HcFrame)
++                RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++            /* first read scheme and check that it is valid */
++            memset(p_HcFrame, 0, sizeof(t_HcFrame));
++            p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++            p_HcFrame->actionReg  = FmPcdPlcrBuildReadPlcrActionReg(absoluteProfileId);
++            p_HcFrame->extraReg = 0x00008000;
++            p_HcFrame->commandSequence = seqNum;
++
++            BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC);
++
++            if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MINOR, err, NO_MSG);
++            }
++
++            tmpReg32 = p_HcFrame->hcSpecificData.profileRegs.fmpl_pegnia;
++            if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)))
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                             ("Next engine of this policer profile has to be assigned to FM_PCD_DONE"));
++            }
++
++            tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA;
++
++            p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++            p_HcFrame->actionReg  = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId);
++            p_HcFrame->actionReg |= FmPcdPlcrBuildNiaProfileReg(TRUE, FALSE, FALSE);
++            p_HcFrame->extraReg = 0x00008000;
++            p_HcFrame->hcSpecificData.singleRegForWrite = tmpReg32;
++
++            BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT);
++
++            if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MINOR, err, NO_MSG);
++            }
++
++            tmpReg32 = p_HcFrame->hcSpecificData.profileRegs.fmpl_peynia;
++            if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)))
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next engine of this policer profile has to be assigned to FM_PCD_DONE"));
++            }
++
++            tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA;
++
++            p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++            p_HcFrame->actionReg  = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId);
++            p_HcFrame->actionReg |= FmPcdPlcrBuildNiaProfileReg(FALSE, TRUE, FALSE);
++            p_HcFrame->extraReg = 0x00008000;
++            p_HcFrame->hcSpecificData.singleRegForWrite = tmpReg32;
++
++            BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT);
++
++            if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MINOR, err, NO_MSG);
++            }
++
++            tmpReg32 = p_HcFrame->hcSpecificData.profileRegs.fmpl_pernia;
++            if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)))
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next engine of this policer profile has to be assigned to FM_PCD_DONE"));
++            }
++
++            tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA;
++
++            p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++            p_HcFrame->actionReg  = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId);
++            p_HcFrame->actionReg |= FmPcdPlcrBuildNiaProfileReg(FALSE, FALSE, TRUE);
++            p_HcFrame->extraReg = 0x00008000;
++            p_HcFrame->hcSpecificData.singleRegForWrite = tmpReg32;
++
++            BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT);
++
++            if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++            {
++                PutBuf(p_FmHc, p_HcFrame, seqNum);
++                RETURN_ERROR(MINOR, err, NO_MSG);
++            }
++
++            PutBuf(p_FmHc, p_HcFrame, seqNum);
++        }
++    }
++
++    return E_OK;
++}
++
++t_Error FmHcPcdPlcrSetProfile(t_Handle h_FmHc, t_Handle h_Profile, t_FmPcdPlcrProfileRegs *p_PlcrRegs)
++{
++    t_FmHc                              *p_FmHc = (t_FmHc*)h_FmHc;
++    t_Error                             err = E_OK;
++    uint16_t                            profileIndx;
++    t_HcFrame                           *p_HcFrame;
++    t_DpaaFD                            fmFd;
++    uint32_t                            seqNum;
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++
++    profileIndx = FmPcdPlcrProfileGetAbsoluteId(h_Profile);
++
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++    p_HcFrame->actionReg  = FmPcdPlcrBuildWritePlcrActionRegs(profileIndx);
++    p_HcFrame->extraReg = 0x00008000;
++    memcpy(&p_HcFrame->hcSpecificData.profileRegs, p_PlcrRegs, sizeof(t_FmPcdPlcrProfileRegs));
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Error FmHcPcdPlcrDeleteProfile(t_Handle h_FmHc, t_Handle h_Profile)
++{
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    uint16_t    absoluteProfileId = FmPcdPlcrProfileGetAbsoluteId(h_Profile);
++    t_Error     err = E_OK;
++    t_HcFrame   *p_HcFrame;
++    t_DpaaFD    fmFd;
++    uint32_t    seqNum;
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++    p_HcFrame->actionReg  = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId);
++    p_HcFrame->actionReg  |= 0x00008000;
++    p_HcFrame->extraReg = 0x00008000;
++    memset(&p_HcFrame->hcSpecificData.profileRegs, 0, sizeof(t_FmPcdPlcrProfileRegs));
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Error  FmHcPcdPlcrSetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter, uint32_t value)
++{
++
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    uint16_t    absoluteProfileId = FmPcdPlcrProfileGetAbsoluteId(h_Profile);
++    t_Error     err = E_OK;
++    t_HcFrame   *p_HcFrame;
++    t_DpaaFD    fmFd;
++    uint32_t    seqNum;
++
++    /* first read scheme and check that it is valid */
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++    p_HcFrame->actionReg  = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId);
++    p_HcFrame->actionReg |= FmPcdPlcrBuildCounterProfileReg(counter);
++    p_HcFrame->extraReg = 0x00008000;
++    p_HcFrame->hcSpecificData.singleRegForWrite = value;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT);
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++uint32_t FmHcPcdPlcrGetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter)
++{
++    t_FmHc      *p_FmHc = (t_FmHc*)h_FmHc;
++    uint16_t    absoluteProfileId = FmPcdPlcrProfileGetAbsoluteId(h_Profile);
++    t_Error     err;
++    t_HcFrame   *p_HcFrame;
++    t_DpaaFD    fmFd;
++    uint32_t    retVal = 0;
++    uint32_t    seqNum;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0);
++
++    /* first read scheme and check that it is valid */
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++    {
++        REPORT_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++        return 0;
++    }
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL);
++    p_HcFrame->actionReg  = FmPcdPlcrBuildReadPlcrActionReg(absoluteProfileId);
++    p_HcFrame->extraReg = 0x00008000;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC);
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++    if (err != E_OK)
++    {
++        PutBuf(p_FmHc, p_HcFrame, seqNum);
++        REPORT_ERROR(MINOR, err, NO_MSG);
++        return 0;
++    }
++
++    switch (counter)
++    {
++        case e_FM_PCD_PLCR_PROFILE_GREEN_PACKET_TOTAL_COUNTER:
++            retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_pegpc;
++            break;
++        case e_FM_PCD_PLCR_PROFILE_YELLOW_PACKET_TOTAL_COUNTER:
++            retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_peypc;
++            break;
++        case e_FM_PCD_PLCR_PROFILE_RED_PACKET_TOTAL_COUNTER:
++            retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_perpc;
++            break;
++        case e_FM_PCD_PLCR_PROFILE_RECOLOURED_YELLOW_PACKET_TOTAL_COUNTER:
++            retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_perypc;
++            break;
++        case e_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER:
++            retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_perrpc;
++            break;
++        default:
++            REPORT_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG);
++    }
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++    return retVal;
++}
++
++t_Error FmHcKgWriteSp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t spReg, bool add)
++{
++    t_FmHc                  *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame               *p_HcFrame;
++    t_DpaaFD                fmFd;
++    t_Error                 err = E_OK;
++    uint32_t                seqNum;
++
++    ASSERT_COND(p_FmHc);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    /* first read SP register */
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++    p_HcFrame->actionReg  = FmPcdKgBuildReadPortSchemeBindActionReg(hardwarePortId);
++    p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(SIZE_OF_HC_FRAME_PORT_REGS);
++
++    if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK)
++    {
++        PutBuf(p_FmHc, p_HcFrame, seqNum);
++        RETURN_ERROR(MINOR, err, NO_MSG);
++    }
++
++    /* spReg is the first reg, so we can use it both for read and for write */
++    if (add)
++        p_HcFrame->hcSpecificData.portRegsForRead.spReg |= spReg;
++    else
++        p_HcFrame->hcSpecificData.portRegsForRead.spReg &= ~spReg;
++
++    p_HcFrame->actionReg  = FmPcdKgBuildWritePortSchemeBindActionReg(hardwarePortId);
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Error FmHcKgWriteCpp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t cppReg)
++{
++    t_FmHc                  *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame               *p_HcFrame;
++    t_DpaaFD                fmFd;
++    t_Error                 err = E_OK;
++    uint32_t                seqNum;
++
++    ASSERT_COND(p_FmHc);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    /* first read SP register */
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM);
++    p_HcFrame->actionReg  = FmPcdKgBuildWritePortClsPlanBindActionReg(hardwarePortId);
++    p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK;
++    p_HcFrame->hcSpecificData.singleRegForWrite = cppReg;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Error FmHcPcdCcDoDynamicChange(t_Handle h_FmHc, uint32_t oldAdAddrOffset, uint32_t newAdAddrOffset)
++{
++    t_FmHc                  *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame               *p_HcFrame;
++    t_DpaaFD                fmFd;
++    t_Error                 err = E_OK;
++    uint32_t                seqNum;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmHc, E_INVALID_HANDLE);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++
++    p_HcFrame->opcode     = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC);
++    p_HcFrame->actionReg  = newAdAddrOffset;
++    p_HcFrame->actionReg |= 0xc0000000;
++    p_HcFrame->extraReg   = oldAdAddrOffset;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC);
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Error FmHcPcdSync(t_Handle h_FmHc)
++{
++    t_FmHc                  *p_FmHc = (t_FmHc*)h_FmHc;
++    t_HcFrame               *p_HcFrame;
++    t_DpaaFD                fmFd;
++    t_Error                 err = E_OK;
++    uint32_t                seqNum;
++
++    ASSERT_COND(p_FmHc);
++
++    p_HcFrame = GetBuf(p_FmHc, &seqNum);
++    if (!p_HcFrame)
++        RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object"));
++    memset(p_HcFrame, 0, sizeof(t_HcFrame));
++    /* first read SP register */
++    p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_SYNC);
++    p_HcFrame->actionReg = 0;
++    p_HcFrame->extraReg = 0;
++    p_HcFrame->commandSequence = seqNum;
++
++    BUILD_FD(sizeof(t_HcFrame));
++
++    err = EnQFrm(p_FmHc, &fmFd, seqNum);
++
++    PutBuf(p_FmHc, p_HcFrame, seqNum);
++
++    if (err != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++t_Handle    FmHcGetPort(t_Handle h_FmHc)
++{
++    t_FmHc *p_FmHc = (t_FmHc*)h_FmHc;
++    return p_FmHc->h_HcPortDev;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/Makefile b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/Makefile
+new file mode 100644
+index 0000000..823f6ad
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/Makefile
+@@ -0,0 +1,25 @@
++#
++# Makefile for the Freescale Ethernet controllers
++#
++ccflags-y           += -DVERSION=\"\"
++#
++#Include netcomm SW specific definitions
++include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
++
++NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
++
++ccflags-y += -I$(NCSW_FM_INC)
++
++obj-y		+= fsl-ncsw-MAC.o
++
++fsl-ncsw-MAC-objs	:=  dtsec.o dtsec_mii_acc.o fm_mac.o tgec.o tgec_mii_acc.o \
++			    fman_dtsec.o fman_dtsec_mii_acc.o fman_memac.o \
++			    fman_tgec.o fman_crc32.o
++
++ifeq ($(CONFIG_FMAN_V3H),y)
++fsl-ncsw-MAC-objs	+=  memac.o memac_mii_acc.o fman_memac_mii_acc.o
++endif
++ifeq ($(CONFIG_FMAN_V3L),y)
++fsl-ncsw-MAC-objs       +=  memac.o memac_mii_acc.o fman_memac_mii_acc.o
++endif
++
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c
+new file mode 100644
+index 0000000..5ae65f8
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c
+@@ -0,0 +1,1463 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          dtsec.c
++
++ @Description   FMan dTSEC driver
++*//***************************************************************************/
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "string_ext.h"
++#include "xx_ext.h"
++#include "endian_ext.h"
++#include "debug_ext.h"
++#include "crc_mac_addr_ext.h"
++
++#include "fm_common.h"
++#include "dtsec.h"
++#include "fsl_fman_dtsec.h"
++#include "fsl_fman_dtsec_mii_acc.h"
++
++/*****************************************************************************/
++/*                      Internal routines                                    */
++/*****************************************************************************/
++
++static t_Error CheckInitParameters(t_Dtsec *p_Dtsec)
++{
++    if (ENET_SPEED_FROM_MODE(p_Dtsec->enetMode) >= e_ENET_SPEED_10000)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 1G MAC driver only supports 1G or lower speeds"));
++    if (p_Dtsec->macId >= FM_MAX_NUM_OF_1G_MACS)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("macId can not be greater than the number of 1G MACs"));
++    if (p_Dtsec->addr == 0)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet MAC Must have a valid MAC Address"));
++    if ((ENET_SPEED_FROM_MODE(p_Dtsec->enetMode) >= e_ENET_SPEED_1000) &&
++        p_Dtsec->p_DtsecDriverParam->halfdup_on)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet MAC 1G can't work in half duplex"));
++    if (p_Dtsec->p_DtsecDriverParam->halfdup_on && (p_Dtsec->p_DtsecDriverParam)->loopback)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("LoopBack is not supported in halfDuplex mode"));
++#ifdef FM_RX_PREAM_4_ERRATA_DTSEC_A001
++    if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev <= 6) /* fixed for rev3 */
++        if (p_Dtsec->p_DtsecDriverParam->rx_preamble)
++            RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("preambleRxEn"));
++#endif /* FM_RX_PREAM_4_ERRATA_DTSEC_A001 */
++    if (((p_Dtsec->p_DtsecDriverParam)->tx_preamble || (p_Dtsec->p_DtsecDriverParam)->rx_preamble) &&( (p_Dtsec->p_DtsecDriverParam)->preamble_len != 0x7))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Preamble length should be 0x7 bytes"));
++    if ((p_Dtsec->p_DtsecDriverParam)->halfdup_on &&
++       (p_Dtsec->p_DtsecDriverParam->tx_time_stamp_en || p_Dtsec->p_DtsecDriverParam->rx_time_stamp_en))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dTSEC in half duplex mode has to be with 1588 timeStamping diable"));
++    if ((p_Dtsec->p_DtsecDriverParam)->rx_flow && (p_Dtsec->p_DtsecDriverParam)->rx_ctrl_acc )
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Receive control frame are not passed to the system memory so it can not be accept "));
++    if ((p_Dtsec->p_DtsecDriverParam)->rx_prepend  > MAX_PACKET_ALIGNMENT)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("packetAlignmentPadding can't be greater than %d ",MAX_PACKET_ALIGNMENT ));
++    if (((p_Dtsec->p_DtsecDriverParam)->non_back_to_back_ipg1  > MAX_INTER_PACKET_GAP) ||
++        ((p_Dtsec->p_DtsecDriverParam)->non_back_to_back_ipg2 > MAX_INTER_PACKET_GAP) ||
++        ((p_Dtsec->p_DtsecDriverParam)->back_to_back_ipg > MAX_INTER_PACKET_GAP))
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inter packet gap can't be greater than %d ",MAX_INTER_PACKET_GAP ));
++    if ((p_Dtsec->p_DtsecDriverParam)->halfdup_alt_backoff_val > MAX_INTER_PALTERNATE_BEB)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("alternateBackoffVal can't be greater than %d ",MAX_INTER_PALTERNATE_BEB ));
++    if ((p_Dtsec->p_DtsecDriverParam)->halfdup_retransmit > MAX_RETRANSMISSION)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("maxRetransmission can't be greater than %d ",MAX_RETRANSMISSION ));
++    if ((p_Dtsec->p_DtsecDriverParam)->halfdup_coll_window > MAX_COLLISION_WINDOW)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("collisionWindow can't be greater than %d ",MAX_COLLISION_WINDOW ));
++
++    /*  If Auto negotiation process is disabled, need to */
++    /*  Set up the PHY using the MII Management Interface */
++    if (p_Dtsec->p_DtsecDriverParam->tbipa > MAX_PHYS)
++        RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, ("PHY address (should be 0-%d)", MAX_PHYS));
++    if (!p_Dtsec->f_Exception)
++        RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("uninitialized f_Exception"));
++    if (!p_Dtsec->f_Event)
++        RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("uninitialized f_Event"));
++
++#ifdef FM_LEN_CHECK_ERRATA_FMAN_SW002
++    if (p_Dtsec->p_DtsecDriverParam->rx_len_check)
++       RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("LengthCheck!"));
++#endif /* FM_LEN_CHECK_ERRATA_FMAN_SW002 */
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static uint32_t GetMacAddrHashCode(uint64_t ethAddr)
++{
++    uint32_t crc;
++
++    /* CRC calculation */
++    GET_MAC_ADDR_CRC(ethAddr, crc);
++
++    crc = GetMirror32(crc);
++
++    return crc;
++}
++
++/* ......................................................................... */
++
++static void UpdateStatistics(t_Dtsec *p_Dtsec)
++{
++    uint32_t car1, car2;
++
++    fman_dtsec_get_clear_carry_regs(p_Dtsec->p_MemMap, &car1, &car2);
++
++    if (car1)
++    {
++        if (car1 & CAR1_TR64)
++            p_Dtsec->internalStatistics.tr64 += VAL22BIT;
++        if (car1 & CAR1_TR127)
++            p_Dtsec->internalStatistics.tr127 += VAL22BIT;
++        if (car1 & CAR1_TR255)
++            p_Dtsec->internalStatistics.tr255 += VAL22BIT;
++        if (car1 & CAR1_TR511)
++            p_Dtsec->internalStatistics.tr511 += VAL22BIT;
++        if (car1 & CAR1_TRK1)
++            p_Dtsec->internalStatistics.tr1k += VAL22BIT;
++        if (car1 & CAR1_TRMAX)
++            p_Dtsec->internalStatistics.trmax += VAL22BIT;
++        if (car1 & CAR1_TRMGV)
++            p_Dtsec->internalStatistics.trmgv += VAL22BIT;
++        if (car1 & CAR1_RBYT)
++            p_Dtsec->internalStatistics.rbyt += (uint64_t)VAL32BIT;
++        if (car1 & CAR1_RPKT)
++            p_Dtsec->internalStatistics.rpkt += VAL22BIT;
++        if (car1 & CAR1_RMCA)
++            p_Dtsec->internalStatistics.rmca += VAL22BIT;
++        if (car1 & CAR1_RBCA)
++            p_Dtsec->internalStatistics.rbca += VAL22BIT;
++        if (car1 & CAR1_RXPF)
++            p_Dtsec->internalStatistics.rxpf += VAL16BIT;
++        if (car1 & CAR1_RALN)
++            p_Dtsec->internalStatistics.raln += VAL16BIT;
++        if (car1 & CAR1_RFLR)
++            p_Dtsec->internalStatistics.rflr += VAL16BIT;
++        if (car1 & CAR1_RCDE)
++            p_Dtsec->internalStatistics.rcde += VAL16BIT;
++        if (car1 & CAR1_RCSE)
++            p_Dtsec->internalStatistics.rcse += VAL16BIT;
++        if (car1 & CAR1_RUND)
++            p_Dtsec->internalStatistics.rund += VAL16BIT;
++        if (car1 & CAR1_ROVR)
++            p_Dtsec->internalStatistics.rovr += VAL16BIT;
++        if (car1 & CAR1_RFRG)
++            p_Dtsec->internalStatistics.rfrg += VAL16BIT;
++        if (car1 & CAR1_RJBR)
++            p_Dtsec->internalStatistics.rjbr += VAL16BIT;
++        if (car1 & CAR1_RDRP)
++            p_Dtsec->internalStatistics.rdrp += VAL16BIT;
++    }
++    if (car2)
++    {
++        if (car2  & CAR2_TFCS)
++            p_Dtsec->internalStatistics.tfcs += VAL12BIT;
++        if (car2  & CAR2_TBYT)
++            p_Dtsec->internalStatistics.tbyt += (uint64_t)VAL32BIT;
++        if (car2  & CAR2_TPKT)
++            p_Dtsec->internalStatistics.tpkt += VAL22BIT;
++        if (car2  & CAR2_TMCA)
++            p_Dtsec->internalStatistics.tmca += VAL22BIT;
++        if (car2  & CAR2_TBCA)
++            p_Dtsec->internalStatistics.tbca += VAL22BIT;
++        if (car2  & CAR2_TXPF)
++            p_Dtsec->internalStatistics.txpf += VAL16BIT;
++        if (car2  & CAR2_TDRP)
++            p_Dtsec->internalStatistics.tdrp += VAL16BIT;
++    }
++}
++
++/* .............................................................................. */
++
++static uint16_t DtsecGetMaxFrameLength(t_Handle h_Dtsec)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_VALUE(p_Dtsec, E_INVALID_HANDLE, 0);
++    SANITY_CHECK_RETURN_VALUE(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE, 0);
++
++    return fman_dtsec_get_max_frame_len(p_Dtsec->p_MemMap);
++}
++
++/* .............................................................................. */
++
++static void DtsecIsr(t_Handle h_Dtsec)
++{
++    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    uint32_t            event;
++    struct dtsec_regs   *p_DtsecMemMap = p_Dtsec->p_MemMap;
++
++    /* do not handle MDIO events */
++    event = fman_dtsec_get_event(p_DtsecMemMap, (uint32_t)(~(DTSEC_IMASK_MMRDEN | DTSEC_IMASK_MMWREN)));
++
++    event &= fman_dtsec_get_interrupt_mask(p_DtsecMemMap);
++
++    fman_dtsec_ack_event(p_DtsecMemMap, event);
++
++    if (event & DTSEC_IMASK_BREN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_BAB_RX);
++    if (event & DTSEC_IMASK_RXCEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_RX_CTL);
++    if (event & DTSEC_IMASK_MSROEN)
++        UpdateStatistics(p_Dtsec);
++    if (event & DTSEC_IMASK_GTSCEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET);
++    if (event & DTSEC_IMASK_BTEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_BAB_TX);
++    if (event & DTSEC_IMASK_TXCEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_CTL);
++    if (event & DTSEC_IMASK_TXEEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_ERR);
++    if (event & DTSEC_IMASK_LCEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_LATE_COL);
++    if (event & DTSEC_IMASK_CRLEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_COL_RET_LMT);
++    if (event & DTSEC_IMASK_XFUNEN)
++    {
++#ifdef FM_TX_LOCKUP_ERRATA_DTSEC6
++        if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2)
++        {
++            uint32_t  tpkt1, tmpReg1, tpkt2, tmpReg2, i;
++            /* a. Write 0x00E0_0C00 to DTSEC_ID */
++            /* This is a read only regidter */
++
++            /* b. Read and save the value of TPKT */
++            tpkt1 = GET_UINT32(p_DtsecMemMap->tpkt);
++
++            /* c. Read the register at dTSEC address offset 0x32C */
++            tmpReg1 =  GET_UINT32(*(uint32_t*)((uint8_t*)p_DtsecMemMap + 0x32c));
++
++            /* d. Compare bits [9:15] to bits [25:31] of the register at address offset 0x32C. */
++            if ((tmpReg1 & 0x007F0000) != (tmpReg1 & 0x0000007F))
++            {
++                /* If they are not equal, save the value of this register and wait for at least
++                 * MAXFRM*16 ns */
++                XX_UDelay((uint32_t)(MIN(DtsecGetMaxFrameLength(p_Dtsec)*16/1000, 1)));
++            }
++
++            /* e. Read and save TPKT again and read the register at dTSEC address offset
++                0x32C again*/
++            tpkt2 = GET_UINT32(p_DtsecMemMap->tpkt);
++            tmpReg2 = GET_UINT32(*(uint32_t*)((uint8_t*)p_DtsecMemMap + 0x32c));
++
++            /* f. Compare the value of TPKT saved in step b to value read in step e. Also
++                compare bits [9:15] of the register at offset 0x32C saved in step d to the value
++                of bits [9:15] saved in step e. If the two registers values are unchanged, then
++                the transmit portion of the dTSEC controller is locked up and the user should
++                proceed to the recover sequence. */
++            if ((tpkt1 == tpkt2) && ((tmpReg1 & 0x007F0000) == (tmpReg2 & 0x007F0000)))
++            {
++                /* recover sequence */
++
++                /* a.Write a 1 to RCTRL[GRS]*/
++
++                WRITE_UINT32(p_DtsecMemMap->rctrl, GET_UINT32(p_DtsecMemMap->rctrl) | RCTRL_GRS);
++
++                /* b.Wait until IEVENT[GRSC]=1, or at least 100 us has elapsed. */
++                for (i = 0 ; i < 100 ; i++ )
++                {
++                    if (GET_UINT32(p_DtsecMemMap->ievent) & DTSEC_IMASK_GRSCEN)
++                        break;
++                    XX_UDelay(1);
++                }
++                if (GET_UINT32(p_DtsecMemMap->ievent) & DTSEC_IMASK_GRSCEN)
++                    WRITE_UINT32(p_DtsecMemMap->ievent, DTSEC_IMASK_GRSCEN);
++                else
++                    DBG(INFO,("Rx lockup due to dTSEC Tx lockup"));
++
++                /* c.Write a 1 to bit n of FM_RSTC (offset 0x0CC of FPM)*/
++                FmResetMac(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MAC_1G, p_Dtsec->fmMacControllerDriver.macId);
++
++                /* d.Wait 4 Tx clocks (32 ns) */
++                XX_UDelay(1);
++
++                /* e.Write a 0 to bit n of FM_RSTC. */
++                /* cleared by FMAN */
++            }
++        }
++#endif /* FM_TX_LOCKUP_ERRATA_DTSEC6 */
++
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_FIFO_UNDRN);
++    }
++    if (event & DTSEC_IMASK_MAGEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_MAG_PCKT);
++    if (event & DTSEC_IMASK_GRSCEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET);
++    if (event & DTSEC_IMASK_TDPEEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_DATA_ERR);
++    if (event & DTSEC_IMASK_RDPEEN)
++        p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_RX_DATA_ERR);
++
++    /*  - masked interrupts */
++    ASSERT_COND(!(event & DTSEC_IMASK_ABRTEN));
++    ASSERT_COND(!(event & DTSEC_IMASK_IFERREN));
++}
++
++static void DtsecMdioIsr(t_Handle h_Dtsec)
++{
++    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    uint32_t            event;
++    struct dtsec_regs   *p_DtsecMemMap = p_Dtsec->p_MemMap;
++
++    event = GET_UINT32(p_DtsecMemMap->ievent);
++    /* handle only MDIO events */
++    event &= (DTSEC_IMASK_MMRDEN | DTSEC_IMASK_MMWREN);
++    if (event)
++    {
++        event &= GET_UINT32(p_DtsecMemMap->imask);
++
++        WRITE_UINT32(p_DtsecMemMap->ievent, event);
++
++        if (event & DTSEC_IMASK_MMRDEN)
++            p_Dtsec->f_Event(p_Dtsec->h_App, e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET);
++        if (event & DTSEC_IMASK_MMWREN)
++            p_Dtsec->f_Event(p_Dtsec->h_App, e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET);
++    }
++}
++
++static void Dtsec1588Isr(t_Handle h_Dtsec)
++{
++    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    uint32_t            event;
++    struct dtsec_regs   *p_DtsecMemMap = p_Dtsec->p_MemMap;
++
++    if (p_Dtsec->ptpTsuEnabled)
++    {
++        event = fman_dtsec_check_and_clear_tmr_event(p_DtsecMemMap);
++
++        if (event)
++        {
++            ASSERT_COND(event & TMR_PEVENT_TSRE);
++            p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_1588_TS_RX_ERR);
++        }
++    }
++}
++
++/* ........................................................................... */
++
++static void FreeInitResources(t_Dtsec *p_Dtsec)
++{
++    if (p_Dtsec->mdioIrq != NO_IRQ)
++    {
++        XX_DisableIntr(p_Dtsec->mdioIrq);
++        XX_FreeIntr(p_Dtsec->mdioIrq);
++    }
++    FmUnregisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MOD_1G_MAC, p_Dtsec->macId, e_FM_INTR_TYPE_ERR);
++    FmUnregisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MOD_1G_MAC, p_Dtsec->macId, e_FM_INTR_TYPE_NORMAL);
++
++    /* release the driver's group hash table */
++    FreeHashTable(p_Dtsec->p_MulticastAddrHash);
++    p_Dtsec->p_MulticastAddrHash =   NULL;
++
++    /* release the driver's individual hash table */
++    FreeHashTable(p_Dtsec->p_UnicastAddrHash);
++    p_Dtsec->p_UnicastAddrHash =     NULL;
++}
++
++/* ........................................................................... */
++
++static t_Error GracefulStop(t_Dtsec *p_Dtsec, e_CommMode mode)
++{
++    struct dtsec_regs *p_MemMap;
++
++    ASSERT_COND(p_Dtsec);
++
++    p_MemMap = p_Dtsec->p_MemMap;
++    ASSERT_COND(p_MemMap);
++
++    /* Assert the graceful transmit stop bit */
++    if (mode & e_COMM_MODE_RX)
++    {
++        fman_dtsec_stop_rx(p_MemMap);
++
++#ifdef FM_GRS_ERRATA_DTSEC_A002
++        if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2)
++            XX_UDelay(100);
++#else  /* FM_GRS_ERRATA_DTSEC_A002 */
++#ifdef FM_GTS_AFTER_DROPPED_FRAME_ERRATA_DTSEC_A004839
++        XX_UDelay(10);
++#endif /* FM_GTS_AFTER_DROPPED_FRAME_ERRATA_DTSEC_A004839 */
++#endif /* FM_GRS_ERRATA_DTSEC_A002 */
++    }
++
++    if (mode & e_COMM_MODE_TX)
++#if defined(FM_GTS_ERRATA_DTSEC_A004) || defined(FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012)
++    if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2)
++        DBG(INFO, ("GTS not supported due to DTSEC_A004 errata."));
++#else  /* not defined(FM_GTS_ERRATA_DTSEC_A004) ||... */
++#ifdef FM_GTS_UNDERRUN_ERRATA_DTSEC_A0014
++        DBG(INFO, ("GTS not supported due to DTSEC_A0014 errata."));
++#else  /* FM_GTS_UNDERRUN_ERRATA_DTSEC_A0014 */
++        fman_dtsec_stop_tx(p_MemMap);
++#endif /* FM_GTS_UNDERRUN_ERRATA_DTSEC_A0014 */
++#endif /* defined(FM_GTS_ERRATA_DTSEC_A004) ||...  */
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error GracefulRestart(t_Dtsec *p_Dtsec, e_CommMode mode)
++{
++    struct dtsec_regs *p_MemMap;
++
++    ASSERT_COND(p_Dtsec);
++    p_MemMap = p_Dtsec->p_MemMap;
++    ASSERT_COND(p_MemMap);
++
++    /* clear the graceful receive stop bit */
++    if (mode & e_COMM_MODE_TX)
++        fman_dtsec_start_tx(p_MemMap);
++
++    if (mode & e_COMM_MODE_RX)
++        fman_dtsec_start_rx(p_MemMap);
++
++    return E_OK;
++}
++
++
++/*****************************************************************************/
++/*                      dTSEC Configs modification functions                 */
++/*****************************************************************************/
++
++/* .............................................................................. */
++
++static t_Error DtsecConfigLoopback(t_Handle h_Dtsec, bool newVal)
++{
++
++    t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->p_DtsecDriverParam->loopback = newVal;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecConfigMaxFrameLength(t_Handle h_Dtsec, uint16_t newVal)
++{
++    t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->p_DtsecDriverParam->maximum_frame = newVal;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecConfigPadAndCrc(t_Handle h_Dtsec, bool newVal)
++{
++    t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->p_DtsecDriverParam->tx_pad_crc = newVal;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecConfigHalfDuplex(t_Handle h_Dtsec, bool newVal)
++{
++    t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->p_DtsecDriverParam->halfdup_on = newVal;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecConfigTbiPhyAddr(t_Handle h_Dtsec, uint8_t newVal)
++{
++    t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->p_DtsecDriverParam->tbi_phy_addr = newVal;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecConfigLengthCheck(t_Handle h_Dtsec, bool newVal)
++{
++    t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->p_DtsecDriverParam->rx_len_check = newVal;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecConfigException(t_Handle h_Dtsec, e_FmMacExceptions exception, bool enable)
++{
++    t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    uint32_t    bitMask = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    if (exception != e_FM_MAC_EX_1G_1588_TS_RX_ERR)
++    {
++        GET_EXCEPTION_FLAG(bitMask, exception);
++        if (bitMask)
++        {
++            if (enable)
++                p_Dtsec->exceptions |= bitMask;
++            else
++                p_Dtsec->exceptions &= ~bitMask;
++        }
++        else
++            RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++    }
++    else
++    {
++        if (!p_Dtsec->ptpTsuEnabled)
++            RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exception valid for 1588 only"));
++
++        if (enable)
++            p_Dtsec->enTsuErrExeption = TRUE;
++        else
++            p_Dtsec->enTsuErrExeption = FALSE;
++    }
++
++    return E_OK;
++}
++
++
++/*****************************************************************************/
++/*                      dTSEC Run Time API functions                         */
++/*****************************************************************************/
++
++/* .............................................................................. */
++
++static t_Error DtsecEnable(t_Handle h_Dtsec,  e_CommMode mode)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    fman_dtsec_enable(p_Dtsec->p_MemMap,
++                 (bool)!!(mode & e_COMM_MODE_RX),
++                 (bool)!!(mode & e_COMM_MODE_TX));
++
++    GracefulRestart(p_Dtsec, mode);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecDisable (t_Handle h_Dtsec, e_CommMode mode)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    GracefulStop(p_Dtsec, mode);
++
++    fman_dtsec_disable(p_Dtsec->p_MemMap,
++                  (bool)!!(mode & e_COMM_MODE_RX),
++                  (bool)!!(mode & e_COMM_MODE_TX));
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecSetTxPauseFrames(t_Handle h_Dtsec,
++                                     uint8_t  priority,
++                                     uint16_t pauseTime,
++                                     uint16_t threshTime)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    UNUSED(priority);UNUSED(threshTime);
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++#ifdef FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003
++    if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2)
++        if (0 < pauseTime && pauseTime <= 320)
++            RETURN_ERROR(MINOR, E_INVALID_VALUE,
++                     ("This pause-time value of %d is illegal due to errata dTSEC-A003!"
++                      " value should be greater than 320."));
++#endif /* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 */
++
++    fman_dtsec_set_tx_pause_frames(p_Dtsec->p_MemMap, pauseTime);
++    return E_OK;
++}
++
++/* .............................................................................. */
++/* backward compatibility. will be removed in the future. */
++static t_Error DtsecTxMacPause(t_Handle h_Dtsec, uint16_t pauseTime)
++{
++    return DtsecSetTxPauseFrames(h_Dtsec, 0, pauseTime, 0);
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecRxIgnoreMacPause(t_Handle h_Dtsec, bool en)
++{
++    t_Dtsec         *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    bool            accept_pause = !en;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    fman_dtsec_handle_rx_pause(p_Dtsec->p_MemMap, accept_pause);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecEnable1588TimeStamp(t_Handle h_Dtsec)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->ptpTsuEnabled = TRUE;
++    fman_dtsec_set_ts(p_Dtsec->p_MemMap, TRUE);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecDisable1588TimeStamp(t_Handle h_Dtsec)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->ptpTsuEnabled = FALSE;
++    fman_dtsec_set_ts(p_Dtsec->p_MemMap, FALSE);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecGetStatistics(t_Handle h_Dtsec, t_FmMacStatistics *p_Statistics)
++{
++    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    struct dtsec_regs   *p_DtsecMemMap;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_Statistics, E_NULL_POINTER);
++
++    p_DtsecMemMap = p_Dtsec->p_MemMap;
++
++    if (p_Dtsec->statisticsLevel == e_FM_MAC_NONE_STATISTICS)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("Statistics disabled"));
++
++    memset(p_Statistics, 0xff, sizeof(t_FmMacStatistics));
++
++    if (p_Dtsec->statisticsLevel == e_FM_MAC_FULL_STATISTICS)
++    {
++        p_Statistics->eStatPkts64 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR64)
++                + p_Dtsec->internalStatistics.tr64;
++        p_Statistics->eStatPkts65to127 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR127)
++                + p_Dtsec->internalStatistics.tr127;
++        p_Statistics->eStatPkts128to255 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR255)
++                + p_Dtsec->internalStatistics.tr255;
++        p_Statistics->eStatPkts256to511 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR511)
++                + p_Dtsec->internalStatistics.tr511;
++        p_Statistics->eStatPkts512to1023 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR1K)
++                + p_Dtsec->internalStatistics.tr1k;
++        p_Statistics->eStatPkts1024to1518 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TRMAX)
++                + p_Dtsec->internalStatistics.trmax;
++        p_Statistics->eStatPkts1519to1522 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TRMGV)
++                + p_Dtsec->internalStatistics.trmgv;
++
++        /* MIB II */
++        p_Statistics->ifInOctets = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RBYT)
++                + p_Dtsec->internalStatistics.rbyt;
++        p_Statistics->ifInPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RPKT)
++                + p_Dtsec->internalStatistics.rpkt;
++        p_Statistics->ifInUcastPkts = 0;
++        p_Statistics->ifInMcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RMCA)
++                + p_Dtsec->internalStatistics.rmca;
++        p_Statistics->ifInBcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RBCA)
++                + p_Dtsec->internalStatistics.rbca;
++        p_Statistics->ifOutOctets = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TBYT)
++                + p_Dtsec->internalStatistics.tbyt;
++        p_Statistics->ifOutPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TPKT)
++                + p_Dtsec->internalStatistics.tpkt;
++        p_Statistics->ifOutUcastPkts = 0;
++        p_Statistics->ifOutMcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TMCA)
++                + p_Dtsec->internalStatistics.tmca;
++        p_Statistics->ifOutBcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TBCA)
++                + p_Dtsec->internalStatistics.tbca;
++    }
++
++    p_Statistics->eStatFragments = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RFRG)
++            + p_Dtsec->internalStatistics.rfrg;
++    p_Statistics->eStatJabbers = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RJBR)
++            + p_Dtsec->internalStatistics.rjbr;
++    p_Statistics->eStatsDropEvents = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RDRP)
++            + p_Dtsec->internalStatistics.rdrp;
++    p_Statistics->eStatCRCAlignErrors = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RALN)
++            + p_Dtsec->internalStatistics.raln;
++    p_Statistics->eStatUndersizePkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RUND)
++            + p_Dtsec->internalStatistics.rund;
++    p_Statistics->eStatOversizePkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_ROVR)
++            + p_Dtsec->internalStatistics.rovr;
++    p_Statistics->reStatPause = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RXPF)
++            + p_Dtsec->internalStatistics.rxpf;
++    p_Statistics->teStatPause = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TXPF)
++            + p_Dtsec->internalStatistics.txpf;
++    p_Statistics->ifInDiscards = p_Statistics->eStatsDropEvents;
++    p_Statistics->ifInErrors = p_Statistics->eStatsDropEvents + p_Statistics->eStatCRCAlignErrors
++            + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_RFLR) + p_Dtsec->internalStatistics.rflr
++            + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_RCDE) + p_Dtsec->internalStatistics.rcde
++            + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_RCSE) + p_Dtsec->internalStatistics.rcse;
++
++    p_Statistics->ifOutDiscards = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TDRP)
++            + p_Dtsec->internalStatistics.tdrp;
++    p_Statistics->ifOutErrors = p_Statistics->ifOutDiscards                                           /**< Number of frames transmitted with error: */
++            + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_TFCS)
++            + p_Dtsec->internalStatistics.tfcs;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecModifyMacAddress (t_Handle h_Dtsec, t_EnetAddr *p_EnetAddr)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    /* Initialize MAC Station Address registers (1 & 2)    */
++    /* Station address have to be swapped (big endian to little endian */
++    p_Dtsec->addr = ENET_ADDR_TO_UINT64(*p_EnetAddr);
++    fman_dtsec_set_mac_address(p_Dtsec->p_MemMap, (uint8_t *)(*p_EnetAddr));
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecResetCounters (t_Handle h_Dtsec)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    /* clear HW counters */
++    fman_dtsec_reset_stat(p_Dtsec->p_MemMap);
++
++    /* clear SW counters holding carries */
++    memset(&p_Dtsec->internalStatistics, 0, sizeof(t_InternalStatistics));
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecAddExactMatchMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr)
++{
++    t_Dtsec   *p_Dtsec = (t_Dtsec *) h_Dtsec;
++    uint64_t  ethAddr;
++    uint8_t   paddrNum;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    if (ethAddr & GROUP_ADDRESS)
++        /* Multicast address has no effect in PADDR */
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Multicast address"));
++
++    /* Make sure no PADDR contains this address */
++    for (paddrNum = 0; paddrNum < DTSEC_NUM_OF_PADDRS; paddrNum++)
++        if (p_Dtsec->indAddrRegUsed[paddrNum])
++            if (p_Dtsec->paddr[paddrNum] == ethAddr)
++                RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG);
++
++    /* Find first unused PADDR */
++    for (paddrNum = 0; paddrNum < DTSEC_NUM_OF_PADDRS; paddrNum++)
++        if (!(p_Dtsec->indAddrRegUsed[paddrNum]))
++        {
++            /* mark this PADDR as used */
++            p_Dtsec->indAddrRegUsed[paddrNum] = TRUE;
++            /* store address */
++            p_Dtsec->paddr[paddrNum] = ethAddr;
++
++            /* put in hardware */
++            fman_dtsec_add_addr_in_paddr(p_Dtsec->p_MemMap, (uint64_t)PTR_TO_UINT(&ethAddr), paddrNum);
++            p_Dtsec->numOfIndAddrInRegs++;
++
++            return E_OK;
++        }
++
++    /* No free PADDR */
++    RETURN_ERROR(MAJOR, E_FULL, NO_MSG);
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecDelExactMatchMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr)
++{
++    t_Dtsec   *p_Dtsec = (t_Dtsec *) h_Dtsec;
++    uint64_t  ethAddr;
++    uint8_t   paddrNum;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    /* Find used PADDR containing this address */
++    for (paddrNum = 0; paddrNum < DTSEC_NUM_OF_PADDRS; paddrNum++)
++    {
++        if ((p_Dtsec->indAddrRegUsed[paddrNum]) &&
++            (p_Dtsec->paddr[paddrNum] == ethAddr))
++        {
++            /* mark this PADDR as not used */
++            p_Dtsec->indAddrRegUsed[paddrNum] = FALSE;
++            /* clear in hardware */
++            fman_dtsec_clear_addr_in_paddr(p_Dtsec->p_MemMap, paddrNum);
++            p_Dtsec->numOfIndAddrInRegs--;
++
++            return E_OK;
++        }
++    }
++
++    RETURN_ERROR(MAJOR, E_NOT_FOUND, NO_MSG);
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecAddHashMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr)
++{
++    t_Dtsec         *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    t_EthHashEntry  *p_HashEntry;
++    uint64_t        ethAddr;
++    int32_t         bucket;
++    uint32_t        crc;
++    bool            mcast, ghtx;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    ghtx = (bool)((fman_dtsec_get_rctrl(p_Dtsec->p_MemMap) & RCTRL_GHTX) ? TRUE : FALSE);
++    mcast = (bool)((ethAddr & MAC_GROUP_ADDRESS) ? TRUE : FALSE);
++
++    if (ghtx && !mcast) /* Cannot handle unicast mac addr when GHTX is on */
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Could not compute hash bucket"));
++
++    crc = GetMacAddrHashCode(ethAddr);
++
++    /* considering the 9 highest order bits in crc H[8:0]:
++     * if ghtx = 0 H[8:6] (highest order 3 bits) identify the hash register
++     * and H[5:1] (next 5 bits) identify the hash bit
++     * if ghts = 1 H[8:5] (highest order 4 bits) identify the hash register
++     * and H[4:0] (next 5 bits) identify the hash bit.
++     *
++     * In bucket index output the low 5 bits identify the hash register bit,
++     * while the higher 4 bits identify the hash register
++     */
++
++    if (ghtx)
++        bucket = (int32_t)((crc >> 23) & 0x1ff);
++    else {
++        bucket = (int32_t)((crc >> 24) & 0xff);
++        /* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */
++        if (mcast)
++            bucket += 0x100;
++    }
++
++    fman_dtsec_set_bucket(p_Dtsec->p_MemMap, bucket, TRUE);
++
++    /* Create element to be added to the driver hash table */
++    p_HashEntry = (t_EthHashEntry *)XX_Malloc(sizeof(t_EthHashEntry));
++    p_HashEntry->addr = ethAddr;
++    INIT_LIST(&p_HashEntry->node);
++
++    if (ethAddr & MAC_GROUP_ADDRESS)
++        /* Group Address */
++        LIST_AddToTail(&(p_HashEntry->node), &(p_Dtsec->p_MulticastAddrHash->p_Lsts[bucket]));
++    else
++        LIST_AddToTail(&(p_HashEntry->node), &(p_Dtsec->p_UnicastAddrHash->p_Lsts[bucket]));
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecDelHashMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr)
++{
++    t_Dtsec         *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    t_List          *p_Pos;
++    t_EthHashEntry  *p_HashEntry = NULL;
++    uint64_t        ethAddr;
++    int32_t         bucket;
++    uint32_t        crc;
++    bool            mcast, ghtx;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    ghtx = (bool)((fman_dtsec_get_rctrl(p_Dtsec->p_MemMap) & RCTRL_GHTX) ? TRUE : FALSE);
++    mcast = (bool)((ethAddr & MAC_GROUP_ADDRESS) ? TRUE : FALSE);
++
++    if (ghtx && !mcast) /* Cannot handle unicast mac addr when GHTX is on */
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Could not compute hash bucket"));
++
++    crc = GetMacAddrHashCode(ethAddr);
++
++    if (ghtx)
++        bucket = (int32_t)((crc >> 23) & 0x1ff);
++    else {
++        bucket = (int32_t)((crc >> 24) & 0xff);
++        /* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */
++        if (mcast)
++            bucket += 0x100;
++    }
++
++    if (ethAddr & MAC_GROUP_ADDRESS)
++    {
++        /* Group Address */
++        LIST_FOR_EACH(p_Pos, &(p_Dtsec->p_MulticastAddrHash->p_Lsts[bucket]))
++        {
++            p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos);
++            if (p_HashEntry->addr == ethAddr)
++            {
++                LIST_DelAndInit(&p_HashEntry->node);
++                XX_Free(p_HashEntry);
++                break;
++            }
++        }
++        if (LIST_IsEmpty(&p_Dtsec->p_MulticastAddrHash->p_Lsts[bucket]))
++            fman_dtsec_set_bucket(p_Dtsec->p_MemMap, bucket, FALSE);
++    }
++    else
++    {
++        /* Individual Address */
++        LIST_FOR_EACH(p_Pos, &(p_Dtsec->p_UnicastAddrHash->p_Lsts[bucket]))
++        {
++            p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos);
++            if (p_HashEntry->addr == ethAddr)
++            {
++                LIST_DelAndInit(&p_HashEntry->node);
++                XX_Free(p_HashEntry);
++                break;
++            }
++        }
++        if (LIST_IsEmpty(&p_Dtsec->p_UnicastAddrHash->p_Lsts[bucket]))
++            fman_dtsec_set_bucket(p_Dtsec->p_MemMap, bucket, FALSE);
++    }
++
++    /* address does not exist */
++    ASSERT_COND(p_HashEntry != NULL);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecSetPromiscuous(t_Handle h_Dtsec, bool newVal)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    fman_dtsec_set_uc_promisc(p_Dtsec->p_MemMap, newVal);
++    fman_dtsec_set_mc_promisc(p_Dtsec->p_MemMap, newVal);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecSetStatistics(t_Handle h_Dtsec, e_FmMacStatisticsLevel statisticsLevel)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    t_Error     err;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->statisticsLevel = statisticsLevel;
++
++    err = (t_Error)fman_dtsec_set_stat_level(p_Dtsec->p_MemMap,
++                                        (enum dtsec_stat_level)statisticsLevel);
++    if (err != E_OK)
++        return err;
++
++    switch (statisticsLevel)
++    {
++    case (e_FM_MAC_NONE_STATISTICS):
++            p_Dtsec->exceptions &= ~DTSEC_IMASK_MSROEN;
++            break;
++    case (e_FM_MAC_PARTIAL_STATISTICS):
++            p_Dtsec->exceptions |= DTSEC_IMASK_MSROEN;
++            break;
++    case (e_FM_MAC_FULL_STATISTICS):
++            p_Dtsec->exceptions |= DTSEC_IMASK_MSROEN;
++            break;
++        default:
++            RETURN_ERROR(MINOR, E_INVALID_SELECTION, NO_MSG);
++    }
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecSetWakeOnLan(t_Handle h_Dtsec, bool en)
++{
++    t_Dtsec         *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    fman_dtsec_set_wol(p_Dtsec->p_MemMap, en);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecAdjustLink(t_Handle h_Dtsec, e_EnetSpeed speed, bool fullDuplex)
++{
++    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    int                 err;
++    enum enet_interface enet_interface;
++    enum enet_speed     enet_speed;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    p_Dtsec->enetMode = MAKE_ENET_MODE(ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode), speed);
++    enet_interface = (enum enet_interface) ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode);
++    enet_speed = (enum enet_speed) ENET_SPEED_FROM_MODE(p_Dtsec->enetMode);
++    p_Dtsec->halfDuplex = !fullDuplex;
++
++    err = fman_dtsec_adjust_link(p_Dtsec->p_MemMap, enet_interface, enet_speed, fullDuplex);
++
++    if (err == -EINVAL)
++        RETURN_ERROR(MAJOR, E_CONFLICT, ("Ethernet interface does not support Half Duplex mode"));
++
++    return (t_Error)err;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecRestartAutoneg(t_Handle h_Dtsec)
++{
++    t_Dtsec      *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    uint16_t     tmpReg16;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    DTSEC_MII_ReadPhyReg(p_Dtsec, p_Dtsec->tbi_phy_addr, 0, &tmpReg16);
++
++    tmpReg16 &= ~( PHY_CR_SPEED0 | PHY_CR_SPEED1 );
++    tmpReg16 |= (PHY_CR_ANE | PHY_CR_RESET_AN | PHY_CR_FULLDUPLEX | PHY_CR_SPEED1);
++
++    DTSEC_MII_WritePhyReg(p_Dtsec, p_Dtsec->tbi_phy_addr, 0, tmpReg16);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecGetId(t_Handle h_Dtsec, uint32_t *macId)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    *macId = p_Dtsec->macId;
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecGetVersion(t_Handle h_Dtsec, uint32_t *macVersion)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    *macVersion = fman_dtsec_get_revision(p_Dtsec->p_MemMap);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error DtsecSetException(t_Handle h_Dtsec, e_FmMacExceptions exception, bool enable)
++{
++    t_Dtsec     *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    uint32_t    bitMask = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++
++    if (exception != e_FM_MAC_EX_1G_1588_TS_RX_ERR)
++    {
++        GET_EXCEPTION_FLAG(bitMask, exception);
++        if (bitMask)
++        {
++            if (enable)
++                p_Dtsec->exceptions |= bitMask;
++            else
++                p_Dtsec->exceptions &= ~bitMask;
++        }
++        else
++            RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++        if (enable)
++            fman_dtsec_enable_interrupt(p_Dtsec->p_MemMap, bitMask);
++        else
++            fman_dtsec_disable_interrupt(p_Dtsec->p_MemMap, bitMask);
++    }
++    else
++    {
++        if (!p_Dtsec->ptpTsuEnabled)
++            RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exception valid for 1588 only"));
++
++        if (enable)
++        {
++            p_Dtsec->enTsuErrExeption = TRUE;
++            fman_dtsec_enable_tmr_interrupt(p_Dtsec->p_MemMap);
++        }
++        else
++        {
++            p_Dtsec->enTsuErrExeption = FALSE;
++            fman_dtsec_disable_tmr_interrupt(p_Dtsec->p_MemMap);
++        }
++    }
++
++    return E_OK;
++}
++
++
++/*****************************************************************************/
++/*                      dTSEC Init & Free API                                   */
++/*****************************************************************************/
++
++/* .............................................................................. */
++
++static t_Error DtsecInit(t_Handle h_Dtsec)
++{
++    t_Dtsec             *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    struct dtsec_cfg    *p_DtsecDriverParam;
++    t_Error             err;
++    uint16_t            maxFrmLn;
++    enum enet_interface enet_interface;
++    enum enet_speed     enet_speed;
++    t_EnetAddr          ethAddr;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->fmMacControllerDriver.h_Fm, E_INVALID_HANDLE);
++
++    FM_GetRevision(p_Dtsec->fmMacControllerDriver.h_Fm, &p_Dtsec->fmMacControllerDriver.fmRevInfo);
++    CHECK_INIT_PARAMETERS(p_Dtsec, CheckInitParameters);
++
++    p_DtsecDriverParam  = p_Dtsec->p_DtsecDriverParam;
++    p_Dtsec->halfDuplex = p_DtsecDriverParam->halfdup_on;
++
++    enet_interface = (enum enet_interface)ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode);
++    enet_speed = (enum enet_speed)ENET_SPEED_FROM_MODE(p_Dtsec->enetMode);
++    MAKE_ENET_ADDR_FROM_UINT64(p_Dtsec->addr, ethAddr);
++
++    err = (t_Error)fman_dtsec_init(p_Dtsec->p_MemMap,
++                              p_DtsecDriverParam,
++                              enet_interface,
++                              enet_speed,
++                              (uint8_t*)ethAddr,
++                              p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev,
++                              p_Dtsec->fmMacControllerDriver.fmRevInfo.minorRev,
++                              p_Dtsec->exceptions);
++    if (err)
++    {
++        FreeInitResources(p_Dtsec);
++        RETURN_ERROR(MAJOR, err, ("This DTSEC version does not support the required i/f mode"));
++    }
++
++    if (ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode) == e_ENET_IF_SGMII)
++    {
++        uint16_t            tmpReg16;
++
++        /* Configure the TBI PHY Control Register */
++        tmpReg16 = PHY_TBICON_CLK_SEL | PHY_TBICON_SRESET;
++        DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 17, tmpReg16);
++
++        tmpReg16 = PHY_TBICON_CLK_SEL;
++        DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 17, tmpReg16);
++
++        tmpReg16 = (PHY_CR_PHY_RESET | PHY_CR_ANE | PHY_CR_FULLDUPLEX | PHY_CR_SPEED1);
++        DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 0, tmpReg16);
++
++        if (p_Dtsec->enetMode & ENET_IF_SGMII_BASEX)
++            tmpReg16 = PHY_TBIANA_1000X;
++        else
++            tmpReg16 = PHY_TBIANA_SGMII;
++        DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 4, tmpReg16);
++
++        tmpReg16 = (PHY_CR_ANE | PHY_CR_RESET_AN | PHY_CR_FULLDUPLEX | PHY_CR_SPEED1);
++
++        DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 0, tmpReg16);
++    }
++
++    /* Max Frame Length */
++    maxFrmLn = fman_dtsec_get_max_frame_len(p_Dtsec->p_MemMap);
++    err = FmSetMacMaxFrame(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MAC_1G,
++            p_Dtsec->fmMacControllerDriver.macId, maxFrmLn);
++    if (err)
++        RETURN_ERROR(MINOR,err, NO_MSG);
++
++    p_Dtsec->p_MulticastAddrHash = AllocHashTable(EXTENDED_HASH_TABLE_SIZE);
++    if (!p_Dtsec->p_MulticastAddrHash) {
++        FreeInitResources(p_Dtsec);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MC hash table is FAILED"));
++    }
++
++    p_Dtsec->p_UnicastAddrHash = AllocHashTable(HASH_TABLE_SIZE);
++    if (!p_Dtsec->p_UnicastAddrHash)
++    {
++        FreeInitResources(p_Dtsec);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("UC hash table is FAILED"));
++    }
++
++    /* register err intr handler for dtsec to FPM (err)*/
++    FmRegisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm,
++                   e_FM_MOD_1G_MAC,
++                   p_Dtsec->macId,
++                   e_FM_INTR_TYPE_ERR,
++                   DtsecIsr,
++                   p_Dtsec);
++    /* register 1588 intr handler for TMR to FPM (normal)*/
++    FmRegisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm,
++                   e_FM_MOD_1G_MAC,
++                   p_Dtsec->macId,
++                   e_FM_INTR_TYPE_NORMAL,
++                   Dtsec1588Isr,
++                   p_Dtsec);
++    /* register normal intr handler for dtsec to main interrupt controller. */
++    if (p_Dtsec->mdioIrq != NO_IRQ)
++    {
++        XX_SetIntr(p_Dtsec->mdioIrq, DtsecMdioIsr, p_Dtsec);
++        XX_EnableIntr(p_Dtsec->mdioIrq);
++    }
++
++    XX_Free(p_DtsecDriverParam);
++    p_Dtsec->p_DtsecDriverParam = NULL;
++
++    err = DtsecSetStatistics(h_Dtsec, e_FM_MAC_FULL_STATISTICS);
++    if (err)
++    {
++        FreeInitResources(p_Dtsec);
++        RETURN_ERROR(MAJOR, err, ("Undefined statistics level"));
++    }
++
++    return E_OK;
++}
++
++/* ........................................................................... */
++
++static t_Error DtsecFree(t_Handle h_Dtsec)
++{
++    t_Dtsec      *p_Dtsec = (t_Dtsec *)h_Dtsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++
++    if (p_Dtsec->p_DtsecDriverParam)
++    {
++        /* Called after config */
++        XX_Free(p_Dtsec->p_DtsecDriverParam);
++        p_Dtsec->p_DtsecDriverParam = NULL;
++    }
++    else
++        /* Called after init */
++        FreeInitResources(p_Dtsec);
++
++    XX_Free(p_Dtsec);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static void InitFmMacControllerDriver(t_FmMacControllerDriver *p_FmMacControllerDriver)
++{
++    p_FmMacControllerDriver->f_FM_MAC_Init                      = DtsecInit;
++    p_FmMacControllerDriver->f_FM_MAC_Free                      = DtsecFree;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetStatistics             = DtsecSetStatistics;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback            = DtsecConfigLoopback;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength      = DtsecConfigMaxFrameLength;
++
++    p_FmMacControllerDriver->f_FM_MAC_ConfigWan                 = NULL; /* Not supported on dTSEC */
++
++    p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc           = DtsecConfigPadAndCrc;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex          = DtsecConfigHalfDuplex;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck         = DtsecConfigLengthCheck;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr          = DtsecConfigTbiPhyAddr;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigException           = DtsecConfigException;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit         = NULL;
++
++    p_FmMacControllerDriver->f_FM_MAC_Enable                    = DtsecEnable;
++    p_FmMacControllerDriver->f_FM_MAC_Disable                   = DtsecDisable;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetException              = DtsecSetException;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous            = DtsecSetPromiscuous;
++    p_FmMacControllerDriver->f_FM_MAC_AdjustLink                = DtsecAdjustLink;
++    p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan              = DtsecSetWakeOnLan;
++    p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg            = DtsecRestartAutoneg;
++
++    p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp       = DtsecEnable1588TimeStamp;
++    p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp      = DtsecDisable1588TimeStamp;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames      = DtsecTxMacPause;
++    p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames          = DtsecSetTxPauseFrames;
++    p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames    = DtsecRxIgnoreMacPause;
++
++    p_FmMacControllerDriver->f_FM_MAC_ResetCounters             = DtsecResetCounters;
++    p_FmMacControllerDriver->f_FM_MAC_GetStatistics             = DtsecGetStatistics;
++
++    p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr             = DtsecModifyMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr            = DtsecAddHashMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr         = DtsecDelHashMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr      = DtsecAddExactMatchMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr  = DtsecDelExactMatchMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_GetId                     = DtsecGetId;
++    p_FmMacControllerDriver->f_FM_MAC_GetVersion                = DtsecGetVersion;
++    p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength         = DtsecGetMaxFrameLength;
++
++    p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg           = DTSEC_MII_WritePhyReg;
++    p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg            = DTSEC_MII_ReadPhyReg;
++
++}
++
++
++/*****************************************************************************/
++/*                      dTSEC Config Main Entry                             */
++/*****************************************************************************/
++
++/* .............................................................................. */
++
++t_Handle  DTSEC_Config(t_FmMacParams *p_FmMacParam)
++{
++    t_Dtsec             *p_Dtsec;
++    struct dtsec_cfg    *p_DtsecDriverParam;
++    uintptr_t           baseAddr;
++
++    SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_NULL_POINTER, NULL);
++
++    baseAddr = p_FmMacParam->baseAddr;
++
++    /* allocate memory for the UCC GETH data structure. */
++    p_Dtsec = (t_Dtsec *)XX_Malloc(sizeof(t_Dtsec));
++    if (!p_Dtsec)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("dTSEC driver structure"));
++        return NULL;
++    }
++    memset(p_Dtsec, 0, sizeof(t_Dtsec));
++    InitFmMacControllerDriver(&p_Dtsec->fmMacControllerDriver);
++
++    /* allocate memory for the dTSEC driver parameters data structure. */
++    p_DtsecDriverParam = (struct dtsec_cfg *) XX_Malloc(sizeof(struct dtsec_cfg));
++    if (!p_DtsecDriverParam)
++    {
++        XX_Free(p_Dtsec);
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("dTSEC driver parameters"));
++        return NULL;
++    }
++    memset(p_DtsecDriverParam, 0, sizeof(struct dtsec_cfg));
++
++    /* Plant parameter structure pointer */
++    p_Dtsec->p_DtsecDriverParam = p_DtsecDriverParam;
++
++    fman_dtsec_defconfig(p_DtsecDriverParam);
++
++    p_Dtsec->p_MemMap           = (struct dtsec_regs *)UINT_TO_PTR(baseAddr);
++    p_Dtsec->p_MiiMemMap        = (struct dtsec_mii_reg *)UINT_TO_PTR(baseAddr + DTSEC_TO_MII_OFFSET);
++    p_Dtsec->addr               = ENET_ADDR_TO_UINT64(p_FmMacParam->addr);
++    p_Dtsec->enetMode           = p_FmMacParam->enetMode;
++    p_Dtsec->macId              = p_FmMacParam->macId;
++    p_Dtsec->exceptions         = DEFAULT_exceptions;
++    p_Dtsec->mdioIrq            = p_FmMacParam->mdioIrq;
++    p_Dtsec->f_Exception        = p_FmMacParam->f_Exception;
++    p_Dtsec->f_Event            = p_FmMacParam->f_Event;
++    p_Dtsec->h_App              = p_FmMacParam->h_App;
++    p_Dtsec->ptpTsuEnabled      = p_Dtsec->p_DtsecDriverParam->ptp_tsu_en;
++    p_Dtsec->enTsuErrExeption   = p_Dtsec->p_DtsecDriverParam->ptp_exception_en;
++    p_Dtsec->tbi_phy_addr       = p_Dtsec->p_DtsecDriverParam->tbi_phy_addr;
++
++    return p_Dtsec;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h
+new file mode 100644
+index 0000000..c26f40c
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h
+@@ -0,0 +1,228 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          dtsec.h
++
++ @Description   FM dTSEC ...
++*//***************************************************************************/
++#ifndef __DTSEC_H
++#define __DTSEC_H
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "list_ext.h"
++#include "enet_ext.h"
++
++#include "dtsec_mii_acc.h"
++#include "fm_mac.h"
++
++
++#define DEFAULT_exceptions            \
++    ((uint32_t)(DTSEC_IMASK_BREN    | \
++                DTSEC_IMASK_RXCEN   | \
++                DTSEC_IMASK_BTEN    | \
++                DTSEC_IMASK_TXCEN   | \
++                DTSEC_IMASK_TXEEN   | \
++                DTSEC_IMASK_ABRTEN  | \
++                DTSEC_IMASK_LCEN    | \
++                DTSEC_IMASK_CRLEN   | \
++                DTSEC_IMASK_XFUNEN  | \
++                DTSEC_IMASK_IFERREN | \
++                DTSEC_IMASK_MAGEN   | \
++                DTSEC_IMASK_TDPEEN  | \
++                DTSEC_IMASK_RDPEEN))
++
++#define GET_EXCEPTION_FLAG(bitMask, exception)  switch (exception){ \
++    case e_FM_MAC_EX_1G_BAB_RX:                                     \
++        bitMask = DTSEC_IMASK_BREN; break;                          \
++    case e_FM_MAC_EX_1G_RX_CTL:                                     \
++        bitMask = DTSEC_IMASK_RXCEN; break;                         \
++    case e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET:                    \
++        bitMask = DTSEC_IMASK_GTSCEN ; break;                       \
++    case e_FM_MAC_EX_1G_BAB_TX:                                     \
++        bitMask = DTSEC_IMASK_BTEN   ; break;                       \
++    case e_FM_MAC_EX_1G_TX_CTL:                                     \
++        bitMask = DTSEC_IMASK_TXCEN  ; break;                       \
++    case e_FM_MAC_EX_1G_TX_ERR:                                     \
++        bitMask = DTSEC_IMASK_TXEEN  ; break;                       \
++    case e_FM_MAC_EX_1G_LATE_COL:                                   \
++        bitMask = DTSEC_IMASK_LCEN   ; break;                       \
++    case e_FM_MAC_EX_1G_COL_RET_LMT:                                \
++        bitMask = DTSEC_IMASK_CRLEN  ; break;                       \
++    case e_FM_MAC_EX_1G_TX_FIFO_UNDRN:                              \
++        bitMask = DTSEC_IMASK_XFUNEN ; break;                       \
++    case e_FM_MAC_EX_1G_MAG_PCKT:                                   \
++        bitMask = DTSEC_IMASK_MAGEN ; break;                        \
++    case e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET:                         \
++        bitMask = DTSEC_IMASK_MMRDEN; break;                        \
++    case e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET:                         \
++        bitMask = DTSEC_IMASK_MMWREN  ; break;                      \
++    case e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET:                    \
++        bitMask = DTSEC_IMASK_GRSCEN; break;                        \
++    case e_FM_MAC_EX_1G_TX_DATA_ERR:                                \
++        bitMask = DTSEC_IMASK_TDPEEN; break;                        \
++    case e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL:                            \
++        bitMask = DTSEC_IMASK_MSROEN ; break;                       \
++    default: bitMask = 0;break;}
++
++
++#define MAX_PACKET_ALIGNMENT        31
++#define MAX_INTER_PACKET_GAP        0x7f
++#define MAX_INTER_PALTERNATE_BEB    0x0f
++#define MAX_RETRANSMISSION          0x0f
++#define MAX_COLLISION_WINDOW        0x03ff
++
++
++/********************* From mac ext ******************************************/
++typedef  uint32_t t_ErrorDisable;
++
++#define ERROR_DISABLE_TRANSMIT              0x00400000
++#define ERROR_DISABLE_LATE_COLLISION        0x00040000
++#define ERROR_DISABLE_COLLISION_RETRY_LIMIT 0x00020000
++#define ERROR_DISABLE_TxFIFO_UNDERRUN       0x00010000
++#define ERROR_DISABLE_TxABORT               0x00008000
++#define ERROR_DISABLE_INTERFACE             0x00004000
++#define ERROR_DISABLE_TxDATA_PARITY         0x00000002
++#define ERROR_DISABLE_RxDATA_PARITY         0x00000001
++
++/*****************************************************************************/
++#define DTSEC_NUM_OF_PADDRS             15  /* number of pattern match registers (entries) */
++
++#define GROUP_ADDRESS                   0x0000010000000000LL /* Group address bit indication */
++
++#define HASH_TABLE_SIZE                 256 /* Hash table size (= 32 bits * 8 regs) */
++
++#define HASH_TABLE_SIZE                 256 /* Hash table size (32 bits * 8 regs) */
++#define EXTENDED_HASH_TABLE_SIZE        512 /* Extended Hash table size (32 bits * 16 regs) */
++
++#define DTSEC_TO_MII_OFFSET             0x1000  /* number of pattern match registers (entries) */
++
++#define MAX_PHYS                    32 /* maximum number of phys */
++
++#define     VAL32BIT    0x100000000LL
++#define     VAL22BIT    0x00400000
++#define     VAL16BIT    0x00010000
++#define     VAL12BIT    0x00001000
++
++/* CAR1/2 bits */
++#define CAR1_TR64   0x80000000
++#define CAR1_TR127  0x40000000
++#define CAR1_TR255  0x20000000
++#define CAR1_TR511  0x10000000
++#define CAR1_TRK1   0x08000000
++#define CAR1_TRMAX  0x04000000
++#define CAR1_TRMGV  0x02000000
++
++#define CAR1_RBYT   0x00010000
++#define CAR1_RPKT   0x00008000
++#define CAR1_RMCA   0x00002000
++#define CAR1_RBCA   0x00001000
++#define CAR1_RXPF   0x00000400
++#define CAR1_RALN   0x00000100
++#define CAR1_RFLR   0x00000080
++#define CAR1_RCDE   0x00000040
++#define CAR1_RCSE   0x00000020
++#define CAR1_RUND   0x00000010
++#define CAR1_ROVR   0x00000008
++#define CAR1_RFRG   0x00000004
++#define CAR1_RJBR   0x00000002
++#define CAR1_RDRP   0x00000001
++
++#define CAR2_TFCS   0x00040000
++#define CAR2_TBYT   0x00002000
++#define CAR2_TPKT   0x00001000
++#define CAR2_TMCA   0x00000800
++#define CAR2_TBCA   0x00000400
++#define CAR2_TXPF   0x00000200
++#define CAR2_TDRP   0x00000001
++
++typedef struct t_InternalStatistics
++{
++    uint64_t    tr64;
++    uint64_t    tr127;
++    uint64_t    tr255;
++    uint64_t    tr511;
++    uint64_t    tr1k;
++    uint64_t    trmax;
++    uint64_t    trmgv;
++    uint64_t    rfrg;
++    uint64_t    rjbr;
++    uint64_t    rdrp;
++    uint64_t    raln;
++    uint64_t    rund;
++    uint64_t    rovr;
++    uint64_t    rxpf;
++    uint64_t    txpf;
++    uint64_t    rbyt;
++    uint64_t    rpkt;
++    uint64_t    rmca;
++    uint64_t    rbca;
++    uint64_t    rflr;
++    uint64_t    rcde;
++    uint64_t    rcse;
++    uint64_t    tbyt;
++    uint64_t    tpkt;
++    uint64_t    tmca;
++    uint64_t    tbca;
++    uint64_t    tdrp;
++    uint64_t    tfcs;
++} t_InternalStatistics;
++
++typedef struct {
++    t_FmMacControllerDriver     fmMacControllerDriver;
++    t_Handle                    h_App;            /**< Handle to the upper layer application              */
++    struct dtsec_regs           *p_MemMap;        /**< pointer to dTSEC memory mapped registers.          */
++    struct dtsec_mii_reg        *p_MiiMemMap;     /**< pointer to dTSEC MII memory mapped registers.          */
++    uint64_t                    addr;             /**< MAC address of device;                             */
++    e_EnetMode                  enetMode;         /**< Ethernet physical interface  */
++    t_FmMacExceptionCallback    *f_Exception;
++    int                         mdioIrq;
++    t_FmMacExceptionCallback    *f_Event;
++    bool                        indAddrRegUsed[DTSEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
++    uint64_t                    paddr[DTSEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
++    uint8_t                     numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
++    bool                        halfDuplex;
++    t_InternalStatistics        internalStatistics;
++    t_EthHash                   *p_MulticastAddrHash;      /* pointer to driver's global address hash table  */
++    t_EthHash                   *p_UnicastAddrHash;    /* pointer to driver's individual address hash table  */
++    uint8_t                     macId;
++    uint8_t                     tbi_phy_addr;
++    uint32_t                    exceptions;
++    bool                        ptpTsuEnabled;
++    bool                        enTsuErrExeption;
++    e_FmMacStatisticsLevel      statisticsLevel;
++    struct dtsec_cfg            *p_DtsecDriverParam;
++} t_Dtsec;
++
++
++#endif /* __DTSEC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c
+new file mode 100644
+index 0000000..87da25f
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c
+@@ -0,0 +1,97 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          dtsec_mii_acc.c
++
++ @Description   FM dtsec MII register access MAC ...
++*//***************************************************************************/
++
++#include "error_ext.h"
++#include "std_ext.h"
++#include "fm_mac.h"
++#include "dtsec.h"
++#include "fsl_fman_dtsec_mii_acc.h"
++
++
++/*****************************************************************************/
++t_Error DTSEC_MII_WritePhyReg(t_Handle    h_Dtsec,
++                              uint8_t     phyAddr,
++                              uint8_t     reg,
++                              uint16_t    data)
++{
++    t_Dtsec              *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    struct dtsec_mii_reg *miiregs;
++    uint16_t              dtsec_freq;
++    t_Error                   err;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
++
++    dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
++    miiregs = p_Dtsec->p_MiiMemMap;
++
++    err = (t_Error)fman_dtsec_mii_write_reg(miiregs, phyAddr, reg, data, dtsec_freq);
++
++    return err;
++}
++
++/*****************************************************************************/
++t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec,
++                             uint8_t  phyAddr,
++                             uint8_t  reg,
++                             uint16_t *p_Data)
++{
++    t_Dtsec               *p_Dtsec = (t_Dtsec *)h_Dtsec;
++    struct dtsec_mii_reg  *miiregs;
++    uint16_t               dtsec_freq;
++    t_Error                    err;
++
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
++
++    dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
++    miiregs = p_Dtsec->p_MiiMemMap;
++
++    err = fman_dtsec_mii_read_reg(miiregs, phyAddr, reg, p_Data, dtsec_freq);
++
++    if (*p_Data == 0xffff)
++        RETURN_ERROR(MINOR, E_NO_DEVICE,
++                     ("Read wrong data (0xffff): phyAddr 0x%x, reg 0x%x",
++                      phyAddr, reg));
++    if (err)
++        RETURN_ERROR(MINOR, (t_Error)err, NO_MSG);
++
++    return E_OK;
++}
++
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h
+new file mode 100644
+index 0000000..75cc658
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __DTSEC_MII_ACC_H
++#define __DTSEC_MII_ACC_H
++
++#include "std_ext.h"
++
++
++t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data);
++t_Error DTSEC_MII_ReadPhyReg(t_Handle  h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
++
++#endif /* __DTSEC_MII_ACC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c
+new file mode 100644
+index 0000000..a76ca6a
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c
+@@ -0,0 +1,646 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          fm_mac.c
++
++ @Description   FM MAC ...
++*//***************************************************************************/
++#include "std_ext.h"
++#include "string_ext.h"
++#include "sprint_ext.h"
++#include "error_ext.h"
++#include "fm_ext.h"
++
++#include "fm_common.h"
++#include "fm_mac.h"
++
++
++/* ......................................................................... */
++
++t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver;
++    uint16_t                fmClkFreq;
++
++    SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_INVALID_HANDLE, NULL);
++
++    fmClkFreq = FmGetClockFreq(p_FmMacParam->h_Fm);
++    if (fmClkFreq == 0)
++    {
++        REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Can't get clock for MAC!"));
++        return NULL;
++    }
++
++#if (DPAA_VERSION == 10)
++    if (ENET_SPEED_FROM_MODE(p_FmMacParam->enetMode) < e_ENET_SPEED_10000)
++        p_FmMacControllerDriver = (t_FmMacControllerDriver *)DTSEC_Config(p_FmMacParam);
++    else
++#if FM_MAX_NUM_OF_10G_MACS > 0
++        p_FmMacControllerDriver = (t_FmMacControllerDriver *)TGEC_Config(p_FmMacParam);
++#else
++        p_FmMacControllerDriver = NULL;
++#endif /* FM_MAX_NUM_OF_10G_MACS > 0 */
++#else
++    p_FmMacControllerDriver = (t_FmMacControllerDriver *)MEMAC_Config(p_FmMacParam);
++#endif /* (DPAA_VERSION == 10) */
++
++    if (!p_FmMacControllerDriver)
++        return NULL;
++
++    p_FmMacControllerDriver->h_Fm           = p_FmMacParam->h_Fm;
++    p_FmMacControllerDriver->enetMode       = p_FmMacParam->enetMode;
++    p_FmMacControllerDriver->macId          = p_FmMacParam->macId;
++    p_FmMacControllerDriver->resetOnInit    = DEFAULT_resetOnInit;
++
++    p_FmMacControllerDriver->clkFreq        = fmClkFreq;
++
++    return (t_Handle)p_FmMacControllerDriver;
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_Init (t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->resetOnInit &&
++        !p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit &&
++        (FmResetMac(p_FmMacControllerDriver->h_Fm,
++                    ((ENET_INTERFACE_FROM_MODE(p_FmMacControllerDriver->enetMode) == e_ENET_IF_XGMII) ?
++                        e_FM_MAC_10G : e_FM_MAC_1G),
++                    p_FmMacControllerDriver->macId) != E_OK))
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't reset MAC!"));
++
++    if (p_FmMacControllerDriver->f_FM_MAC_Init)
++        return p_FmMacControllerDriver->f_FM_MAC_Init(h_FmMac);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_Free (t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_Free)
++        return p_FmMacControllerDriver->f_FM_MAC_Free(h_FmMac);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit(h_FmMac, enable);
++
++    p_FmMacControllerDriver->resetOnInit = enable;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool newVal)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback(h_FmMac, newVal);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength(h_FmMac, newVal);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool flag)
++{
++   t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigWan)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigWan(h_FmMac, flag);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool newVal)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc(h_FmMac, newVal);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool newVal)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex(h_FmMac,newVal);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigTbiPhyAddr (t_Handle h_FmMac, uint8_t newVal)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr(h_FmMac,newVal);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool newVal)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck(h_FmMac,newVal);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigException (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigException)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigException(h_FmMac, ex, enable);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
++/* ......................................................................... */
++
++t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround)
++        return p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround(h_FmMac);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
++
++
++/*****************************************************************************/
++/* Run Time Control                                                          */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++t_Error FM_MAC_Enable  (t_Handle h_FmMac,  e_CommMode mode)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_Enable)
++        return p_FmMacControllerDriver->f_FM_MAC_Enable(h_FmMac, mode);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_Disable)
++        return p_FmMacControllerDriver->f_FM_MAC_Disable(h_FmMac, mode);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp)
++        return p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp(h_FmMac);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_Disable1588TimeStamp (t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp)
++        return p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp(h_FmMac);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_SetTxAutoPauseFrames(t_Handle h_FmMac,
++                                    uint16_t pauseTime)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames)
++        return p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames(h_FmMac,
++                                                                      pauseTime);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac,
++                                uint8_t  priority,
++                                uint16_t pauseTime,
++                                uint16_t threshTime)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames)
++        return p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames(h_FmMac,
++                                                                  priority,
++                                                                  pauseTime,
++                                                                  threshTime);
++
++    RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames)
++        return p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames(h_FmMac, en);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_SetWakeOnLan (t_Handle h_FmMac, bool en)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan)
++        return p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan(h_FmMac, en);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ResetCounters (t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ResetCounters)
++        return p_FmMacControllerDriver->f_FM_MAC_ResetCounters(h_FmMac);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
++{
++   t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_SetException)
++        return p_FmMacControllerDriver->f_FM_MAC_SetException(h_FmMac, ex, enable);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_SetStatistics)
++        return p_FmMacControllerDriver->f_FM_MAC_SetStatistics(h_FmMac, statisticsLevel);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_GetStatistics)
++        return p_FmMacControllerDriver->f_FM_MAC_GetStatistics(h_FmMac, p_Statistics);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr)
++        return p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr(h_FmMac, p_EnetAddr);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr)
++        return p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr(h_FmMac, p_EnetAddr);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr)
++        return p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr(h_FmMac, p_EnetAddr);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr)
++        return p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr(h_FmMac, p_EnetAddr);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr)
++        return p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr(h_FmMac, p_EnetAddr);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *macVresion)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_GetVersion)
++        return p_FmMacControllerDriver->f_FM_MAC_GetVersion(h_FmMac, macVresion);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *macId)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_GetId)
++        return p_FmMacControllerDriver->f_FM_MAC_GetId(h_FmMac, macId);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool newVal)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous)
++        return p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous(h_FmMac, newVal);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_AdjustLink)
++        return p_FmMacControllerDriver->f_FM_MAC_AdjustLink(h_FmMac, speed, fullDuplex);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_RestartAutoneg(t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg)
++        return p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg(h_FmMac);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg)
++        return p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg(h_FmMac, phyAddr, reg, data);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac,  uint8_t phyAddr, uint8_t reg, uint16_t *p_Data)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg)
++        return p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg(h_FmMac, phyAddr, reg, p_Data);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++/* ......................................................................... */
++
++uint16_t FM_MAC_GetMaxFrameLength(t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_VALUE(p_FmMacControllerDriver, E_INVALID_HANDLE, 0);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength)
++        return p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength(h_FmMac);
++
++    REPORT_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++    return 0;
++}
++
++#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
++/*****************************************************************************/
++t_Error FM_MAC_DumpRegs(t_Handle h_FmMac)
++{
++    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacControllerDriver->f_FM_MAC_DumpRegs)
++         return p_FmMacControllerDriver->f_FM_MAC_DumpRegs(h_FmMac);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++#endif /* (defined(DEBUG_ERRORS) && ... */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h
+new file mode 100644
+index 0000000..0d7b8d2
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h
+@@ -0,0 +1,224 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          fm_mac.h
++
++ @Description   FM MAC ...
++*//***************************************************************************/
++#ifndef __FM_MAC_H
++#define __FM_MAC_H
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "list_ext.h"
++#include "fm_mac_ext.h"
++#include "fm_common.h"
++
++
++#define __ERR_MODULE__  MODULE_FM_MAC
++
++/**************************************************************************//**
++ @Description       defaults
++*//***************************************************************************/
++
++
++#define DEFAULT_halfDuplex                  FALSE
++#define DEFAULT_padAndCrcEnable             TRUE
++#define DEFAULT_resetOnInit                 FALSE
++
++
++typedef struct {
++    uint64_t addr;      /* Ethernet Address  */
++    t_List   node;
++} t_EthHashEntry;
++#define ETH_HASH_ENTRY_OBJ(ptr) LIST_OBJECT(ptr, t_EthHashEntry, node)
++
++typedef struct {
++    uint16_t    size;
++    t_List      *p_Lsts;
++} t_EthHash;
++
++typedef struct {
++    t_Error (*f_FM_MAC_Init) (t_Handle h_FmMac);
++    t_Error (*f_FM_MAC_Free) (t_Handle h_FmMac);
++
++    t_Error (*f_FM_MAC_SetStatistics) (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel);
++    t_Error (*f_FM_MAC_ConfigLoopback) (t_Handle h_FmMac, bool newVal);
++    t_Error (*f_FM_MAC_ConfigMaxFrameLength) (t_Handle h_FmMac, uint16_t newVal);
++    t_Error (*f_FM_MAC_ConfigWan) (t_Handle h_FmMac, bool flag);
++    t_Error (*f_FM_MAC_ConfigPadAndCrc) (t_Handle h_FmMac, bool newVal);
++    t_Error (*f_FM_MAC_ConfigHalfDuplex) (t_Handle h_FmMac, bool newVal);
++    t_Error (*f_FM_MAC_ConfigLengthCheck) (t_Handle h_FmMac, bool newVal);
++    t_Error (*f_FM_MAC_ConfigTbiPhyAddr) (t_Handle h_FmMac, uint8_t newVal);
++    t_Error (*f_FM_MAC_ConfigException) (t_Handle h_FmMac, e_FmMacExceptions, bool enable);
++    t_Error (*f_FM_MAC_ConfigResetOnInit) (t_Handle h_FmMac, bool enable);
++#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
++    t_Error (*f_FM_MAC_ConfigSkipFman11Workaround) (t_Handle h_FmMac);
++#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
++
++    t_Error (*f_FM_MAC_SetException) (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable);
++
++    t_Error (*f_FM_MAC_Enable)  (t_Handle h_FmMac,  e_CommMode mode);
++    t_Error (*f_FM_MAC_Disable) (t_Handle h_FmMac, e_CommMode mode);
++    t_Error (*f_FM_MAC_Enable1588TimeStamp) (t_Handle h_FmMac);
++    t_Error (*f_FM_MAC_Disable1588TimeStamp) (t_Handle h_FmMac);
++    t_Error (*f_FM_MAC_Reset)   (t_Handle h_FmMac, bool wait);
++
++    t_Error (*f_FM_MAC_SetTxAutoPauseFrames) (t_Handle h_FmMac,
++                                              uint16_t pauseTime);
++    t_Error (*f_FM_MAC_SetTxPauseFrames) (t_Handle h_FmMac,
++                                          uint8_t  priority,
++                                          uint16_t pauseTime,
++                                          uint16_t threshTime);
++    t_Error (*f_FM_MAC_SetRxIgnorePauseFrames) (t_Handle h_FmMac, bool en);
++
++    t_Error (*f_FM_MAC_ResetCounters) (t_Handle h_FmMac);
++    t_Error (*f_FM_MAC_GetStatistics) (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics);
++
++    t_Error (*f_FM_MAC_ModifyMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
++    t_Error (*f_FM_MAC_AddHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
++    t_Error (*f_FM_MAC_RemoveHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
++    t_Error (*f_FM_MAC_AddExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
++    t_Error (*f_FM_MAC_RemovelExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
++
++    t_Error (*f_FM_MAC_SetPromiscuous) (t_Handle h_FmMac, bool newVal);
++    t_Error (*f_FM_MAC_AdjustLink)     (t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
++    t_Error (*f_FM_MAC_RestartAutoneg) (t_Handle h_FmMac);
++
++    t_Error (*f_FM_MAC_SetWakeOnLan)   (t_Handle h_FmMac, bool en);
++
++    t_Error (*f_FM_MAC_GetId) (t_Handle h_FmMac, uint32_t *macId);
++
++    t_Error (*f_FM_MAC_GetVersion) (t_Handle h_FmMac, uint32_t *macVersion);
++
++    uint16_t (*f_FM_MAC_GetMaxFrameLength) (t_Handle h_FmMac);
++
++    t_Error (*f_FM_MAC_MII_WritePhyReg)(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data);
++    t_Error (*f_FM_MAC_MII_ReadPhyReg)(t_Handle h_FmMac,  uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
++
++#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
++    t_Error (*f_FM_MAC_DumpRegs) (t_Handle h_FmMac);
++#endif /* (defined(DEBUG_ERRORS) && ... */
++
++    t_Handle            h_Fm;
++    t_FmRevisionInfo    fmRevInfo;
++    e_EnetMode          enetMode;
++    uint8_t             macId;
++    bool                resetOnInit;
++    uint16_t            clkFreq;
++} t_FmMacControllerDriver;
++
++
++#if (DPAA_VERSION == 10)
++t_Handle    DTSEC_Config(t_FmMacParams *p_FmMacParam);
++t_Handle    TGEC_Config(t_FmMacParams *p_FmMacParams);
++#else
++t_Handle    MEMAC_Config(t_FmMacParams *p_FmMacParam);
++#endif /* (DPAA_VERSION == 10) */
++uint16_t    FM_MAC_GetMaxFrameLength(t_Handle FmMac);
++
++
++/* ........................................................................... */
++
++static __inline__ t_EthHashEntry *DequeueAddrFromHashEntry(t_List *p_AddrLst)
++{
++   t_EthHashEntry *p_HashEntry = NULL;
++    if (!LIST_IsEmpty(p_AddrLst))
++    {
++        p_HashEntry = ETH_HASH_ENTRY_OBJ(p_AddrLst->p_Next);
++        LIST_DelAndInit(&p_HashEntry->node);
++    }
++    return p_HashEntry;
++}
++
++/* ........................................................................... */
++
++static __inline__ void FreeHashTable(t_EthHash *p_Hash)
++{
++    t_EthHashEntry  *p_HashEntry;
++    int             i = 0;
++
++    if (p_Hash)
++    {
++        if  (p_Hash->p_Lsts)
++        {
++            for (i=0; i<p_Hash->size; i++)
++            {
++                p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
++                while (p_HashEntry)
++                {
++                    XX_Free(p_HashEntry);
++                    p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
++                }
++            }
++
++            XX_Free(p_Hash->p_Lsts);
++        }
++
++        XX_Free(p_Hash);
++    }
++}
++
++/* ........................................................................... */
++
++static __inline__ t_EthHash * AllocHashTable(uint16_t size)
++{
++    uint32_t    i;
++    t_EthHash *p_Hash;
++
++    /* Allocate address hash table */
++    p_Hash = (t_EthHash *)XX_Malloc(sizeof(t_EthHash));
++    if (!p_Hash)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table"));
++        return NULL;
++    }
++    p_Hash->size = size;
++
++    p_Hash->p_Lsts = (t_List *)XX_Malloc(p_Hash->size*sizeof(t_List));
++    if (!p_Hash->p_Lsts)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table"));
++        XX_Free(p_Hash);
++        return NULL;
++    }
++
++    for (i=0 ; i<p_Hash->size; i++)
++        INIT_LIST(&p_Hash->p_Lsts[i]);
++
++    return p_Hash;
++}
++
++
++#endif /* __FM_MAC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.c
+new file mode 100644
+index 0000000..b6a4ca2
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.c
+@@ -0,0 +1,119 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "fman_crc32.h"
++#include "common/general.h"
++
++
++/* precomputed CRC values for address hashing */
++static const uint32_t crc_tbl[256] = {
++	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
++	0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
++	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
++	0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
++	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
++	0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
++	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
++	0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
++	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
++	0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
++	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
++	0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
++	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
++	0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
++	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
++	0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
++	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
++	0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
++	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
++	0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
++	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
++	0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
++	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
++	0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
++	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
++	0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
++	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
++	0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
++	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
++	0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
++	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
++	0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
++	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
++	0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
++	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
++	0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
++	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
++	0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
++	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
++	0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
++	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
++	0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
++	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
++};
++
++/* Get the mirrored value of a byte size number. (0x11010011 --> 0x11001011) */
++static inline uint8_t get_mirror8(uint8_t n)
++{
++	uint8_t mirror[16] = {
++		0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e,
++		0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
++	};
++	return (uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4])));
++}
++
++static inline uint32_t get_mirror32(uint32_t n)
++{
++	return ((uint32_t)get_mirror8((uint8_t)(n))<<24) |
++		((uint32_t)get_mirror8((uint8_t)(n>>8))<<16) |
++		((uint32_t)get_mirror8((uint8_t)(n>>16))<<8) |
++		((uint32_t)get_mirror8((uint8_t)(n>>24)));
++}
++
++uint32_t get_mac_addr_crc(uint64_t _addr)
++{
++	uint32_t i;
++	uint8_t  data;
++	uint32_t crc;
++
++	/* CRC calculation */
++	crc = 0xffffffff;
++	for (i = 0; i < 6; i++) {
++		data = (uint8_t)(_addr >> ((5-i)*8));
++		crc = crc ^ data;
++		crc = crc_tbl[crc&0xff] ^ (crc>>8);
++	}
++
++	crc = get_mirror32(crc);
++	return crc;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.h
+new file mode 100644
+index 0000000..6e32fdc
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.h
+@@ -0,0 +1,43 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#ifndef __FMAN_CRC32_H
++#define __FMAN_CRC32_H
++
++#include "common/general.h"
++
++
++uint32_t get_mac_addr_crc(uint64_t _addr);
++
++
++#endif /* __FMAN_CRC32_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c
+new file mode 100644
+index 0000000..5b09286
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c
+@@ -0,0 +1,845 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "fsl_fman_dtsec.h"
++
++
++void fman_dtsec_stop_rx(struct dtsec_regs *regs)
++{
++	/* Assert the graceful stop bit */
++	iowrite32be(ioread32be(&regs->rctrl) | RCTRL_GRS, &regs->rctrl);
++}
++
++void fman_dtsec_stop_tx(struct dtsec_regs *regs)
++{
++	/* Assert the graceful stop bit */
++	iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_GTS, &regs->tctrl);
++}
++
++void fman_dtsec_start_tx(struct dtsec_regs *regs)
++{
++	/* clear the graceful stop bit */
++	iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_GTS, &regs->tctrl);
++}
++
++void fman_dtsec_start_rx(struct dtsec_regs *regs)
++{
++	/* clear the graceful stop bit */
++	iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_GRS, &regs->rctrl);
++}
++
++void fman_dtsec_defconfig(struct dtsec_cfg *cfg)
++{
++	cfg->halfdup_on = DEFAULT_HALFDUP_ON;
++	cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT;
++	cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW;
++	cfg->halfdup_excess_defer = DEFAULT_HALFDUP_EXCESS_DEFER;
++	cfg->halfdup_no_backoff = DEFAULT_HALFDUP_NO_BACKOFF;
++	cfg->halfdup_bp_no_backoff = DEFAULT_HALFDUP_BP_NO_BACKOFF;
++	cfg->halfdup_alt_backoff_val = DEFAULT_HALFDUP_ALT_BACKOFF_VAL;
++	cfg->halfdup_alt_backoff_en = DEFAULT_HALFDUP_ALT_BACKOFF_EN;
++	cfg->rx_drop_bcast = DEFAULT_RX_DROP_BCAST;
++	cfg->rx_short_frm = DEFAULT_RX_SHORT_FRM;
++	cfg->rx_len_check = DEFAULT_RX_LEN_CHECK;
++	cfg->tx_pad_crc = DEFAULT_TX_PAD_CRC;
++	cfg->tx_crc = DEFAULT_TX_CRC;
++	cfg->rx_ctrl_acc = DEFAULT_RX_CTRL_ACC;
++	cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME;
++	cfg->tbipa = DEFAULT_TBIPA; /* PHY address 0 is reserved (DPAA RM)*/
++	cfg->rx_prepend = DEFAULT_RX_PREPEND;
++	cfg->ptp_tsu_en = DEFAULT_PTP_TSU_EN;
++	cfg->ptp_exception_en = DEFAULT_PTP_EXCEPTION_EN;
++	cfg->preamble_len = DEFAULT_PREAMBLE_LEN;
++	cfg->rx_preamble = DEFAULT_RX_PREAMBLE;
++	cfg->tx_preamble = DEFAULT_TX_PREAMBLE;
++	cfg->loopback = DEFAULT_LOOPBACK;
++	cfg->rx_time_stamp_en = DEFAULT_RX_TIME_STAMP_EN;
++	cfg->tx_time_stamp_en = DEFAULT_TX_TIME_STAMP_EN;
++	cfg->rx_flow = DEFAULT_RX_FLOW;
++	cfg->tx_flow = DEFAULT_TX_FLOW;
++	cfg->rx_group_hash_exd = DEFAULT_RX_GROUP_HASH_EXD;
++	cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD;
++	cfg->rx_promisc = DEFAULT_RX_PROMISC;
++	cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1;
++	cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2;
++	cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT;
++	cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG;
++	cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME;
++	cfg->tbi_phy_addr = DEFAULT_TBI_PHY_ADDR;
++	cfg->wake_on_lan = DEFAULT_WAKE_ON_LAN;
++}
++
++int fman_dtsec_init(struct dtsec_regs *regs, struct dtsec_cfg *cfg,
++		enum enet_interface iface_mode,
++		enum enet_speed iface_speed,
++		uint8_t *macaddr,
++		uint8_t fm_rev_maj,
++		uint8_t fm_rev_min,
++		uint32_t exception_mask)
++{
++	bool		is_rgmii = FALSE;
++	bool		is_sgmii = FALSE;
++	bool		is_qsgmii = FALSE;
++	int		i;
++	uint32_t	tmp;
++
++UNUSED(fm_rev_maj);UNUSED(fm_rev_min);
++
++	/* let's start with a soft reset */
++	iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
++	iowrite32be(0, &regs->maccfg1);
++
++	/*************dtsec_id2******************/
++	tmp =  ioread32be(&regs->tsec_id2);
++
++	/* check RGMII support */
++	if (iface_mode == E_ENET_IF_RGMII ||
++			iface_mode == E_ENET_IF_RMII)
++		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
++			return -EINVAL;
++
++	if (iface_mode == E_ENET_IF_SGMII ||
++			iface_mode == E_ENET_IF_MII)
++		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
++			return -EINVAL;
++
++	/***************ECNTRL************************/
++
++	is_rgmii = (bool)((iface_mode == E_ENET_IF_RGMII) ? TRUE : FALSE);
++	is_sgmii = (bool)((iface_mode == E_ENET_IF_SGMII) ? TRUE : FALSE);
++	is_qsgmii = (bool)((iface_mode == E_ENET_IF_QSGMII) ? TRUE : FALSE);
++
++	tmp = 0;
++	if (is_rgmii || iface_mode == E_ENET_IF_GMII)
++		tmp |= DTSEC_ECNTRL_GMIIM;
++	if (is_sgmii)
++		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
++	if (is_qsgmii)
++		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
++				DTSEC_ECNTRL_QSGMIIM);
++	if (is_rgmii)
++		tmp |= DTSEC_ECNTRL_RPM;
++	if (iface_speed == E_ENET_SPEED_100)
++		tmp |= DTSEC_ECNTRL_R100M;
++
++	iowrite32be(tmp, &regs->ecntrl);
++	/***************ECNTRL************************/
++
++	/***************TCTRL************************/
++	tmp = 0;
++	if (cfg->halfdup_on)
++		tmp |= DTSEC_TCTRL_THDF;
++	if (cfg->tx_time_stamp_en)
++		tmp |= DTSEC_TCTRL_TTSE;
++
++	iowrite32be(tmp, &regs->tctrl);
++
++	/***************TCTRL************************/
++
++	/***************PTV************************/
++	tmp = 0;
++
++#ifdef FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1
++	if ((fm_rev_maj == 1) && (fm_rev_min == 0))
++		cfg->tx_pause_time += 2;
++#endif /* FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1 */
++
++	if (cfg->tx_pause_time)
++		tmp |= cfg->tx_pause_time;
++	if (cfg->tx_pause_time_extd)
++		tmp |= cfg->tx_pause_time_extd << PTV_PTE_OFST;
++	iowrite32be(tmp, &regs->ptv);
++
++	/***************RCTRL************************/
++	tmp = 0;
++	tmp |= ((uint32_t)(cfg->rx_prepend & 0x0000001f)) << 16;
++	if (cfg->rx_ctrl_acc)
++		tmp |= RCTRL_CFA;
++	if (cfg->rx_group_hash_exd)
++		tmp |= RCTRL_GHTX;
++	if (cfg->rx_time_stamp_en)
++		tmp |= RCTRL_RTSE;
++	if (cfg->rx_drop_bcast)
++		tmp |= RCTRL_BC_REJ;
++	if (cfg->rx_short_frm)
++		tmp |= RCTRL_RSF;
++	if (cfg->rx_promisc)
++		tmp |= RCTRL_PROM;
++
++	iowrite32be(tmp, &regs->rctrl);
++	/***************RCTRL************************/
++
++	/*
++	 * Assign a Phy Address to the TBI (TBIPA).
++	 * Done also in cases where TBI is not selected to avoid conflict with
++	 * the external PHY's Physical address
++	 */
++	iowrite32be(cfg->tbipa, &regs->tbipa);
++
++	/***************TMR_CTL************************/
++	iowrite32be(0, &regs->tmr_ctrl);
++
++	if (cfg->ptp_tsu_en) {
++		tmp = 0;
++		tmp |= TMR_PEVENT_TSRE;
++		iowrite32be(tmp, &regs->tmr_pevent);
++
++		if (cfg->ptp_exception_en) {
++			tmp = 0;
++			tmp |= TMR_PEMASK_TSREEN;
++			iowrite32be(tmp, &regs->tmr_pemask);
++		}
++	}
++
++	/***************MACCFG1***********************/
++	tmp = 0;
++	if (cfg->loopback)
++		tmp |= MACCFG1_LOOPBACK;
++	if (cfg->rx_flow)
++		tmp |= MACCFG1_RX_FLOW;
++	if (cfg->tx_flow)
++		tmp |= MACCFG1_TX_FLOW;
++	iowrite32be(tmp, &regs->maccfg1);
++
++	/***************MACCFG1***********************/
++
++	/***************MACCFG2***********************/
++	tmp = 0;
++
++	if (iface_speed < E_ENET_SPEED_1000)
++		tmp |= MACCFG2_NIBBLE_MODE;
++	else if (iface_speed == E_ENET_SPEED_1000)
++		tmp |= MACCFG2_BYTE_MODE;
++
++	tmp |= ((uint32_t) cfg->preamble_len & 0x0000000f)
++		<< PREAMBLE_LENGTH_SHIFT;
++
++	if (cfg->rx_preamble)
++		tmp |= MACCFG2_PRE_AM_Rx_EN;
++	if (cfg->tx_preamble)
++		tmp |= MACCFG2_PRE_AM_Tx_EN;
++	if (cfg->rx_len_check)
++		tmp |= MACCFG2_LENGTH_CHECK;
++	if (cfg->tx_pad_crc)
++		tmp |= MACCFG2_PAD_CRC_EN;
++	if (cfg->tx_crc)
++		tmp |= MACCFG2_CRC_EN;
++	if (!cfg->halfdup_on)
++		tmp |= MACCFG2_FULL_DUPLEX;
++	iowrite32be(tmp, &regs->maccfg2);
++
++	/***************MACCFG2***********************/
++
++	/***************IPGIFG************************/
++	tmp = (((cfg->non_back_to_back_ipg1 <<
++		IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT)
++		& IPGIFG_NON_BACK_TO_BACK_IPG_1)
++		| ((cfg->non_back_to_back_ipg2 <<
++		IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT)
++		& IPGIFG_NON_BACK_TO_BACK_IPG_2)
++		| ((cfg->min_ifg_enforcement <<
++		IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT)
++		& IPGIFG_MIN_IFG_ENFORCEMENT)
++		| (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG));
++	iowrite32be(tmp, &regs->ipgifg);
++
++	/***************IPGIFG************************/
++
++	/***************HAFDUP************************/
++	tmp = 0;
++
++	if (cfg->halfdup_alt_backoff_en)
++		tmp = (uint32_t)(HAFDUP_ALT_BEB |
++				((cfg->halfdup_alt_backoff_val & 0x0000000f)
++				 << HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT));
++	if (cfg->halfdup_bp_no_backoff)
++		tmp |= HAFDUP_BP_NO_BACKOFF;
++	if (cfg->halfdup_no_backoff)
++		tmp |= HAFDUP_NO_BACKOFF;
++	if (cfg->halfdup_excess_defer)
++		tmp |= HAFDUP_EXCESS_DEFER;
++	tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT)
++		& HAFDUP_RETRANSMISSION_MAX);
++	tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW);
++
++	iowrite32be(tmp, &regs->hafdup);
++	/***************HAFDUP************************/
++
++	/***************MAXFRM************************/
++	/* Initialize MAXFRM */
++	iowrite32be(cfg->maximum_frame, &regs->maxfrm);
++
++	/***************MAXFRM************************/
++
++	/***************CAM1************************/
++	iowrite32be(0xffffffff, &regs->cam1);
++	iowrite32be(0xffffffff, &regs->cam2);
++
++	/***************IMASK************************/
++	iowrite32be(exception_mask, &regs->imask);
++	/***************IMASK************************/
++
++	/***************IEVENT************************/
++	iowrite32be(0xffffffff, &regs->ievent);
++
++	/***************MACSTNADDR1/2*****************/
++
++	tmp = (uint32_t)((macaddr[5] << 24) |
++			 (macaddr[4] << 16) |
++			 (macaddr[3] << 8) |
++			  macaddr[2]);
++	iowrite32be(tmp, &regs->macstnaddr1);
++
++	tmp = (uint32_t)((macaddr[1] << 24) |
++			 (macaddr[0] << 16));
++	iowrite32be(tmp, &regs->macstnaddr2);
++
++	/***************MACSTNADDR1/2*****************/
++
++	/*****************HASH************************/
++	for (i = 0; i < NUM_OF_HASH_REGS ; i++) {
++		/* Initialize IADDRx */
++		iowrite32be(0, &regs->igaddr[i]);
++		/* Initialize GADDRx */
++		iowrite32be(0, &regs->gaddr[i]);
++	}
++
++	fman_dtsec_reset_stat(regs);
++
++	return 0;
++}
++
++uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs *regs)
++{
++	return (uint16_t)ioread32be(&regs->maxfrm);
++}
++
++void fman_dtsec_set_max_frame_len(struct dtsec_regs *regs, uint16_t length)
++{
++	iowrite32be(length, &regs->maxfrm);
++}
++
++void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *adr)
++{
++	uint32_t tmp;
++
++	tmp = (uint32_t)((adr[5] << 24) |
++			 (adr[4] << 16) |
++			 (adr[3] << 8) |
++			  adr[2]);
++	iowrite32be(tmp, &regs->macstnaddr1);
++
++	tmp = (uint32_t)((adr[1] << 24) |
++			 (adr[0] << 16));
++	iowrite32be(tmp, &regs->macstnaddr2);
++}
++
++void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr)
++{
++	uint32_t tmp1, tmp2;
++
++	tmp1 = ioread32be(&regs->macstnaddr1);
++	tmp2 = ioread32be(&regs->macstnaddr2);
++
++	macaddr[0] = (uint8_t)((tmp2 & 0x00ff0000) >> 16);
++	macaddr[1] = (uint8_t)((tmp2 & 0xff000000) >> 24);
++	macaddr[2] = (uint8_t)(tmp1 & 0x000000ff);
++	macaddr[3] = (uint8_t)((tmp1 & 0x0000ff00) >> 8);
++	macaddr[4] = (uint8_t)((tmp1 & 0x00ff0000) >> 16);
++	macaddr[5] = (uint8_t)((tmp1 & 0xff000000) >> 24);
++}
++
++void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, bool mcast, bool ghtx)
++{
++    int32_t bucket;
++    if (ghtx)
++        bucket = (int32_t)((crc >> 23) & 0x1ff);
++    else {
++        bucket = (int32_t)((crc >> 24) & 0xff);
++        /* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */
++        if (mcast)
++            bucket += 0x100;
++    }
++    fman_dtsec_set_bucket(regs, bucket, TRUE);
++}
++
++void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable)
++{
++	int reg_idx = (bucket >> 5) & 0xf;
++	int bit_idx = bucket & 0x1f;
++	uint32_t bit_mask = 0x80000000 >> bit_idx;
++	uint32_t *reg;
++
++	if (reg_idx > 7)
++		reg = &regs->gaddr[reg_idx-8];
++	else
++		reg = &regs->igaddr[reg_idx];
++
++	if (enable)
++		iowrite32be(ioread32be(reg) | bit_mask, reg);
++	else
++		iowrite32be(ioread32be(reg) & (~bit_mask), reg);
++}
++
++void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, bool ucast)
++{
++	int		i;
++	bool	ghtx;
++
++	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? TRUE : FALSE);
++
++	if (ucast || (ghtx && mcast)) {
++		for (i = 0; i < NUM_OF_HASH_REGS; i++)
++			iowrite32be(0, &regs->igaddr[i]);
++	}
++	if (mcast) {
++		for (i = 0; i < NUM_OF_HASH_REGS; i++)
++			iowrite32be(0, &regs->gaddr[i]);
++	}
++}
++
++int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs *regs,
++		uint8_t addr)
++{
++	if (addr > 0 && addr < 32)
++		iowrite32be(addr, &regs->tbipa);
++	else
++		return -EINVAL;
++
++	return 0;
++}
++
++void fman_dtsec_set_wol(struct dtsec_regs *regs, bool en)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->maccfg2);
++	if (en)
++		tmp |= MACCFG2_MAGIC_PACKET_EN;
++	else
++		tmp &= ~MACCFG2_MAGIC_PACKET_EN;
++	iowrite32be(tmp, &regs->maccfg2);
++}
++
++int fman_dtsec_adjust_link(struct dtsec_regs *regs,
++		enum enet_interface iface_mode,
++		enum enet_speed speed, bool full_dx)
++{
++	uint32_t		tmp;
++
++	UNUSED(iface_mode);
++
++	if ((speed == E_ENET_SPEED_1000) && !full_dx)
++		return -EINVAL;
++
++	tmp = ioread32be(&regs->maccfg2);
++	if (!full_dx)
++		tmp &= ~MACCFG2_FULL_DUPLEX;
++	else
++		tmp |= MACCFG2_FULL_DUPLEX;
++
++	tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
++	if (speed < E_ENET_SPEED_1000)
++		tmp |= MACCFG2_NIBBLE_MODE;
++	else if (speed == E_ENET_SPEED_1000)
++		tmp |= MACCFG2_BYTE_MODE;
++	iowrite32be(tmp, &regs->maccfg2);
++
++	tmp = ioread32be(&regs->ecntrl);
++	if (speed == E_ENET_SPEED_100)
++		tmp |= DTSEC_ECNTRL_R100M;
++	else
++		tmp &= ~DTSEC_ECNTRL_R100M;
++	iowrite32be(tmp, &regs->ecntrl);
++
++	return 0;
++}
++
++void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable)
++{
++	uint32_t		tmp;
++
++	tmp = ioread32be(&regs->rctrl);
++
++	if (enable)
++		tmp |= RCTRL_UPROM;
++	else
++		tmp &= ~RCTRL_UPROM;
++
++	iowrite32be(tmp, &regs->rctrl);
++}
++
++void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable)
++{
++	uint32_t		tmp;
++
++	tmp = ioread32be(&regs->rctrl);
++
++	if (enable)
++		tmp |= RCTRL_MPROM;
++	else
++		tmp &= ~RCTRL_MPROM;
++
++	iowrite32be(tmp, &regs->rctrl);
++}
++
++bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs *regs,
++				uint32_t *car1, uint32_t *car2)
++{
++	/* read carry registers */
++	*car1 = ioread32be(&regs->car1);
++	*car2 = ioread32be(&regs->car2);
++	/* clear carry registers */
++	if (*car1)
++		iowrite32be(*car1, &regs->car1);
++	if (*car2)
++		iowrite32be(*car2, &regs->car2);
++
++	return (bool)((*car1 | *car2) ? TRUE : FALSE);
++}
++
++void fman_dtsec_reset_stat(struct dtsec_regs *regs)
++{
++	/* clear HW counters */
++	iowrite32be(ioread32be(&regs->ecntrl) |
++			DTSEC_ECNTRL_CLRCNT, &regs->ecntrl);
++}
++
++int fman_dtsec_set_stat_level(struct dtsec_regs *regs, enum dtsec_stat_level level)
++{
++	switch (level) {
++	case E_MAC_STAT_NONE:
++		iowrite32be(0xffffffff, &regs->cam1);
++		iowrite32be(0xffffffff, &regs->cam2);
++		iowrite32be(ioread32be(&regs->ecntrl) & ~DTSEC_ECNTRL_STEN,
++				&regs->ecntrl);
++		iowrite32be(ioread32be(&regs->imask) & ~DTSEC_IMASK_MSROEN,
++				&regs->imask);
++		break;
++	case E_MAC_STAT_PARTIAL:
++		iowrite32be(CAM1_ERRORS_ONLY, &regs->cam1);
++		iowrite32be(CAM2_ERRORS_ONLY, &regs->cam2);
++		iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
++				&regs->ecntrl);
++		iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
++				&regs->imask);
++		break;
++	case E_MAC_STAT_MIB_GRP1:
++		iowrite32be((uint32_t)~CAM1_MIB_GRP_1, &regs->cam1);
++		iowrite32be((uint32_t)~CAM2_MIB_GRP_1, &regs->cam2);
++		iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
++				&regs->ecntrl);
++		iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
++				&regs->imask);
++		break;
++	case E_MAC_STAT_FULL:
++		iowrite32be(0, &regs->cam1);
++		iowrite32be(0, &regs->cam2);
++		iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
++				&regs->ecntrl);
++		iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
++				&regs->imask);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en)
++{
++	if (en) {
++		iowrite32be(ioread32be(&regs->rctrl) | RCTRL_RTSE,
++				&regs->rctrl);
++		iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_TTSE,
++				&regs->tctrl);
++	} else {
++		iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_RTSE,
++				&regs->rctrl);
++		iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_TTSE,
++				&regs->tctrl);
++	}
++}
++
++void fman_dtsec_enable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->maccfg1);
++
++	if (apply_rx)
++		tmp |= MACCFG1_RX_EN ;
++
++	if (apply_tx)
++		tmp |= MACCFG1_TX_EN ;
++
++	iowrite32be(tmp, &regs->maccfg1);
++}
++
++void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs *regs, uint8_t paddr_num)
++{
++    iowrite32be(0, &regs->macaddr[paddr_num].exact_match1);
++    iowrite32be(0, &regs->macaddr[paddr_num].exact_match2);
++}
++
++void fman_dtsec_add_addr_in_paddr(struct dtsec_regs *regs,
++				uint64_t addr,
++				uint8_t paddr_num)
++{
++	uint32_t tmp;
++
++	tmp = (uint32_t)(addr);
++	/* swap */
++	tmp = (((tmp & 0x000000FF) << 24) |
++		((tmp & 0x0000FF00) <<  8) |
++		((tmp & 0x00FF0000) >>  8) |
++		((tmp & 0xFF000000) >> 24));
++	iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match1);
++
++	tmp = (uint32_t)(addr>>32);
++	/* swap */
++	tmp = (((tmp & 0x000000FF) << 24) |
++		((tmp & 0x0000FF00) <<  8) |
++		((tmp & 0x00FF0000) >>  8) |
++		((tmp & 0xFF000000) >> 24));
++	iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match2);
++}
++
++void fman_dtsec_disable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->maccfg1);
++
++	if (apply_rx)
++		tmp &= ~MACCFG1_RX_EN;
++
++	if (apply_tx)
++		tmp &= ~MACCFG1_TX_EN;
++
++	iowrite32be(tmp, &regs->maccfg1);
++}
++
++void fman_dtsec_set_tx_pause_frames(struct dtsec_regs *regs, uint16_t time)
++{
++	uint32_t ptv = 0;
++
++	/* fixme: don't enable tx pause for half-duplex */
++
++	if (time) {
++		ptv = ioread32be(&regs->ptv);
++		ptv &= 0xffff0000;
++		ptv |= time & 0x0000ffff;
++		iowrite32be(ptv, &regs->ptv);
++
++		/* trigger the transmission of a flow-control pause frame */
++		iowrite32be(ioread32be(&regs->maccfg1) | MACCFG1_TX_FLOW,
++				&regs->maccfg1);
++	} else
++		iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
++				&regs->maccfg1);
++}
++
++void fman_dtsec_handle_rx_pause(struct dtsec_regs *regs, bool en)
++{
++	uint32_t tmp;
++
++	/* todo: check if mac is set to full-duplex */
++
++	tmp = ioread32be(&regs->maccfg1);
++	if (en)
++		tmp |= MACCFG1_RX_FLOW;
++	else
++		tmp &= ~MACCFG1_RX_FLOW;
++	iowrite32be(tmp, &regs->maccfg1);
++}
++
++uint32_t fman_dtsec_get_rctrl(struct dtsec_regs *regs)
++{
++	return ioread32be(&regs->rctrl);
++}
++
++uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs)
++{
++	return ioread32be(&regs->tsec_id);
++}
++
++uint32_t fman_dtsec_get_event(struct dtsec_regs *regs, uint32_t ev_mask)
++{
++	return ioread32be(&regs->ievent) & ev_mask;
++}
++
++void fman_dtsec_ack_event(struct dtsec_regs *regs, uint32_t ev_mask)
++{
++	iowrite32be(ev_mask, &regs->ievent);
++}
++
++uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs *regs)
++{
++	return ioread32be(&regs->imask);
++}
++
++uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs *regs)
++{
++	uint32_t event;
++
++	event = ioread32be(&regs->tmr_pevent);
++	event &= ioread32be(&regs->tmr_pemask);
++
++	if (event)
++		iowrite32be(event, &regs->tmr_pevent);
++	return event;
++}
++
++void fman_dtsec_enable_tmr_interrupt(struct dtsec_regs *regs)
++{
++	iowrite32be(ioread32be(&regs->tmr_pemask) | TMR_PEMASK_TSREEN,
++			&regs->tmr_pemask);
++}
++
++void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs *regs)
++{
++	iowrite32be(ioread32be(&regs->tmr_pemask) & ~TMR_PEMASK_TSREEN,
++			&regs->tmr_pemask);
++}
++
++void fman_dtsec_enable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)
++{
++	iowrite32be(ioread32be(&regs->imask) | ev_mask, &regs->imask);
++}
++
++void fman_dtsec_disable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)
++{
++	iowrite32be(ioread32be(&regs->imask) & ~ev_mask, &regs->imask);
++}
++
++uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs *regs,
++		enum dtsec_stat_counters reg_name)
++{
++	uint32_t ret_val;
++
++	switch (reg_name) {
++	case E_DTSEC_STAT_TR64:
++		ret_val = ioread32be(&regs->tr64);
++		break;
++	case E_DTSEC_STAT_TR127:
++		ret_val = ioread32be(&regs->tr127);
++		break;
++	case E_DTSEC_STAT_TR255:
++		ret_val = ioread32be(&regs->tr255);
++		break;
++	case E_DTSEC_STAT_TR511:
++		ret_val = ioread32be(&regs->tr511);
++		break;
++	case E_DTSEC_STAT_TR1K:
++		ret_val = ioread32be(&regs->tr1k);
++		break;
++	case E_DTSEC_STAT_TRMAX:
++		ret_val = ioread32be(&regs->trmax);
++		break;
++	case E_DTSEC_STAT_TRMGV:
++		ret_val = ioread32be(&regs->trmgv);
++		break;
++	case E_DTSEC_STAT_RBYT:
++		ret_val = ioread32be(&regs->rbyt);
++		break;
++	case E_DTSEC_STAT_RPKT:
++		ret_val = ioread32be(&regs->rpkt);
++		break;
++	case E_DTSEC_STAT_RMCA:
++		ret_val = ioread32be(&regs->rmca);
++		break;
++	case E_DTSEC_STAT_RBCA:
++		ret_val = ioread32be(&regs->rbca);
++		break;
++	case E_DTSEC_STAT_RXPF:
++		ret_val = ioread32be(&regs->rxpf);
++		break;
++	case E_DTSEC_STAT_RALN:
++		ret_val = ioread32be(&regs->raln);
++		break;
++	case E_DTSEC_STAT_RFLR:
++		ret_val = ioread32be(&regs->rflr);
++		break;
++	case E_DTSEC_STAT_RCDE:
++		ret_val = ioread32be(&regs->rcde);
++		break;
++	case E_DTSEC_STAT_RCSE:
++		ret_val = ioread32be(&regs->rcse);
++		break;
++	case E_DTSEC_STAT_RUND:
++		ret_val = ioread32be(&regs->rund);
++		break;
++	case E_DTSEC_STAT_ROVR:
++		ret_val = ioread32be(&regs->rovr);
++		break;
++	case E_DTSEC_STAT_RFRG:
++		ret_val = ioread32be(&regs->rfrg);
++		break;
++	case E_DTSEC_STAT_RJBR:
++		ret_val = ioread32be(&regs->rjbr);
++		break;
++	case E_DTSEC_STAT_RDRP:
++		ret_val = ioread32be(&regs->rdrp);
++		break;
++	case E_DTSEC_STAT_TFCS:
++		ret_val = ioread32be(&regs->tfcs);
++		break;
++	case E_DTSEC_STAT_TBYT:
++		ret_val = ioread32be(&regs->tbyt);
++		break;
++	case E_DTSEC_STAT_TPKT:
++		ret_val = ioread32be(&regs->tpkt);
++		break;
++	case E_DTSEC_STAT_TMCA:
++		ret_val = ioread32be(&regs->tmca);
++		break;
++	case E_DTSEC_STAT_TBCA:
++		ret_val = ioread32be(&regs->tbca);
++		break;
++	case E_DTSEC_STAT_TXPF:
++		ret_val = ioread32be(&regs->txpf);
++		break;
++	case E_DTSEC_STAT_TNCL:
++		ret_val = ioread32be(&regs->tncl);
++		break;
++	case E_DTSEC_STAT_TDRP:
++		ret_val = ioread32be(&regs->tdrp);
++		break;
++	default:
++		ret_val = 0;
++	}
++
++	return ret_val;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c
+new file mode 100644
+index 0000000..8819f8f
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c
+@@ -0,0 +1,163 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "common/general.h"
++#include "fsl_fman_dtsec_mii_acc.h"
++
++
++/**
++ * dtsec_mii_get_div() - calculates the value of the dtsec mii divider
++ * @dtsec_freq:		dtsec clock frequency (in Mhz)
++ *
++ * This function calculates the dtsec mii clock divider that determines
++ * the MII MDC clock. MII MDC clock will be set to work in the range
++ * of 1.5 to 2.5Mhz
++ * The output of this function is the value of MIIMCFG[MgmtClk] which
++ * implicitly determines the divider value.
++ * Note: the dTSEC system clock is equal to 1/2 of the FMan clock.
++ *
++ * The table below which reflects dtsec_mii_get_div() functionality
++ * shows the relations among dtsec_freq, MgmtClk, actual divider
++ * and the MII frequency:
++ *
++ * dtsec freq   MgmtClk     div        MII freq Mhz
++ * [0.....80]     1      (1/4)(1/8)    [0   to 2.5]
++ * [81...120]     2      (1/6)(1/8)    [1.6 to 2.5]
++ * [121..160]     3      (1/8)(1/8)    [1.8 to 2.5]
++ * [161..200]     4      (1/10)(1/8)   [2.0 to 2.5]
++ * [201..280]     5      (1/14)(1/8)   [1.8 to 2.5]
++ * [281..400]     6      (1/20)(1/8)   [1.1 to 2.5]
++ * [401..560]     7      (1/28)(1/8)   [1.8 to 2.5]
++ * [560..frq]     7      (1/28)(1/8)   [frq/224]
++ *
++ * Returns: the MIIMCFG[MgmtClk] appropriate value
++ */
++
++static uint8_t dtsec_mii_get_div(uint16_t dtsec_freq)
++{
++	uint16_t mgmt_clk;
++
++	if (dtsec_freq < 80) mgmt_clk = 1;
++	else if (dtsec_freq < 120) mgmt_clk = 2;
++	else if (dtsec_freq < 160) mgmt_clk = 3;
++	else if (dtsec_freq < 200) mgmt_clk = 4;
++	else if (dtsec_freq < 280) mgmt_clk = 5;
++	else if (dtsec_freq < 400) mgmt_clk = 6;
++	else mgmt_clk = 7;
++
++	return (uint8_t)mgmt_clk;
++}
++
++void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs)
++{
++	/* Reset the management interface */
++	iowrite32be(ioread32be(&regs->miimcfg) | MIIMCFG_RESET_MGMT,
++			&regs->miimcfg);
++	iowrite32be(ioread32be(&regs->miimcfg) & ~MIIMCFG_RESET_MGMT,
++			&regs->miimcfg);
++}
++
++
++int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr,
++		uint8_t reg, uint16_t data, uint16_t dtsec_freq)
++{
++	uint32_t	tmp;
++
++	/* Setup the MII Mgmt clock speed */
++	iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
++	wmb();
++
++	/* Stop the MII management read cycle */
++	iowrite32be(0, &regs->miimcom);
++	/* Dummy read to make sure MIIMCOM is written */
++	tmp = ioread32be(&regs->miimcom);
++	wmb();
++
++	/* Setting up MII Management Address Register */
++	tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
++	iowrite32be(tmp, &regs->miimadd);
++	wmb();
++
++	/* Setting up MII Management Control Register with data */
++	iowrite32be((uint32_t)data, &regs->miimcon);
++	/* Dummy read to make sure MIIMCON is written */
++	tmp = ioread32be(&regs->miimcon);
++	wmb();
++
++	/* Wait until MII management write is complete */
++	/* todo: a timeout could be useful here */
++	while ((ioread32be(&regs->miimind)) & MIIMIND_BUSY)
++		/* busy wait */;
++
++	return 0;
++}
++
++int fman_dtsec_mii_read_reg(struct dtsec_mii_reg *regs, uint8_t  addr,
++		uint8_t reg, uint16_t *data, uint16_t dtsec_freq)
++{
++	uint32_t	tmp;
++
++	/* Setup the MII Mgmt clock speed */
++	iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
++	wmb();
++
++	/* Setting up the MII Management Address Register */
++	tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
++	iowrite32be(tmp, &regs->miimadd);
++	wmb();
++
++	/* Perform an MII management read cycle */
++	iowrite32be(MIIMCOM_READ_CYCLE, &regs->miimcom);
++	/* Dummy read to make sure MIIMCOM is written */
++	tmp = ioread32be(&regs->miimcom);
++	wmb();
++
++	/* Wait until MII management read is complete */
++	/* todo: a timeout could be useful here */
++	while ((ioread32be(&regs->miimind)) & MIIMIND_BUSY)
++		/* busy wait */;
++
++	/* Read MII management status  */
++	*data = (uint16_t)ioread32be(&regs->miimstat);
++	wmb();
++
++	iowrite32be(0, &regs->miimcom);
++	/* Dummy read to make sure MIIMCOM is written */
++	tmp = ioread32be(&regs->miimcom);
++
++	if (*data == 0xffff)
++		return -ENXIO;
++
++	return 0;
++}
++
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac.c
+new file mode 100644
+index 0000000..00995a1
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac.c
+@@ -0,0 +1,511 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "fsl_fman_memac.h"
++
++
++uint32_t fman_memac_get_event(struct memac_regs *regs, uint32_t ev_mask)
++{
++    return ioread32be(&regs->ievent) & ev_mask;
++}
++
++uint32_t fman_memac_get_interrupt_mask(struct memac_regs *regs)
++{
++    return ioread32be(&regs->imask);
++}
++
++void fman_memac_ack_event(struct memac_regs *regs, uint32_t ev_mask)
++{
++    iowrite32be(ev_mask, &regs->ievent);
++}
++
++void fman_memac_set_promiscuous(struct memac_regs *regs, bool val)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->command_config);
++
++    if (val)
++        tmp |= CMD_CFG_PROMIS_EN;
++    else
++        tmp &= ~CMD_CFG_PROMIS_EN;
++
++    iowrite32be(tmp, &regs->command_config);
++}
++
++void fman_memac_clear_addr_in_paddr(struct memac_regs *regs,
++                    uint8_t paddr_num)
++{
++    if (paddr_num == 0) {
++        iowrite32be(0, &regs->mac_addr0.mac_addr_l);
++        iowrite32be(0, &regs->mac_addr0.mac_addr_u);
++    } else {
++        iowrite32be(0x0, &regs->mac_addr[paddr_num - 1].mac_addr_l);
++        iowrite32be(0x0, &regs->mac_addr[paddr_num - 1].mac_addr_u);
++    }
++}
++
++void fman_memac_add_addr_in_paddr(struct memac_regs *regs,
++                    uint8_t *adr,
++                    uint8_t paddr_num)
++{
++    uint32_t tmp0, tmp1;
++
++    tmp0 = (uint32_t)(adr[0] |
++            adr[1] << 8 |
++            adr[2] << 16 |
++            adr[3] << 24);
++    tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
++
++    if (paddr_num == 0) {
++        iowrite32be(tmp0, &regs->mac_addr0.mac_addr_l);
++        iowrite32be(tmp1, &regs->mac_addr0.mac_addr_u);
++    } else {
++        iowrite32be(tmp0, &regs->mac_addr[paddr_num-1].mac_addr_l);
++        iowrite32be(tmp1, &regs->mac_addr[paddr_num-1].mac_addr_u);
++    }
++}
++
++void fman_memac_enable(struct memac_regs *regs, bool apply_rx, bool apply_tx)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->command_config);
++
++    if (apply_rx)
++        tmp |= CMD_CFG_RX_EN;
++
++    if (apply_tx)
++        tmp |= CMD_CFG_TX_EN;
++
++    iowrite32be(tmp, &regs->command_config);
++}
++
++void fman_memac_disable(struct memac_regs *regs, bool apply_rx, bool apply_tx)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->command_config);
++
++    if (apply_rx)
++        tmp &= ~CMD_CFG_RX_EN;
++
++    if (apply_tx)
++        tmp &= ~CMD_CFG_TX_EN;
++
++    iowrite32be(tmp, &regs->command_config);
++}
++
++void fman_memac_reset_stat(struct memac_regs *regs)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->statn_config);
++
++    tmp |= STATS_CFG_CLR;
++
++    iowrite32be(tmp, &regs->statn_config);
++
++    while (ioread32be(&regs->statn_config) & STATS_CFG_CLR);
++}
++
++void fman_memac_reset(struct memac_regs *regs)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->command_config);
++
++    tmp |= CMD_CFG_SW_RESET;
++
++    iowrite32be(tmp, &regs->command_config);
++
++    while (ioread32be(&regs->command_config) & CMD_CFG_SW_RESET);
++}
++
++int fman_memac_init(struct memac_regs *regs,
++        struct memac_cfg *cfg,
++        enum enet_interface enet_interface,
++        enum enet_speed enet_speed,
++	bool slow_10g_if,
++        uint32_t exceptions)
++{
++    uint32_t    tmp;
++
++    /* Config */
++    tmp = 0;
++    if (cfg->wan_mode_enable)
++        tmp |= CMD_CFG_WAN_MODE;
++    if (cfg->promiscuous_mode_enable)
++        tmp |= CMD_CFG_PROMIS_EN;
++    if (cfg->pause_forward_enable)
++        tmp |= CMD_CFG_PAUSE_FWD;
++    if (cfg->pause_ignore)
++        tmp |= CMD_CFG_PAUSE_IGNORE;
++    if (cfg->tx_addr_ins_enable)
++        tmp |= CMD_CFG_TX_ADDR_INS;
++    if (cfg->loopback_enable)
++        tmp |= CMD_CFG_LOOPBACK_EN;
++    if (cfg->cmd_frame_enable)
++        tmp |= CMD_CFG_CNT_FRM_EN;
++    if (cfg->send_idle_enable)
++        tmp |= CMD_CFG_SEND_IDLE;
++    if (cfg->no_length_check_enable)
++        tmp |= CMD_CFG_NO_LEN_CHK;
++    if (cfg->rx_sfd_any)
++        tmp |= CMD_CFG_SFD_ANY;
++    if (cfg->pad_enable)
++        tmp |= CMD_CFG_TX_PAD_EN;
++    if (cfg->wake_on_lan)
++        tmp |= CMD_CFG_MG;
++
++    tmp |= CMD_CFG_CRC_FWD;
++
++    iowrite32be(tmp, &regs->command_config);
++
++    /* Max Frame Length */
++    iowrite32be((uint32_t)cfg->max_frame_length, &regs->maxfrm);
++
++    /* Pause Time */
++    iowrite32be((uint32_t)cfg->pause_quanta, &regs->pause_quanta[0]);
++    iowrite32be((uint32_t)0, &regs->pause_thresh[0]);
++
++    /* IF_MODE */
++    tmp = 0;
++    switch (enet_interface) {
++    case E_ENET_IF_XGMII:
++    case E_ENET_IF_XFI:
++        tmp |= IF_MODE_XGMII;
++        break;
++    default:
++        tmp |= IF_MODE_GMII;
++        if (enet_interface == E_ENET_IF_RGMII && !cfg->loopback_enable)
++            tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
++    }
++    iowrite32be(tmp, &regs->if_mode);
++
++	/* TX_FIFO_SECTIONS */
++	tmp = 0;
++	if (enet_interface == E_ENET_IF_XGMII ||
++		enet_interface == E_ENET_IF_XFI) {
++		if(slow_10g_if) {
++			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
++				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
++		} else {
++			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
++				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
++		}
++	} else {
++		tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
++				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
++	}
++	iowrite32be(tmp, &regs->tx_fifo_sections);
++
++    /* clear all pending events and set-up interrupts */
++    fman_memac_ack_event(regs, 0xffffffff);
++    fman_memac_set_exception(regs, exceptions, TRUE);
++
++    return 0;
++}
++
++void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, bool enable)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->imask);
++    if (enable)
++        tmp |= val;
++    else
++        tmp &= ~val;
++
++    iowrite32be(tmp, &regs->imask);
++}
++
++void fman_memac_reset_filter_table(struct memac_regs *regs)
++{
++	uint32_t i;
++	for (i = 0; i < 64; i++)
++		iowrite32be(i & ~HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
++}
++
++void fman_memac_set_hash_table_entry(struct memac_regs *regs, uint32_t crc)
++{
++	iowrite32be(crc | HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
++}
++
++void fman_memac_set_hash_table(struct memac_regs *regs, uint32_t val)
++{
++    iowrite32be(val, &regs->hashtable_ctrl);
++}
++
++uint16_t fman_memac_get_max_frame_len(struct memac_regs *regs)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->maxfrm);
++
++    return(uint16_t)tmp;
++}
++
++
++void fman_memac_set_tx_pause_frames(struct memac_regs *regs,
++                uint8_t priority,
++                uint16_t pause_time,
++                uint16_t thresh_time)
++{
++    uint32_t tmp;
++
++	tmp = ioread32be(&regs->tx_fifo_sections);
++
++	if (priority == 0xff) {
++		GET_TX_EMPTY_DEFAULT_VALUE(tmp);
++		iowrite32be(tmp, &regs->tx_fifo_sections);
++
++		tmp = ioread32be(&regs->command_config);
++		tmp &= ~CMD_CFG_PFC_MODE;
++		priority = 0;
++	} else {
++		GET_TX_EMPTY_PFC_VALUE(tmp);
++		iowrite32be(tmp, &regs->tx_fifo_sections);
++
++		tmp = ioread32be(&regs->command_config);
++		tmp |= CMD_CFG_PFC_MODE;
++    }
++
++    iowrite32be(tmp, &regs->command_config);
++
++    tmp = ioread32be(&regs->pause_quanta[priority / 2]);
++    if (priority % 2)
++        tmp &= 0x0000FFFF;
++    else
++        tmp &= 0xFFFF0000;
++    tmp |= ((uint32_t)pause_time << (16 * (priority % 2)));
++    iowrite32be(tmp, &regs->pause_quanta[priority / 2]);
++
++    tmp = ioread32be(&regs->pause_thresh[priority / 2]);
++    if (priority % 2)
++            tmp &= 0x0000FFFF;
++    else
++            tmp &= 0xFFFF0000;
++    tmp |= ((uint32_t)thresh_time<<(16 * (priority % 2)));
++    iowrite32be(tmp, &regs->pause_thresh[priority / 2]);
++}
++
++void fman_memac_set_rx_ignore_pause_frames(struct memac_regs    *regs,bool enable)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->command_config);
++    if (enable)
++        tmp |= CMD_CFG_PAUSE_IGNORE;
++    else
++        tmp &= ~CMD_CFG_PAUSE_IGNORE;
++
++    iowrite32be(tmp, &regs->command_config);
++}
++
++void fman_memac_set_wol(struct memac_regs *regs, bool enable)
++{
++    uint32_t tmp;
++
++    tmp = ioread32be(&regs->command_config);
++
++    if (enable)
++        tmp |= CMD_CFG_MG;
++    else
++        tmp &= ~CMD_CFG_MG;
++
++    iowrite32be(tmp, &regs->command_config);
++}
++
++#define GET_MEMAC_CNTR_64(bn) \
++        (ioread32be(&regs->bn ## _l) | \
++        ((uint64_t)ioread32be(&regs->bn ## _u) << 32))
++
++uint64_t fman_memac_get_counter(struct memac_regs *regs,
++                enum memac_counters reg_name)
++{
++    uint64_t ret_val;
++
++    switch (reg_name) {
++    case E_MEMAC_COUNTER_R64:
++        ret_val = GET_MEMAC_CNTR_64(r64);
++        break;
++    case E_MEMAC_COUNTER_R127:
++        ret_val = GET_MEMAC_CNTR_64(r127);
++        break;
++    case E_MEMAC_COUNTER_R255:
++        ret_val = GET_MEMAC_CNTR_64(r255);
++        break;
++    case E_MEMAC_COUNTER_R511:
++        ret_val = GET_MEMAC_CNTR_64(r511);
++        break;
++    case E_MEMAC_COUNTER_R1023:
++        ret_val = GET_MEMAC_CNTR_64(r1023);
++        break;
++    case E_MEMAC_COUNTER_R1518:
++        ret_val = GET_MEMAC_CNTR_64(r1518);
++        break;
++    case E_MEMAC_COUNTER_R1519X:
++        ret_val = GET_MEMAC_CNTR_64(r1519x);
++        break;
++    case E_MEMAC_COUNTER_RFRG:
++        ret_val = GET_MEMAC_CNTR_64(rfrg);
++        break;
++    case E_MEMAC_COUNTER_RJBR:
++        ret_val = GET_MEMAC_CNTR_64(rjbr);
++        break;
++    case E_MEMAC_COUNTER_RDRP:
++        ret_val = GET_MEMAC_CNTR_64(rdrp);
++        break;
++    case E_MEMAC_COUNTER_RALN:
++        ret_val = GET_MEMAC_CNTR_64(raln);
++        break;
++    case E_MEMAC_COUNTER_TUND:
++        ret_val = GET_MEMAC_CNTR_64(tund);
++        break;
++    case E_MEMAC_COUNTER_ROVR:
++        ret_val = GET_MEMAC_CNTR_64(rovr);
++        break;
++    case E_MEMAC_COUNTER_RXPF:
++        ret_val = GET_MEMAC_CNTR_64(rxpf);
++        break;
++    case E_MEMAC_COUNTER_TXPF:
++        ret_val = GET_MEMAC_CNTR_64(txpf);
++        break;
++    case E_MEMAC_COUNTER_ROCT:
++        ret_val = GET_MEMAC_CNTR_64(roct);
++        break;
++    case E_MEMAC_COUNTER_RMCA:
++        ret_val = GET_MEMAC_CNTR_64(rmca);
++        break;
++    case E_MEMAC_COUNTER_RBCA:
++        ret_val = GET_MEMAC_CNTR_64(rbca);
++        break;
++    case E_MEMAC_COUNTER_RPKT:
++        ret_val = GET_MEMAC_CNTR_64(rpkt);
++        break;
++    case E_MEMAC_COUNTER_RUCA:
++        ret_val = GET_MEMAC_CNTR_64(ruca);
++        break;
++    case E_MEMAC_COUNTER_RERR:
++        ret_val = GET_MEMAC_CNTR_64(rerr);
++        break;
++    case E_MEMAC_COUNTER_TOCT:
++        ret_val = GET_MEMAC_CNTR_64(toct);
++        break;
++    case E_MEMAC_COUNTER_TMCA:
++        ret_val = GET_MEMAC_CNTR_64(tmca);
++        break;
++    case E_MEMAC_COUNTER_TBCA:
++        ret_val = GET_MEMAC_CNTR_64(tbca);
++        break;
++    case E_MEMAC_COUNTER_TUCA:
++        ret_val = GET_MEMAC_CNTR_64(tuca);
++        break;
++    case E_MEMAC_COUNTER_TERR:
++        ret_val = GET_MEMAC_CNTR_64(terr);
++        break;
++    default:
++        ret_val = 0;
++    }
++
++    return ret_val;
++}
++
++void fman_memac_adjust_link(struct memac_regs *regs,
++        enum enet_interface iface_mode,
++        enum enet_speed speed, bool full_dx)
++{
++    uint32_t    tmp;
++
++    tmp = ioread32be(&regs->if_mode);
++
++    if (full_dx)
++        tmp &= ~IF_MODE_HD;
++    else
++        tmp |= IF_MODE_HD;
++
++    if (iface_mode == E_ENET_IF_RGMII) {
++        /* Configure RGMII in manual mode */
++        tmp &= ~IF_MODE_RGMII_AUTO;
++        tmp &= ~IF_MODE_RGMII_SP_MASK;
++
++        if (full_dx)
++            tmp |= IF_MODE_RGMII_FD;
++        else
++            tmp &= ~IF_MODE_RGMII_FD;
++
++        switch (speed) {
++        case E_ENET_SPEED_1000:
++            tmp |= IF_MODE_RGMII_1000;
++            break;
++        case E_ENET_SPEED_100:
++            tmp |= IF_MODE_RGMII_100;
++            break;
++        case E_ENET_SPEED_10:
++            tmp |= IF_MODE_RGMII_10;
++            break;
++        default:
++            break;
++        }
++    }
++
++    iowrite32be(tmp, &regs->if_mode);
++}
++
++void fman_memac_defconfig(struct memac_cfg *cfg)
++{
++    cfg->reset_on_init		= FALSE;
++    cfg->wan_mode_enable		= FALSE;
++    cfg->promiscuous_mode_enable	= FALSE;
++    cfg->pause_forward_enable	= FALSE;
++    cfg->pause_ignore		= FALSE;
++    cfg->tx_addr_ins_enable		= FALSE;
++    cfg->loopback_enable		= FALSE;
++    cfg->cmd_frame_enable		= FALSE;
++    cfg->rx_error_discard		= FALSE;
++    cfg->send_idle_enable		= FALSE;
++    cfg->no_length_check_enable	= TRUE;
++    cfg->lgth_check_nostdr		= FALSE;
++    cfg->time_stamp_enable		= FALSE;
++    cfg->tx_ipg_length		= DEFAULT_TX_IPG_LENGTH;
++    cfg->max_frame_length		= DEFAULT_FRAME_LENGTH;
++    cfg->pause_quanta		= DEFAULT_PAUSE_QUANTA;
++    cfg->pad_enable			= TRUE;
++    cfg->phy_tx_ena_on		= FALSE;
++    cfg->rx_sfd_any			= FALSE;
++    cfg->rx_pbl_fwd			= FALSE;
++    cfg->tx_pbl_fwd			= FALSE;
++    cfg->debug_mode			= FALSE;
++    cfg->wake_on_lan        = FALSE;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c
+new file mode 100755
+index 0000000..ccda11e
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c
+@@ -0,0 +1,213 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "fsl_fman_memac_mii_acc.h"
++
++static void write_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
++	uint8_t phy_addr, uint8_t reg, uint16_t data)
++{
++	uint32_t                tmp_reg;
++
++	tmp_reg = ioread32be(&mii_regs->mdio_cfg);
++	/* Leave only MDIO_CLK_DIV bits set on */
++	tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
++	/* Set maximum MDIO_HOLD value to allow phy to see
++	change of data signal */
++	tmp_reg |= MDIO_CFG_HOLD_MASK;
++	/* Add 10G interface mode */
++	tmp_reg |= MDIO_CFG_ENC45;
++	iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
++
++	/* Wait for command completion */
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	/* Specify phy and register to be accessed */
++	iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
++	iowrite32be(reg, &mii_regs->mdio_addr);
++	wmb();
++
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	/* Write data */
++	iowrite32be(data, &mii_regs->mdio_data);
++	wmb();
++
++	/* Wait for write transaction end */
++	while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
++		udelay(1);
++}
++
++static uint32_t read_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
++	uint8_t phy_addr, uint8_t reg, uint16_t *data)
++{
++	uint32_t                tmp_reg;
++
++	tmp_reg = ioread32be(&mii_regs->mdio_cfg);
++	/* Leave only MDIO_CLK_DIV bits set on */
++	tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
++	/* Set maximum MDIO_HOLD value to allow phy to see
++	change of data signal */
++	tmp_reg |= MDIO_CFG_HOLD_MASK;
++	/* Add 10G interface mode */
++	tmp_reg |= MDIO_CFG_ENC45;
++	iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
++
++	/* Wait for command completion */
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	/* Specify phy and register to be accessed */
++	iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
++	iowrite32be(reg, &mii_regs->mdio_addr);
++	wmb();
++
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	/* Read cycle */
++	tmp_reg = phy_addr;
++	tmp_reg |= MDIO_CTL_READ;
++	iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
++	wmb();
++
++	/* Wait for data to be available */
++	while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
++		udelay(1);
++
++	*data =  (uint16_t)ioread32be(&mii_regs->mdio_data);
++
++	/* Check if there was an error */
++	return ioread32be(&mii_regs->mdio_cfg);
++}
++
++static void write_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
++	uint8_t phy_addr, uint8_t reg, uint16_t data)
++{
++	uint32_t                tmp_reg;
++
++	/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
++	tmp_reg = ioread32be(&mii_regs->mdio_cfg);
++	tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
++	iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
++
++	/* Wait for command completion */
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	/* Write transaction */
++	tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
++	tmp_reg |= reg;
++	iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
++
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	iowrite32be(data, &mii_regs->mdio_data);
++
++	wmb();
++
++	/* Wait for write transaction to end */
++	while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
++		udelay(1);
++}
++
++static uint32_t read_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
++	uint8_t phy_addr, uint8_t reg, uint16_t *data)
++{
++	uint32_t tmp_reg;
++
++	/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
++	tmp_reg = ioread32be(&mii_regs->mdio_cfg);
++	tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
++	iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
++
++	/* Wait for command completion */
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	/* Read transaction */
++	tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
++	tmp_reg |= reg;
++	tmp_reg |= MDIO_CTL_READ;
++	iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
++
++	while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
++		udelay(1);
++
++	/* Wait for data to be available */
++	while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
++		udelay(1);
++
++	*data =  (uint16_t)ioread32be(&mii_regs->mdio_data);
++
++	/* Check error */
++	return ioread32be(&mii_regs->mdio_cfg);
++}
++
++/*****************************************************************************/
++int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs,
++	uint8_t phy_addr, uint8_t reg, uint16_t data,
++	enum enet_speed enet_speed)
++{
++	/* Figure out interface type - 10G vs 1G.
++	In 10G interface both phy_addr and devAddr present. */
++	if (enet_speed == E_ENET_SPEED_10000)
++		write_phy_reg_10g(mii_regs, phy_addr, reg, data);
++	else
++		write_phy_reg_1g(mii_regs, phy_addr, reg, data);
++
++	return 0;
++}
++
++/*****************************************************************************/
++int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs,
++	uint8_t phy_addr, uint8_t reg, uint16_t *data,
++	enum enet_speed enet_speed)
++{
++	uint32_t ans;
++	/* Figure out interface type - 10G vs 1G.
++	In 10G interface both phy_addr and devAddr present. */
++	if (enet_speed == E_ENET_SPEED_10000)
++		ans = read_phy_reg_10g(mii_regs, phy_addr, reg, data);
++	else
++		ans = read_phy_reg_1g(mii_regs, phy_addr, reg, data);
++
++	if (ans & MDIO_CFG_READ_ERR)
++		return -EINVAL;
++	return 0;
++}
++
++/* ......................................................................... */
++
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_tgec.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_tgec.c
+new file mode 100644
+index 0000000..fff9d5d
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_tgec.c
+@@ -0,0 +1,367 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "fsl_fman_tgec.h"
++
++
++void fman_tgec_set_mac_address(struct tgec_regs *regs, uint8_t *adr)
++{
++	uint32_t tmp0, tmp1;
++
++	tmp0 = (uint32_t)(adr[0] |
++			adr[1] << 8 |
++			adr[2] << 16 |
++			adr[3] << 24);
++	tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
++	iowrite32be(tmp0, &regs->mac_addr_0);
++	iowrite32be(tmp1, &regs->mac_addr_1);
++}
++
++void fman_tgec_reset_stat(struct tgec_regs *regs)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->command_config);
++
++	tmp |= CMD_CFG_STAT_CLR;
++
++	iowrite32be(tmp, &regs->command_config);
++
++	while (ioread32be(&regs->command_config) & CMD_CFG_STAT_CLR) ;
++}
++
++#define GET_TGEC_CNTR_64(bn) \
++	(((uint64_t)ioread32be(&regs->bn ## _u) << 32) | \
++			ioread32be(&regs->bn ## _l))
++
++uint64_t fman_tgec_get_counter(struct tgec_regs *regs, enum tgec_counters reg_name)
++{
++	uint64_t ret_val;
++
++	switch (reg_name) {
++	case E_TGEC_COUNTER_R64:
++		ret_val = GET_TGEC_CNTR_64(r64);
++		break;
++	case E_TGEC_COUNTER_R127:
++		ret_val = GET_TGEC_CNTR_64(r127);
++		break;
++	case E_TGEC_COUNTER_R255:
++		ret_val = GET_TGEC_CNTR_64(r255);
++		break;
++	case E_TGEC_COUNTER_R511:
++		ret_val = GET_TGEC_CNTR_64(r511);
++		break;
++	case E_TGEC_COUNTER_R1023:
++		ret_val = GET_TGEC_CNTR_64(r1023);
++		break;
++	case E_TGEC_COUNTER_R1518:
++		ret_val = GET_TGEC_CNTR_64(r1518);
++		break;
++	case E_TGEC_COUNTER_R1519X:
++		ret_val = GET_TGEC_CNTR_64(r1519x);
++		break;
++	case E_TGEC_COUNTER_TRFRG:
++		ret_val = GET_TGEC_CNTR_64(trfrg);
++		break;
++	case E_TGEC_COUNTER_TRJBR:
++		ret_val = GET_TGEC_CNTR_64(trjbr);
++		break;
++	case E_TGEC_COUNTER_RDRP:
++		ret_val = GET_TGEC_CNTR_64(rdrp);
++		break;
++	case E_TGEC_COUNTER_RALN:
++		ret_val = GET_TGEC_CNTR_64(raln);
++		break;
++	case E_TGEC_COUNTER_TRUND:
++		ret_val = GET_TGEC_CNTR_64(trund);
++		break;
++	case E_TGEC_COUNTER_TROVR:
++		ret_val = GET_TGEC_CNTR_64(trovr);
++		break;
++	case E_TGEC_COUNTER_RXPF:
++		ret_val = GET_TGEC_CNTR_64(rxpf);
++		break;
++	case E_TGEC_COUNTER_TXPF:
++		ret_val = GET_TGEC_CNTR_64(txpf);
++		break;
++	case E_TGEC_COUNTER_ROCT:
++		ret_val = GET_TGEC_CNTR_64(roct);
++		break;
++	case E_TGEC_COUNTER_RMCA:
++		ret_val = GET_TGEC_CNTR_64(rmca);
++		break;
++	case E_TGEC_COUNTER_RBCA:
++		ret_val = GET_TGEC_CNTR_64(rbca);
++		break;
++	case E_TGEC_COUNTER_RPKT:
++		ret_val = GET_TGEC_CNTR_64(rpkt);
++		break;
++	case E_TGEC_COUNTER_RUCA:
++		ret_val = GET_TGEC_CNTR_64(ruca);
++		break;
++	case E_TGEC_COUNTER_RERR:
++		ret_val = GET_TGEC_CNTR_64(rerr);
++		break;
++	case E_TGEC_COUNTER_TOCT:
++		ret_val = GET_TGEC_CNTR_64(toct);
++		break;
++	case E_TGEC_COUNTER_TMCA:
++		ret_val = GET_TGEC_CNTR_64(tmca);
++		break;
++	case E_TGEC_COUNTER_TBCA:
++		ret_val = GET_TGEC_CNTR_64(tbca);
++		break;
++	case E_TGEC_COUNTER_TUCA:
++		ret_val = GET_TGEC_CNTR_64(tuca);
++		break;
++	case E_TGEC_COUNTER_TERR:
++		ret_val = GET_TGEC_CNTR_64(terr);
++		break;
++	default:
++		ret_val = 0;
++	}
++
++	return ret_val;
++}
++
++void fman_tgec_enable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->command_config);
++	if (apply_rx)
++		tmp |= CMD_CFG_RX_EN;
++	if (apply_tx)
++		tmp |= CMD_CFG_TX_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++void fman_tgec_disable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
++{
++	uint32_t tmp_reg_32;
++
++	tmp_reg_32 = ioread32be(&regs->command_config);
++	if (apply_rx)
++		tmp_reg_32 &= ~CMD_CFG_RX_EN;
++	if (apply_tx)
++		tmp_reg_32 &= ~CMD_CFG_TX_EN;
++	iowrite32be(tmp_reg_32, &regs->command_config);
++}
++
++void fman_tgec_set_promiscuous(struct tgec_regs *regs, bool val)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->command_config);
++	if (val)
++		tmp |= CMD_CFG_PROMIS_EN;
++	else
++		tmp &= ~CMD_CFG_PROMIS_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++void fman_tgec_reset_filter_table(struct tgec_regs *regs)
++{
++	uint32_t i;
++	for (i = 0; i < 512; i++)
++		iowrite32be(i & ~TGEC_HASH_MCAST_EN, &regs->hashtable_ctrl);
++}
++
++void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc)
++{
++    uint32_t hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;        /* Take 9 MSB bits */
++	iowrite32be(hash | TGEC_HASH_MCAST_EN, &regs->hashtable_ctrl);
++}
++
++void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value)
++{
++	iowrite32be(value, &regs->hashtable_ctrl);
++}
++
++void fman_tgec_set_tx_pause_frames(struct tgec_regs *regs, uint16_t pause_time)
++{
++	iowrite32be((uint32_t)pause_time, &regs->pause_quant);
++}
++
++void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs *regs, bool en)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->command_config);
++	if (en)
++		tmp |= CMD_CFG_PAUSE_IGNORE;
++	else
++		tmp &= ~CMD_CFG_PAUSE_IGNORE;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++void fman_tgec_enable_1588_time_stamp(struct tgec_regs *regs, bool en)
++{
++	uint32_t tmp;
++
++	tmp = ioread32be(&regs->command_config);
++	if (en)
++		tmp |= CMD_CFG_EN_TIMESTAMP;
++	else
++		tmp &= ~CMD_CFG_EN_TIMESTAMP;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask)
++{
++	return ioread32be(&regs->ievent) & ev_mask;
++}
++
++void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask)
++{
++	iowrite32be(ev_mask, &regs->ievent);
++}
++
++uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs)
++{
++	return ioread32be(&regs->imask);
++}
++
++void fman_tgec_add_addr_in_paddr(struct tgec_regs *regs, uint8_t *adr)
++{
++	uint32_t tmp0, tmp1;
++
++	tmp0 = (uint32_t)(adr[0] |
++			adr[1] << 8 |
++			adr[2] << 16 |
++			adr[3] << 24);
++	tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
++	iowrite32be(tmp0, &regs->mac_addr_2);
++	iowrite32be(tmp1, &regs->mac_addr_3);
++}
++
++void fman_tgec_clear_addr_in_paddr(struct tgec_regs *regs)
++{
++	iowrite32be(0, &regs->mac_addr_2);
++	iowrite32be(0, &regs->mac_addr_3);
++}
++
++uint32_t fman_tgec_get_revision(struct tgec_regs *regs)
++{
++	return ioread32be(&regs->tgec_id);
++}
++
++void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
++{
++	iowrite32be(ioread32be(&regs->imask) | ev_mask, &regs->imask);
++}
++
++void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
++{
++	iowrite32be(ioread32be(&regs->imask) & ~ev_mask, &regs->imask);
++}
++
++uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs)
++{
++	return (uint16_t) ioread32be(&regs->maxfrm);
++}
++
++void fman_tgec_defconfig(struct tgec_cfg *cfg)
++{
++	cfg->wan_mode_enable = DEFAULT_WAN_MODE_ENABLE;
++	cfg->promiscuous_mode_enable = DEFAULT_PROMISCUOUS_MODE_ENABLE;
++	cfg->pause_forward_enable = DEFAULT_PAUSE_FORWARD_ENABLE;
++	cfg->pause_ignore = DEFAULT_PAUSE_IGNORE;
++	cfg->tx_addr_ins_enable = DEFAULT_TX_ADDR_INS_ENABLE;
++	cfg->loopback_enable = DEFAULT_LOOPBACK_ENABLE;
++	cfg->cmd_frame_enable = DEFAULT_CMD_FRAME_ENABLE;
++	cfg->rx_error_discard = DEFAULT_RX_ERROR_DISCARD;
++	cfg->send_idle_enable = DEFAULT_SEND_IDLE_ENABLE;
++	cfg->no_length_check_enable = DEFAULT_NO_LENGTH_CHECK_ENABLE;
++	cfg->lgth_check_nostdr = DEFAULT_LGTH_CHECK_NOSTDR;
++	cfg->time_stamp_enable = DEFAULT_TIME_STAMP_ENABLE;
++	cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
++	cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH;
++	cfg->pause_quant = DEFAULT_PAUSE_QUANT;
++#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
++	cfg->skip_fman11_workaround = FALSE;
++#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
++}
++
++int fman_tgec_init(struct tgec_regs *regs, struct tgec_cfg *cfg,
++		uint32_t exception_mask)
++{
++	uint32_t tmp;
++
++	/* Config */
++	tmp = 0x40; /* CRC forward */
++	if (cfg->wan_mode_enable)
++		tmp |= CMD_CFG_WAN_MODE;
++	if (cfg->promiscuous_mode_enable)
++		tmp |= CMD_CFG_PROMIS_EN;
++	if (cfg->pause_forward_enable)
++		tmp |= CMD_CFG_PAUSE_FWD;
++	if (cfg->pause_ignore)
++		tmp |= CMD_CFG_PAUSE_IGNORE;
++	if (cfg->tx_addr_ins_enable)
++		tmp |= CMD_CFG_TX_ADDR_INS;
++	if (cfg->loopback_enable)
++		tmp |= CMD_CFG_LOOPBACK_EN;
++	if (cfg->cmd_frame_enable)
++		tmp |= CMD_CFG_CMD_FRM_EN;
++	if (cfg->rx_error_discard)
++		tmp |= CMD_CFG_RX_ER_DISC;
++	if (cfg->send_idle_enable)
++		tmp |= CMD_CFG_SEND_IDLE;
++	if (cfg->no_length_check_enable)
++		tmp |= CMD_CFG_NO_LEN_CHK;
++	if (cfg->time_stamp_enable)
++		tmp |= CMD_CFG_EN_TIMESTAMP;
++	iowrite32be(tmp, &regs->command_config);
++
++	/* Max Frame Length */
++	iowrite32be((uint32_t)cfg->max_frame_length, &regs->maxfrm);
++	/* Pause Time */
++	iowrite32be(cfg->pause_quant, &regs->pause_quant);
++
++	/* clear all pending events and set-up interrupts */
++	fman_tgec_ack_event(regs, 0xffffffff);
++	fman_tgec_enable_interrupt(regs, exception_mask);
++
++	return 0;
++}
++
++void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs *regs)
++{
++	uint32_t tmp;
++
++	/* restore the default tx ipg Length */
++	tmp = (ioread32be(&regs->tx_ipg_len) & ~TGEC_TX_IPG_LENGTH_MASK) | 12;
++
++	iowrite32be(tmp, &regs->tx_ipg_len);
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
+new file mode 100644
+index 0000000..b5aacc9
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
+@@ -0,0 +1,1088 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          memac.c
++
++ @Description   FM mEMAC driver
++*//***************************************************************************/
++
++#include "std_ext.h"
++#include "string_ext.h"
++#include "error_ext.h"
++#include "xx_ext.h"
++#include "endian_ext.h"
++#include "debug_ext.h"
++
++#include "fm_common.h"
++#include "memac.h"
++
++
++/*****************************************************************************/
++/*                      Internal routines                                    */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++static uint32_t GetMacAddrHashCode(uint64_t ethAddr)
++{
++    uint64_t    mask1, mask2;
++    uint32_t    xorVal = 0;
++    uint8_t     i, j;
++
++    for (i=0; i<6; i++)
++    {
++        mask1 = ethAddr & (uint64_t)0x01;
++        ethAddr >>= 1;
++
++        for (j=0; j<7; j++)
++        {
++            mask2 = ethAddr & (uint64_t)0x01;
++            mask1 ^= mask2;
++            ethAddr >>= 1;
++        }
++
++        xorVal |= (mask1 << (5-i));
++    }
++
++    return xorVal;
++}
++
++/* ......................................................................... */
++
++static void SetupSgmiiInternalPhy(t_Memac *p_Memac, uint8_t phyAddr)
++{
++    uint16_t    tmpReg16;
++    e_EnetMode  enetMode;
++
++     /* In case the higher MACs are used (i.e. the MACs that should support 10G),
++        speed=10000 is provided for SGMII ports. Temporary modify enet mode
++        to 1G one, so MII functions can work correctly. */
++    enetMode = p_Memac->enetMode;
++
++    /* SGMII mode + AN enable */
++    tmpReg16 = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
++    if ((p_Memac->enetMode) == e_ENET_MODE_SGMII_2500)
++        tmpReg16 = PHY_SGMII_CR_PHY_RESET | PHY_SGMII_IF_SPEED_GIGABIT | PHY_SGMII_IF_MODE_SGMII;
++
++    p_Memac->enetMode = MAKE_ENET_MODE(ENET_INTERFACE_FROM_MODE(p_Memac->enetMode), e_ENET_SPEED_1000);
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x14, tmpReg16);
++
++    /* Device ability according to SGMII specification */
++    tmpReg16 = PHY_SGMII_DEV_ABILITY_SGMII;
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x4, tmpReg16);
++
++    /* Adjust link timer for SGMII  -
++       According to Cisco SGMII specification the timer should be 1.6 ms.
++       The link_timer register is configured in units of the clock.
++       - When running as 1G SGMII, Serdes clock is 125 MHz, so
++         unit = 1 / (125*10^6 Hz) = 8 ns.
++         1.6 ms in units of 8 ns = 1.6ms / 8ns = 2 * 10^5 = 0x30d40
++       - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
++         unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
++         1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
++       Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
++       we always set up here a value of 2.5 SGMII. */
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x13, 0x0007);
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x12, 0xa120);
++
++    /* Restart AN */
++    tmpReg16 = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x0, tmpReg16);
++
++    /* Restore original enet mode */
++    p_Memac->enetMode = enetMode;
++}
++
++/* ......................................................................... */
++
++static void SetupSgmiiInternalPhyBaseX(t_Memac *p_Memac, uint8_t phyAddr)
++{
++    uint16_t    tmpReg16;
++    e_EnetMode  enetMode;
++
++     /* In case the higher MACs are used (i.e. the MACs that should support 10G),
++        speed=10000 is provided for SGMII ports. Temporary modify enet mode
++        to 1G one, so MII functions can work correctly. */
++    enetMode = p_Memac->enetMode;
++    p_Memac->enetMode = MAKE_ENET_MODE(ENET_INTERFACE_FROM_MODE(p_Memac->enetMode), e_ENET_SPEED_1000);
++
++    /* 1000BaseX mode */
++    tmpReg16 = PHY_SGMII_IF_MODE_1000X;
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x14, tmpReg16);
++
++    /* AN Device capability  */
++    tmpReg16 = PHY_SGMII_DEV_ABILITY_1000X;
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x4, tmpReg16);
++
++    /* Adjust link timer for SGMII  -
++       For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
++       The link_timer register is configured in units of the clock.
++       - When running as 1G SGMII, Serdes clock is 125 MHz, so
++         unit = 1 / (125*10^6 Hz) = 8 ns.
++         10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
++       - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
++         unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
++         10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
++       Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
++       we always set up here a value of 2.5 SGMII. */
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x13, 0x002f);
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x12, 0xaf08);
++
++    /* Restart AN */
++    tmpReg16 = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
++    MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x0, tmpReg16);
++
++    /* Restore original enet mode */
++    p_Memac->enetMode = enetMode;
++}
++
++/* ......................................................................... */
++
++static t_Error CheckInitParameters(t_Memac *p_Memac)
++{
++    e_FmMacType portType;
++
++    portType = ((ENET_SPEED_FROM_MODE(p_Memac->enetMode) < e_ENET_SPEED_10000) ? e_FM_MAC_1G : e_FM_MAC_10G);
++
++#if (FM_MAX_NUM_OF_10G_MACS > 0)
++    if ((portType == e_FM_MAC_10G) && (p_Memac->macId >= FM_MAX_NUM_OF_10G_MACS))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("10G MAC ID must be less than %d", FM_MAX_NUM_OF_10G_MACS));
++#endif /* (FM_MAX_NUM_OF_10G_MACS > 0) */
++
++    if ((portType == e_FM_MAC_1G) && (p_Memac->macId >= FM_MAX_NUM_OF_1G_MACS))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("1G MAC ID must be less than %d", FM_MAX_NUM_OF_1G_MACS));
++    if (p_Memac->addr == 0)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet MAC must have a valid MAC address"));
++    if (!p_Memac->f_Exception)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Uninitialized f_Exception"));
++    if (!p_Memac->f_Event)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Uninitialized f_Event"));
++#ifdef FM_LEN_CHECK_ERRATA_FMAN_SW002
++    if (!p_Memac->p_MemacDriverParam->no_length_check_enable)
++       RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("LengthCheck!"));
++#endif /* FM_LEN_CHECK_ERRATA_FMAN_SW002 */
++
++    return E_OK;
++}
++
++/* ........................................................................... */
++
++static void MemacErrException(t_Handle h_Memac)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++    uint32_t    event, imask;
++
++    event = fman_memac_get_event(p_Memac->p_MemMap, 0xffffffff);
++    imask = fman_memac_get_interrupt_mask(p_Memac->p_MemMap);
++
++    /* Imask include both error and notification/event bits.
++       Leaving only error bits enabled by imask.
++       The imask error bits are shifted by 16 bits offset from
++       their corresponding location in the ievent - hence the >> 16 */
++    event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
++
++    fman_memac_ack_event(p_Memac->p_MemMap, event);
++
++    if (event & MEMAC_IEVNT_TS_ECC_ER)
++        p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_TS_FIFO_ECC_ERR);
++    if (event & MEMAC_IEVNT_TX_ECC_ER)
++        p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_10G_1TX_ECC_ER);
++    if (event & MEMAC_IEVNT_RX_ECC_ER)
++        p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_10G_RX_ECC_ER);
++}
++
++static void MemacException(t_Handle h_Memac)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++    uint32_t    event, imask;
++
++    event = fman_memac_get_event(p_Memac->p_MemMap, 0xffffffff);
++    imask = fman_memac_get_interrupt_mask(p_Memac->p_MemMap);
++
++    /* Imask include both error and notification/event bits.
++       Leaving only error bits enabled by imask.
++       The imask error bits are shifted by 16 bits offset from
++       their corresponding location in the ievent - hence the >> 16 */
++    event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
++
++    fman_memac_ack_event(p_Memac->p_MemMap, event);
++
++    if (event & MEMAC_IEVNT_MGI)
++        p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_MAGIC_PACKET_INDICATION);
++}
++
++/* ......................................................................... */
++
++static void FreeInitResources(t_Memac *p_Memac)
++{
++    e_FmMacType portType;
++
++    portType =
++        ((ENET_SPEED_FROM_MODE(p_Memac->enetMode) < e_ENET_SPEED_10000) ? e_FM_MAC_1G : e_FM_MAC_10G);
++
++    if (portType == e_FM_MAC_10G)
++        FmUnregisterIntr(p_Memac->fmMacControllerDriver.h_Fm, e_FM_MOD_10G_MAC, p_Memac->macId, e_FM_INTR_TYPE_ERR);
++    else
++        FmUnregisterIntr(p_Memac->fmMacControllerDriver.h_Fm, e_FM_MOD_1G_MAC, p_Memac->macId, e_FM_INTR_TYPE_ERR);
++
++    /* release the driver's group hash table */
++    FreeHashTable(p_Memac->p_MulticastAddrHash);
++    p_Memac->p_MulticastAddrHash =   NULL;
++
++    /* release the driver's individual hash table */
++    FreeHashTable(p_Memac->p_UnicastAddrHash);
++    p_Memac->p_UnicastAddrHash =     NULL;
++}
++
++
++/*****************************************************************************/
++/*                     mEMAC API routines                                    */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++static t_Error MemacEnable(t_Handle h_Memac,  e_CommMode mode)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    fman_memac_enable(p_Memac->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacDisable (t_Handle h_Memac, e_CommMode mode)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    fman_memac_disable(p_Memac->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacSetPromiscuous(t_Handle h_Memac, bool newVal)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    fman_memac_set_promiscuous(p_Memac->p_MemMap, newVal);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error MemacAdjustLink(t_Handle h_Memac, e_EnetSpeed speed, bool fullDuplex)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    if ((speed >= e_ENET_SPEED_1000) && (!fullDuplex))
++        RETURN_ERROR(MAJOR, E_CONFLICT,
++                     ("Ethernet MAC 1G or 10G does not support half-duplex"));
++
++    fman_memac_adjust_link(p_Memac->p_MemMap,
++                           (enum enet_interface)ENET_INTERFACE_FROM_MODE(p_Memac->enetMode),
++                           (enum enet_speed)speed,
++                           fullDuplex);
++    return E_OK;
++}
++
++
++/*****************************************************************************/
++/*                      Memac Configs modification functions                 */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++static t_Error MemacConfigLoopback(t_Handle h_Memac, bool newVal)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    p_Memac->p_MemacDriverParam->loopback_enable = newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacConfigWan(t_Handle h_Memac, bool newVal)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    p_Memac->p_MemacDriverParam->wan_mode_enable = newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacConfigMaxFrameLength(t_Handle h_Memac, uint16_t newVal)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    p_Memac->p_MemacDriverParam->max_frame_length = newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacConfigPad(t_Handle h_Memac, bool newVal)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    p_Memac->p_MemacDriverParam->pad_enable = newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacConfigLengthCheck(t_Handle h_Memac, bool newVal)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    p_Memac->p_MemacDriverParam->no_length_check_enable = !newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacConfigException(t_Handle h_Memac, e_FmMacExceptions exception, bool enable)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++    uint32_t    bitMask = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    GET_EXCEPTION_FLAG(bitMask, exception);
++    if (bitMask)
++    {
++        if (enable)
++            p_Memac->exceptions |= bitMask;
++        else
++            p_Memac->exceptions &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacConfigResetOnInit(t_Handle h_Memac, bool enable)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    p_Memac->p_MemacDriverParam->reset_on_init = enable;
++
++    return E_OK;
++}
++
++
++/*****************************************************************************/
++/*                      Memac Run Time API functions                         */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++static t_Error MemacSetTxPauseFrames(t_Handle h_Memac,
++                                     uint8_t  priority,
++                                     uint16_t pauseTime,
++                                     uint16_t threshTime)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    if (priority != 0xFF)
++    {
++        bool   PortConfigured, PreFetchEnabled;
++
++        if (FmGetTnumAgingPeriod(p_Memac->fmMacControllerDriver.h_Fm) == 0)
++            RETURN_ERROR(MAJOR, E_CONFLICT, ("For PFC operation, TNUM aging must be enabled"));
++
++        FmGetPortPreFetchConfiguration(p_Memac->fmMacControllerDriver.h_Fm,
++                                       p_Memac->fmMacControllerDriver.macId,
++                                       &PortConfigured,
++                                       &PreFetchEnabled);
++
++        if ((ENET_SPEED_FROM_MODE(p_Memac->fmMacControllerDriver.enetMode) == e_ENET_SPEED_1000) && !PortConfigured)
++            DBG(INFO, ("For PFC correct operation, prefetch must be configured on the FM Tx PORT"));
++
++        if ((ENET_SPEED_FROM_MODE(p_Memac->fmMacControllerDriver.enetMode) == e_ENET_SPEED_1000) && PortConfigured && !PreFetchEnabled)
++            DBG(WARNING, ("For PFC correct operation, prefetch must be configured on the FM Tx PORT"));
++    }
++
++    fman_memac_set_tx_pause_frames(p_Memac->p_MemMap, priority, pauseTime, threshTime);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacSetTxAutoPauseFrames(t_Handle h_Memac,
++                                         uint16_t pauseTime)
++{
++    return MemacSetTxPauseFrames(h_Memac, FM_MAC_NO_PFC, pauseTime, 0);
++}
++
++/* ......................................................................... */
++
++static t_Error MemacSetRxIgnorePauseFrames(t_Handle h_Memac, bool en)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    fman_memac_set_rx_ignore_pause_frames(p_Memac->p_MemMap, en);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacSetWakeOnLan(t_Handle h_Memac, bool en)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    fman_memac_set_wol(p_Memac->p_MemMap, en);
++
++    return E_OK;
++}
++
++/* .............................................................................. */
++
++static t_Error MemacEnable1588TimeStamp(t_Handle h_Memac)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++UNUSED(p_Memac);
++DBG(WARNING, ("mEMAC has 1588 always enabled!"));
++
++    return E_OK;
++}
++
++/* Counters handling */
++/* ......................................................................... */
++
++static t_Error MemacGetStatistics(t_Handle h_Memac, t_FmMacStatistics *p_Statistics)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_Statistics, E_NULL_POINTER);
++
++    p_Statistics->eStatPkts64           = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R64);
++    p_Statistics->eStatPkts65to127      = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R127);
++    p_Statistics->eStatPkts128to255     = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R255);
++    p_Statistics->eStatPkts256to511     = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R511);
++    p_Statistics->eStatPkts512to1023    = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R1023);
++    p_Statistics->eStatPkts1024to1518   = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R1518);
++    p_Statistics->eStatPkts1519to1522   = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R1519X);
++/* */
++    p_Statistics->eStatFragments        = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RFRG);
++    p_Statistics->eStatJabbers          = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RJBR);
++
++    p_Statistics->eStatsDropEvents      = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RDRP);
++    p_Statistics->eStatCRCAlignErrors   = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RALN);
++
++    p_Statistics->eStatUndersizePkts    = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TUND);
++    p_Statistics->eStatOversizePkts     = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_ROVR);
++/* Pause */
++    p_Statistics->reStatPause           = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RXPF);
++    p_Statistics->teStatPause           = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TXPF);
++
++/* MIB II */
++    p_Statistics->ifInOctets            = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_ROCT);
++    p_Statistics->ifInUcastPkts         = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RUCA);
++    p_Statistics->ifInMcastPkts         = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RMCA);
++    p_Statistics->ifInBcastPkts         = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RBCA);
++    p_Statistics->ifInPkts              = p_Statistics->ifInUcastPkts
++                                        + p_Statistics->ifInMcastPkts
++                                        + p_Statistics->ifInBcastPkts;
++    p_Statistics->ifInDiscards          = 0;
++    p_Statistics->ifInErrors            = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RERR);
++
++    p_Statistics->ifOutOctets           = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TOCT);
++    p_Statistics->ifOutUcastPkts        = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TUCA);
++    p_Statistics->ifOutMcastPkts        = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TMCA);
++    p_Statistics->ifOutBcastPkts        = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TBCA);
++    p_Statistics->ifOutPkts             = p_Statistics->ifOutUcastPkts
++                                        + p_Statistics->ifOutMcastPkts
++                                        + p_Statistics->ifOutBcastPkts;
++    p_Statistics->ifOutDiscards         = 0;
++    p_Statistics->ifOutErrors           = fman_memac_get_counter(p_Memac->p_MemMap,  E_MEMAC_COUNTER_TERR);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacModifyMacAddress (t_Handle h_Memac, t_EnetAddr *p_EnetAddr)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    fman_memac_add_addr_in_paddr(p_Memac->p_MemMap, (uint8_t *)(*p_EnetAddr), 0);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacResetCounters (t_Handle h_Memac)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    fman_memac_reset_stat(p_Memac->p_MemMap);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacAddExactMatchMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr)
++{
++    t_Memac     *p_Memac = (t_Memac *) h_Memac;
++    uint64_t    ethAddr;
++    uint8_t     paddrNum;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    if (ethAddr & GROUP_ADDRESS)
++        /* Multicast address has no effect in PADDR */
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Multicast address"));
++
++    /* Make sure no PADDR contains this address */
++    for (paddrNum = 0; paddrNum < MEMAC_NUM_OF_PADDRS; paddrNum++)
++        if (p_Memac->indAddrRegUsed[paddrNum])
++            if (p_Memac->paddr[paddrNum] == ethAddr)
++                RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG);
++
++    /* Find first unused PADDR */
++    for (paddrNum = 0; paddrNum < MEMAC_NUM_OF_PADDRS; paddrNum++)
++        if (!(p_Memac->indAddrRegUsed[paddrNum]))
++        {
++            /* mark this PADDR as used */
++            p_Memac->indAddrRegUsed[paddrNum] = TRUE;
++            /* store address */
++            p_Memac->paddr[paddrNum] = ethAddr;
++
++            /* put in hardware */
++            fman_memac_add_addr_in_paddr(p_Memac->p_MemMap, (uint8_t*)(*p_EthAddr), paddrNum);
++            p_Memac->numOfIndAddrInRegs++;
++
++            return E_OK;
++        }
++
++    /* No free PADDR */
++    RETURN_ERROR(MAJOR, E_FULL, NO_MSG);
++}
++
++/* ......................................................................... */
++
++static t_Error MemacDelExactMatchMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr)
++{
++    t_Memac     *p_Memac = (t_Memac *) h_Memac;
++    uint64_t    ethAddr;
++    uint8_t     paddrNum;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    /* Find used PADDR containing this address */
++    for (paddrNum = 0; paddrNum < MEMAC_NUM_OF_PADDRS; paddrNum++)
++    {
++        if ((p_Memac->indAddrRegUsed[paddrNum]) &&
++            (p_Memac->paddr[paddrNum] == ethAddr))
++        {
++            /* mark this PADDR as not used */
++            p_Memac->indAddrRegUsed[paddrNum] = FALSE;
++            /* clear in hardware */
++            fman_memac_clear_addr_in_paddr(p_Memac->p_MemMap, paddrNum);
++            p_Memac->numOfIndAddrInRegs--;
++
++            return E_OK;
++        }
++    }
++
++    RETURN_ERROR(MAJOR, E_NOT_FOUND, NO_MSG);
++}
++
++/* ......................................................................... */
++
++static t_Error MemacGetId(t_Handle h_Memac, uint32_t *macId)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    *macId = p_Memac->macId;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++
++static t_Error MemacAddHashMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr)
++{
++    t_Memac             *p_Memac = (t_Memac *)h_Memac;
++    t_EthHashEntry      *p_HashEntry;
++    uint32_t            hash;
++    uint64_t            ethAddr;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    if (!(ethAddr & GROUP_ADDRESS))
++        /* Unicast addresses not supported in hash */
++        RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unicast Address"));
++
++    hash = GetMacAddrHashCode(ethAddr) & HASH_CTRL_ADDR_MASK;
++
++    /* Create element to be added to the driver hash table */
++    p_HashEntry = (t_EthHashEntry *)XX_Malloc(sizeof(t_EthHashEntry));
++    p_HashEntry->addr = ethAddr;
++    INIT_LIST(&p_HashEntry->node);
++
++    LIST_AddToTail(&(p_HashEntry->node), &(p_Memac->p_MulticastAddrHash->p_Lsts[hash]));
++    fman_memac_set_hash_table(p_Memac->p_MemMap, (hash | HASH_CTRL_MCAST_EN));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacDelHashMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr)
++{
++    t_Memac             *p_Memac = (t_Memac *)h_Memac;
++    t_EthHashEntry      *p_HashEntry = NULL;
++    t_List              *p_Pos;
++    uint32_t            hash;
++    uint64_t            ethAddr;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    hash = GetMacAddrHashCode(ethAddr) & HASH_CTRL_ADDR_MASK;
++
++    LIST_FOR_EACH(p_Pos, &(p_Memac->p_MulticastAddrHash->p_Lsts[hash]))
++    {
++        p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos);
++        if (p_HashEntry->addr == ethAddr)
++        {
++            LIST_DelAndInit(&p_HashEntry->node);
++            XX_Free(p_HashEntry);
++            break;
++        }
++    }
++    if (LIST_IsEmpty(&p_Memac->p_MulticastAddrHash->p_Lsts[hash]))
++        fman_memac_set_hash_table(p_Memac->p_MemMap, (hash & ~HASH_CTRL_MCAST_EN));
++
++    return E_OK;
++}
++
++
++/* ......................................................................... */
++
++static t_Error MemacSetException(t_Handle h_Memac, e_FmMacExceptions exception, bool enable)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++    uint32_t    bitMask = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++
++    GET_EXCEPTION_FLAG(bitMask, exception);
++    if (bitMask)
++    {
++        if (enable)
++            p_Memac->exceptions |= bitMask;
++        else
++            p_Memac->exceptions &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    fman_memac_set_exception(p_Memac->p_MemMap, bitMask, enable);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static uint16_t MemacGetMaxFrameLength(t_Handle h_Memac)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_VALUE(p_Memac, E_INVALID_HANDLE, 0);
++    SANITY_CHECK_RETURN_VALUE(!p_Memac->p_MemacDriverParam, E_INVALID_STATE, 0);
++
++    return fman_memac_get_max_frame_len(p_Memac->p_MemMap);
++}
++
++
++/*****************************************************************************/
++/*                      mEMAC Init & Free API                                   */
++/*****************************************************************************/
++
++/* ......................................................................... */
++void *g_MemacRegs;
++static t_Error MemacInit(t_Handle h_Memac)
++{
++    t_Memac                 *p_Memac = (t_Memac *)h_Memac;
++    struct memac_cfg        *p_MemacDriverParam;
++    enum enet_interface     enet_interface;
++    enum enet_speed         enet_speed;
++    uint8_t                 i, phyAddr;
++    t_EnetAddr              ethAddr;
++    e_FmMacType             portType;
++    t_Error                 err;
++    bool                    slow_10g_if = FALSE;
++    if (p_Memac->macId == 3) /* This is a quick WA */
++		g_MemacRegs = p_Memac->p_MemMap;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->fmMacControllerDriver.h_Fm, E_INVALID_HANDLE);
++
++    FM_GetRevision(p_Memac->fmMacControllerDriver.h_Fm, &p_Memac->fmMacControllerDriver.fmRevInfo);
++    if (p_Memac->fmMacControllerDriver.fmRevInfo.majorRev == 6 &&
++        p_Memac->fmMacControllerDriver.fmRevInfo.minorRev == 4)
++        slow_10g_if = TRUE;
++
++    CHECK_INIT_PARAMETERS(p_Memac, CheckInitParameters);
++
++    p_MemacDriverParam = p_Memac->p_MemacDriverParam;
++
++    portType =
++        ((ENET_SPEED_FROM_MODE(p_Memac->enetMode) < e_ENET_SPEED_10000) ? e_FM_MAC_1G : e_FM_MAC_10G);
++
++    /* First, reset the MAC if desired. */
++    if (p_MemacDriverParam->reset_on_init)
++        fman_memac_reset(p_Memac->p_MemMap);
++
++    /* MAC Address */
++    MAKE_ENET_ADDR_FROM_UINT64(p_Memac->addr, ethAddr);
++    fman_memac_add_addr_in_paddr(p_Memac->p_MemMap, (uint8_t*)ethAddr, 0);
++
++    enet_interface = (enum enet_interface) ENET_INTERFACE_FROM_MODE(p_Memac->enetMode);
++    enet_speed = (enum enet_speed) ENET_SPEED_FROM_MODE(p_Memac->enetMode);
++
++    fman_memac_init(p_Memac->p_MemMap,
++               p_Memac->p_MemacDriverParam,
++               enet_interface,
++               enet_speed,
++               slow_10g_if,
++               p_Memac->exceptions);
++
++#ifdef FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320
++    {
++    	uint32_t tmpReg = 0;
++
++    	FM_GetRevision(p_Memac->fmMacControllerDriver.h_Fm, &p_Memac->fmMacControllerDriver.fmRevInfo);
++        /* check the FMAN version - the bug exists only in rev1 */
++        if ((p_Memac->fmMacControllerDriver.fmRevInfo.majorRev == 6) &&
++        	(p_Memac->fmMacControllerDriver.fmRevInfo.minorRev == 0))
++        {
++        	/* MAC strips CRC from received frames - this workaround should
++        	   decrease the likelihood of bug appearance
++            */
++			tmpReg = GET_UINT32(p_Memac->p_MemMap->command_config);
++			tmpReg &= ~CMD_CFG_CRC_FWD;
++			WRITE_UINT32(p_Memac->p_MemMap->command_config, tmpReg);
++			/* DBG(WARNING, ("mEMAC strips CRC from received frames as part of A006320 errata workaround"));*/
++        }
++    }
++#endif /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 */
++
++    if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_SGMII)
++    {
++        /* Configure internal SGMII PHY */
++        if (p_Memac->enetMode & ENET_IF_SGMII_BASEX)
++            SetupSgmiiInternalPhyBaseX(p_Memac, PHY_MDIO_ADDR);
++        else
++            SetupSgmiiInternalPhy(p_Memac, PHY_MDIO_ADDR);
++    }
++    else if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_QSGMII)
++    {
++        /* Configure 4 internal SGMII PHYs */
++        for (i = 0; i < 4; i++)
++        {
++            /* QSGMII PHY address occupies 3 upper bits of 5-bit
++               phyAddress; the lower 2 bits are used to extend
++               register address space and access each one of 4
++               ports inside QSGMII. */
++            phyAddr = (uint8_t)((PHY_MDIO_ADDR << 2) | i);
++            if (p_Memac->enetMode & ENET_IF_SGMII_BASEX)
++                SetupSgmiiInternalPhyBaseX(p_Memac, phyAddr);
++            else
++                SetupSgmiiInternalPhy(p_Memac, phyAddr);
++        }
++    }
++
++    /* Max Frame Length */
++    err = FmSetMacMaxFrame(p_Memac->fmMacControllerDriver.h_Fm,
++                           portType,
++                           p_Memac->fmMacControllerDriver.macId,
++                           p_MemacDriverParam->max_frame_length);
++    if (err)
++        RETURN_ERROR(MAJOR, err, ("settings Mac max frame length is FAILED"));
++
++    p_Memac->p_MulticastAddrHash = AllocHashTable(HASH_TABLE_SIZE);
++    if (!p_Memac->p_MulticastAddrHash)
++    {
++        FreeInitResources(p_Memac);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED"));
++    }
++
++    p_Memac->p_UnicastAddrHash = AllocHashTable(HASH_TABLE_SIZE);
++    if (!p_Memac->p_UnicastAddrHash)
++    {
++        FreeInitResources(p_Memac);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED"));
++    }
++
++    FmRegisterIntr(p_Memac->fmMacControllerDriver.h_Fm,
++                   (portType == e_FM_MAC_10G) ? e_FM_MOD_10G_MAC : e_FM_MOD_1G_MAC,
++                   p_Memac->macId,
++                   e_FM_INTR_TYPE_ERR,
++                   MemacErrException,
++                   p_Memac);
++
++    FmRegisterIntr(p_Memac->fmMacControllerDriver.h_Fm,
++                   (portType == e_FM_MAC_10G) ? e_FM_MOD_10G_MAC : e_FM_MOD_1G_MAC,
++                   p_Memac->macId,
++                   e_FM_INTR_TYPE_NORMAL,
++                   MemacException,
++                   p_Memac);
++
++    XX_Free(p_MemacDriverParam);
++    p_Memac->p_MemacDriverParam = NULL;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error MemacFree(t_Handle h_Memac)
++{
++    t_Memac     *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++
++    if (p_Memac->p_MemacDriverParam)
++    {
++        /* Called after config */
++        XX_Free(p_Memac->p_MemacDriverParam);
++        p_Memac->p_MemacDriverParam = NULL;
++    }
++    else
++        /* Called after init */
++        FreeInitResources(p_Memac);
++
++    XX_Free(p_Memac);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static void InitFmMacControllerDriver(t_FmMacControllerDriver *p_FmMacControllerDriver)
++{
++    p_FmMacControllerDriver->f_FM_MAC_Init                      = MemacInit;
++    p_FmMacControllerDriver->f_FM_MAC_Free                      = MemacFree;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetStatistics             = NULL;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback            = MemacConfigLoopback;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength      = MemacConfigMaxFrameLength;
++
++    p_FmMacControllerDriver->f_FM_MAC_ConfigWan                 = MemacConfigWan;
++
++    p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc           = MemacConfigPad;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex          = NULL; /* half-duplex is detected automatically */
++    p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck         = MemacConfigLengthCheck;
++
++    p_FmMacControllerDriver->f_FM_MAC_ConfigException           = MemacConfigException;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit         = MemacConfigResetOnInit;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetException              = MemacSetException;
++
++    p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp       = MemacEnable1588TimeStamp; /* always enabled */
++    p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp      = NULL;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous            = MemacSetPromiscuous;
++    p_FmMacControllerDriver->f_FM_MAC_AdjustLink                = MemacAdjustLink;
++    p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg            = NULL;
++
++    p_FmMacControllerDriver->f_FM_MAC_Enable                    = MemacEnable;
++    p_FmMacControllerDriver->f_FM_MAC_Disable                   = MemacDisable;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames      = MemacSetTxAutoPauseFrames;
++    p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames          = MemacSetTxPauseFrames;
++    p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames    = MemacSetRxIgnorePauseFrames;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan              = MemacSetWakeOnLan;
++
++    p_FmMacControllerDriver->f_FM_MAC_ResetCounters             = MemacResetCounters;
++    p_FmMacControllerDriver->f_FM_MAC_GetStatistics             = MemacGetStatistics;
++
++    p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr             = MemacModifyMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr            = MemacAddHashMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr         = MemacDelHashMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr      = MemacAddExactMatchMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr  = MemacDelExactMatchMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_GetId                     = MemacGetId;
++    p_FmMacControllerDriver->f_FM_MAC_GetVersion                = NULL;
++    p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength         = MemacGetMaxFrameLength;
++
++    p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg           = MEMAC_MII_WritePhyReg;
++    p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg            = MEMAC_MII_ReadPhyReg;
++}
++
++
++/*****************************************************************************/
++/*                      mEMAC Config Main Entry                             */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++t_Handle MEMAC_Config(t_FmMacParams *p_FmMacParam)
++{
++    t_Memac             *p_Memac;
++    struct memac_cfg    *p_MemacDriverParam;
++    uintptr_t           baseAddr;
++
++    SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_NULL_POINTER, NULL);
++
++    baseAddr = p_FmMacParam->baseAddr;
++    /* Allocate memory for the mEMAC data structure */
++    p_Memac = (t_Memac *)XX_Malloc(sizeof(t_Memac));
++    if (!p_Memac)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("mEMAC driver structure"));
++        return NULL;
++    }
++    memset(p_Memac, 0, sizeof(t_Memac));
++    InitFmMacControllerDriver(&p_Memac->fmMacControllerDriver);
++
++    /* Allocate memory for the mEMAC driver parameters data structure */
++    p_MemacDriverParam = (struct memac_cfg *)XX_Malloc(sizeof(struct memac_cfg));
++    if (!p_MemacDriverParam)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("mEMAC driver parameters"));
++        XX_Free(p_Memac);
++        return NULL;
++    }
++    memset(p_MemacDriverParam, 0, sizeof(struct memac_cfg));
++
++    /* Plant parameter structure pointer */
++    p_Memac->p_MemacDriverParam = p_MemacDriverParam;
++
++    fman_memac_defconfig(p_MemacDriverParam);
++
++    p_Memac->addr           = ENET_ADDR_TO_UINT64(p_FmMacParam->addr);
++
++    p_Memac->p_MemMap       = (struct memac_regs *)UINT_TO_PTR(baseAddr);
++    p_Memac->p_MiiMemMap    = (struct memac_mii_access_mem_map*)UINT_TO_PTR(baseAddr + MEMAC_TO_MII_OFFSET);
++
++    p_Memac->enetMode       = p_FmMacParam->enetMode;
++    p_Memac->macId          = p_FmMacParam->macId;
++    p_Memac->exceptions     = MEMAC_default_exceptions;
++    p_Memac->f_Exception    = p_FmMacParam->f_Exception;
++    p_Memac->f_Event        = p_FmMacParam->f_Event;
++    p_Memac->h_App          = p_FmMacParam->h_App;
++
++    return p_Memac;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.h
+new file mode 100644
+index 0000000..2fd89da
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.h
+@@ -0,0 +1,110 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          memac.h
++
++ @Description   FM Multirate Ethernet MAC (mEMAC)
++*//***************************************************************************/
++#ifndef __MEMAC_H
++#define __MEMAC_H
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "list_ext.h"
++
++#include "fsl_fman_memac_mii_acc.h"
++#include "fm_mac.h"
++#include "fsl_fman_memac.h"
++
++
++#define MEMAC_default_exceptions    \
++        ((uint32_t)(MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI))
++
++#define GET_EXCEPTION_FLAG(bitMask, exception)       switch (exception){    \
++    case e_FM_MAC_EX_10G_1TX_ECC_ER:                                        \
++        bitMask = MEMAC_IMASK_TECC_ER; break;                               \
++    case e_FM_MAC_EX_10G_RX_ECC_ER:                                         \
++        bitMask = MEMAC_IMASK_RECC_ER; break;                               \
++    case e_FM_MAC_EX_TS_FIFO_ECC_ERR:                                       \
++        bitMask = MEMAC_IMASK_TSECC_ER; break;                              \
++    case e_FM_MAC_EX_MAGIC_PACKET_INDICATION:                               \
++        bitMask = MEMAC_IMASK_MGI; break;                                   \
++    default: bitMask = 0;break;}
++
++
++typedef struct
++{
++    t_FmMacControllerDriver     fmMacControllerDriver;               /**< Upper Mac control block */
++    t_Handle                    h_App;                               /**< Handle to the upper layer application  */
++    struct memac_regs           *p_MemMap;                           /**< Pointer to MAC memory mapped registers */
++    struct memac_mii_access_mem_map *p_MiiMemMap;                        /**< Pointer to MII memory mapped registers */
++    uint64_t                    addr;                                /**< MAC address of device */
++    e_EnetMode                  enetMode;                            /**< Ethernet physical interface  */
++    t_FmMacExceptionCallback    *f_Exception;
++    int                         mdioIrq;
++    t_FmMacExceptionCallback    *f_Event;
++    bool                        indAddrRegUsed[MEMAC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
++    uint64_t                    paddr[MEMAC_NUM_OF_PADDRS];          /**< MAC address for particular individual address recognition register */
++    uint8_t                     numOfIndAddrInRegs;                  /**< Number of individual addresses in registers for this station. */
++    t_EthHash                   *p_MulticastAddrHash;                /**< Pointer to driver's global address hash table  */
++    t_EthHash                   *p_UnicastAddrHash;                  /**< Pointer to driver's individual address hash table  */
++    bool                        debugMode;
++    uint8_t                     macId;
++    uint32_t                    exceptions;
++    struct memac_cfg            *p_MemacDriverParam;
++} t_Memac;
++
++
++/* Internal PHY access */
++#define PHY_MDIO_ADDR               0
++
++/* Internal PHY Registers - SGMII */
++#define PHY_SGMII_CR_PHY_RESET          0x8000
++#define PHY_SGMII_CR_RESET_AN           0x0200
++#define PHY_SGMII_CR_DEF_VAL            0x1140
++#define PHY_SGMII_DEV_ABILITY_SGMII     0x4001
++#define PHY_SGMII_DEV_ABILITY_1000X     0x01A0
++#define PHY_SGMII_IF_SPEED_GIGABIT	0x0008
++#define PHY_SGMII_IF_MODE_AN            0x0002
++#define PHY_SGMII_IF_MODE_SGMII         0x0001
++#define PHY_SGMII_IF_MODE_1000X         0x0000
++
++
++#define MEMAC_TO_MII_OFFSET         0x030       /* Offset from the MEM map to the MDIO mem map */
++
++t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t data);
++t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac,  uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
++
++
++#endif /* __MEMAC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c
+new file mode 100644
+index 0000000..56eaffb
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c
+@@ -0,0 +1,78 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#include "error_ext.h"
++#include "std_ext.h"
++#include "fm_mac.h"
++#include "memac.h"
++#include "xx_ext.h"
++
++#include "fm_common.h"
++#include "memac_mii_acc.h"
++
++
++/*****************************************************************************/
++t_Error MEMAC_MII_WritePhyReg(t_Handle  h_Memac,
++                             uint8_t    phyAddr,
++                             uint8_t    reg,
++                             uint16_t   data)
++{
++    t_Memac                 *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
++
++    return (t_Error)fman_memac_mii_write_phy_reg(p_Memac->p_MiiMemMap,
++                                                 phyAddr,
++                                                 reg,
++                                                 data,
++                                                 (enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
++}
++
++/*****************************************************************************/
++t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac,
++                            uint8_t   phyAddr,
++                            uint8_t   reg,
++                            uint16_t  *p_Data)
++{
++    t_Memac                 *p_Memac = (t_Memac *)h_Memac;
++
++    SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
++
++    return fman_memac_mii_read_phy_reg(p_Memac->p_MiiMemMap,
++                                       phyAddr,
++                                       reg,
++                                       p_Data,
++                                       (enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h
+new file mode 100644
+index 0000000..325ec08
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h
+@@ -0,0 +1,73 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#ifndef __MEMAC_MII_ACC_H
++#define __MEMAC_MII_ACC_H
++
++#include "std_ext.h"
++
++
++/* MII Management Registers */
++#define MDIO_CFG_CLK_DIV_MASK       0x0080ff80
++#define MDIO_CFG_CLK_DIV_SHIFT      7
++#define MDIO_CFG_HOLD_MASK          0x0000001c
++#define MDIO_CFG_ENC45              0x00000040
++#define MDIO_CFG_READ_ERR           0x00000002
++#define MDIO_CFG_BSY                0x00000001
++
++#define MDIO_CTL_PHY_ADDR_SHIFT     5
++#define MDIO_CTL_READ               0x00008000
++
++#define MDIO_DATA_BSY               0x80000000
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(push,1)
++#endif /* defined(__MWERKS__) && ... */
++
++/*----------------------------------------------------*/
++/* MII Configuration Control Memory Map Registers     */
++/*----------------------------------------------------*/
++typedef struct t_MemacMiiAccessMemMap
++{
++    volatile uint32_t   mdio_cfg;       /* 0x030  */
++    volatile uint32_t   mdio_ctrl;      /* 0x034  */
++    volatile uint32_t   mdio_data;      /* 0x038  */
++    volatile uint32_t   mdio_addr;      /* 0x03c  */
++} t_MemacMiiAccessMemMap ;
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(pop)
++#endif /* defined(__MWERKS__) && ... */
++
++
++#endif /* __MEMAC_MII_ACC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c
+new file mode 100644
+index 0000000..bf12c5d
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c
+@@ -0,0 +1,974 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          tgec.c
++
++ @Description   FM 10G MAC ...
++*//***************************************************************************/
++
++#include "std_ext.h"
++#include "string_ext.h"
++#include "error_ext.h"
++#include "xx_ext.h"
++#include "endian_ext.h"
++#include "debug_ext.h"
++#include "crc_mac_addr_ext.h"
++
++#include "fm_common.h"
++#include "fsl_fman_tgec.h"
++#include "tgec.h"
++
++
++/*****************************************************************************/
++/*                      Internal routines                                    */
++/*****************************************************************************/
++
++static t_Error CheckInitParameters(t_Tgec    *p_Tgec)
++{
++    if (ENET_SPEED_FROM_MODE(p_Tgec->enetMode) < e_ENET_SPEED_10000)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 10G MAC driver only support 10G speed"));
++#if (FM_MAX_NUM_OF_10G_MACS > 0)
++    if (p_Tgec->macId >= FM_MAX_NUM_OF_10G_MACS)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("macId of 10G can not be greater than 0"));
++#endif /* (FM_MAX_NUM_OF_10G_MACS > 0) */
++
++    if (p_Tgec->addr == 0)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 10G MAC Must have a valid MAC Address"));
++    if (!p_Tgec->f_Exception)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("uninitialized f_Exception"));
++    if (!p_Tgec->f_Event)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("uninitialized f_Event"));
++#ifdef FM_LEN_CHECK_ERRATA_FMAN_SW002
++    if (!p_Tgec->p_TgecDriverParam->no_length_check_enable)
++       RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("LengthCheck!"));
++#endif /* FM_LEN_CHECK_ERRATA_FMAN_SW002 */
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static uint32_t GetMacAddrHashCode(uint64_t ethAddr)
++{
++    uint32_t crc;
++
++    /* CRC calculation */
++    GET_MAC_ADDR_CRC(ethAddr, crc);
++
++    crc = GetMirror32(crc);
++
++    return crc;
++}
++
++/* ......................................................................... */
++
++static void TgecErrException(t_Handle h_Tgec)
++{
++    t_Tgec              *p_Tgec = (t_Tgec *)h_Tgec;
++    uint32_t            event;
++    struct tgec_regs    *p_TgecMemMap = p_Tgec->p_MemMap;
++
++    /* do not handle MDIO events */
++    event = fman_tgec_get_event(p_TgecMemMap, ~(TGEC_IMASK_MDIO_SCAN_EVENT | TGEC_IMASK_MDIO_CMD_CMPL));
++    event &= fman_tgec_get_interrupt_mask(p_TgecMemMap);
++
++    fman_tgec_ack_event(p_TgecMemMap, event);
++
++    if (event & TGEC_IMASK_REM_FAULT)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_REM_FAULT);
++    if (event & TGEC_IMASK_LOC_FAULT)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_LOC_FAULT);
++    if (event & TGEC_IMASK_TX_ECC_ER)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_1TX_ECC_ER);
++    if (event & TGEC_IMASK_TX_FIFO_UNFL)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_FIFO_UNFL);
++    if (event & TGEC_IMASK_TX_FIFO_OVFL)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_FIFO_OVFL);
++    if (event & TGEC_IMASK_TX_ER)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_ER);
++    if (event & TGEC_IMASK_RX_FIFO_OVFL)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_FIFO_OVFL);
++    if (event & TGEC_IMASK_RX_ECC_ER)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_ECC_ER);
++    if (event & TGEC_IMASK_RX_JAB_FRM)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_JAB_FRM);
++    if (event & TGEC_IMASK_RX_OVRSZ_FRM)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_OVRSZ_FRM);
++    if (event & TGEC_IMASK_RX_RUNT_FRM)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_RUNT_FRM);
++    if (event & TGEC_IMASK_RX_FRAG_FRM)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_FRAG_FRM);
++    if (event & TGEC_IMASK_RX_LEN_ER)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_LEN_ER);
++    if (event & TGEC_IMASK_RX_CRC_ER)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_CRC_ER);
++    if (event & TGEC_IMASK_RX_ALIGN_ER)
++        p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_ALIGN_ER);
++}
++
++/* ......................................................................... */
++
++static void TgecException(t_Handle h_Tgec)
++{
++     t_Tgec             *p_Tgec = (t_Tgec *)h_Tgec;
++     uint32_t           event;
++     struct tgec_regs   *p_TgecMemMap = p_Tgec->p_MemMap;
++
++     /* handle only MDIO events */
++     event = fman_tgec_get_event(p_TgecMemMap, (TGEC_IMASK_MDIO_SCAN_EVENT | TGEC_IMASK_MDIO_CMD_CMPL));
++     event &= fman_tgec_get_interrupt_mask(p_TgecMemMap);
++
++     fman_tgec_ack_event(p_TgecMemMap, event);
++
++     if (event & TGEC_IMASK_MDIO_SCAN_EVENT)
++         p_Tgec->f_Event(p_Tgec->h_App, e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO);
++     if (event & TGEC_IMASK_MDIO_CMD_CMPL)
++         p_Tgec->f_Event(p_Tgec->h_App, e_FM_MAC_EX_10G_MDIO_CMD_CMPL);
++}
++
++/* ......................................................................... */
++
++static void FreeInitResources(t_Tgec *p_Tgec)
++{
++    if (p_Tgec->mdioIrq != NO_IRQ)
++    {
++        XX_DisableIntr(p_Tgec->mdioIrq);
++        XX_FreeIntr(p_Tgec->mdioIrq);
++    }
++
++    FmUnregisterIntr(p_Tgec->fmMacControllerDriver.h_Fm, e_FM_MOD_10G_MAC, p_Tgec->macId, e_FM_INTR_TYPE_ERR);
++
++    /* release the driver's group hash table */
++    FreeHashTable(p_Tgec->p_MulticastAddrHash);
++    p_Tgec->p_MulticastAddrHash =   NULL;
++
++    /* release the driver's individual hash table */
++    FreeHashTable(p_Tgec->p_UnicastAddrHash);
++    p_Tgec->p_UnicastAddrHash =     NULL;
++}
++
++
++/*****************************************************************************/
++/*                     10G MAC API routines                                  */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++static t_Error TgecEnable(t_Handle h_Tgec,  e_CommMode mode)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    fman_tgec_enable(p_Tgec->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecDisable (t_Handle h_Tgec, e_CommMode mode)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    fman_tgec_disable(p_Tgec->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecSetPromiscuous(t_Handle h_Tgec, bool newVal)
++{
++    t_Tgec       *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    fman_tgec_set_promiscuous(p_Tgec->p_MemMap, newVal);
++
++    return E_OK;
++}
++
++
++/*****************************************************************************/
++/*                      Tgec Configs modification functions                 */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++static t_Error TgecConfigLoopback(t_Handle h_Tgec, bool newVal)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    p_Tgec->p_TgecDriverParam->loopback_enable = newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecConfigWan(t_Handle h_Tgec, bool newVal)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    p_Tgec->p_TgecDriverParam->wan_mode_enable = newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecConfigMaxFrameLength(t_Handle h_Tgec, uint16_t newVal)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    p_Tgec->p_TgecDriverParam->max_frame_length = newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecConfigLengthCheck(t_Handle h_Tgec, bool newVal)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    UNUSED(newVal);
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    p_Tgec->p_TgecDriverParam->no_length_check_enable = !newVal;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecConfigException(t_Handle h_Tgec, e_FmMacExceptions exception, bool enable)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++    uint32_t    bitMask = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    GET_EXCEPTION_FLAG(bitMask, exception);
++    if (bitMask)
++    {
++        if (enable)
++            p_Tgec->exceptions |= bitMask;
++        else
++            p_Tgec->exceptions &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    return E_OK;
++}
++
++#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
++/* ......................................................................... */
++
++static t_Error TgecConfigSkipFman11Workaround(t_Handle h_Tgec)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    p_Tgec->p_TgecDriverParam->skip_fman11_workaround = TRUE;
++
++    return E_OK;
++}
++#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
++
++
++/*****************************************************************************/
++/*                      Tgec Run Time API functions                         */
++/*****************************************************************************/
++
++/* ......................................................................... */
++/* backward compatibility. will be removed in the future. */
++static t_Error TgecTxMacPause(t_Handle h_Tgec, uint16_t pauseTime)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++    fman_tgec_set_tx_pause_frames(p_Tgec->p_MemMap, pauseTime);
++
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecSetTxPauseFrames(t_Handle h_Tgec,
++                                    uint8_t  priority,
++                                    uint16_t pauseTime,
++                                    uint16_t threshTime)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    UNUSED(priority); UNUSED(threshTime);
++
++    fman_tgec_set_tx_pause_frames(p_Tgec->p_MemMap, pauseTime);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecRxIgnoreMacPause(t_Handle h_Tgec, bool en)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    fman_tgec_set_rx_ignore_pause_frames(p_Tgec->p_MemMap, en);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecGetStatistics(t_Handle h_Tgec, t_FmMacStatistics *p_Statistics)
++{
++    t_Tgec              *p_Tgec = (t_Tgec *)h_Tgec;
++    struct tgec_regs    *p_TgecMemMap;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_Statistics, E_NULL_POINTER);
++
++    p_TgecMemMap = p_Tgec->p_MemMap;
++
++    p_Statistics->eStatPkts64           = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R64);
++    p_Statistics->eStatPkts65to127      = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R127);
++    p_Statistics->eStatPkts128to255     = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R255);
++    p_Statistics->eStatPkts256to511     = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R511);
++    p_Statistics->eStatPkts512to1023    = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1023);
++    p_Statistics->eStatPkts1024to1518   = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1518);
++    p_Statistics->eStatPkts1519to1522   = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1519X);
++/* */
++    p_Statistics->eStatFragments        = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRFRG);
++    p_Statistics->eStatJabbers          = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRJBR);
++
++    p_Statistics->eStatsDropEvents      = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RDRP);
++    p_Statistics->eStatCRCAlignErrors   = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RALN);
++
++    p_Statistics->eStatUndersizePkts    = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRUND);
++    p_Statistics->eStatOversizePkts     = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TROVR);
++/* Pause */
++    p_Statistics->reStatPause           = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RXPF);
++    p_Statistics->teStatPause           = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TXPF);
++
++/* MIB II */
++    p_Statistics->ifInOctets            = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_ROCT);
++    p_Statistics->ifInUcastPkts         = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RUCA);
++    p_Statistics->ifInMcastPkts         = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RMCA);
++    p_Statistics->ifInBcastPkts         = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RBCA);
++    p_Statistics->ifInPkts              = p_Statistics->ifInUcastPkts
++                                        + p_Statistics->ifInMcastPkts
++                                        + p_Statistics->ifInBcastPkts;
++    p_Statistics->ifInDiscards          = 0;
++    p_Statistics->ifInErrors            = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RERR);
++
++    p_Statistics->ifOutOctets           = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TOCT);
++    p_Statistics->ifOutUcastPkts        = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TUCA);
++    p_Statistics->ifOutMcastPkts        = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TMCA);
++    p_Statistics->ifOutBcastPkts        = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TBCA);
++    p_Statistics->ifOutPkts             = p_Statistics->ifOutUcastPkts
++                                        + p_Statistics->ifOutMcastPkts
++                                        + p_Statistics->ifOutBcastPkts;
++    p_Statistics->ifOutDiscards         = 0;
++    p_Statistics->ifOutErrors           = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TERR);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecEnable1588TimeStamp(t_Handle h_Tgec)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    fman_tgec_enable_1588_time_stamp(p_Tgec->p_MemMap, 1);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecDisable1588TimeStamp(t_Handle h_Tgec)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    fman_tgec_enable_1588_time_stamp(p_Tgec->p_MemMap, 0);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecModifyMacAddress (t_Handle h_Tgec, t_EnetAddr *p_EnetAddr)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    p_Tgec->addr = ENET_ADDR_TO_UINT64(*p_EnetAddr);
++    fman_tgec_set_mac_address(p_Tgec->p_MemMap, (uint8_t *)(*p_EnetAddr));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecResetCounters (t_Handle h_Tgec)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    fman_tgec_reset_stat(p_Tgec->p_MemMap);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecAddExactMatchMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *) h_Tgec;
++    uint64_t    ethAddr;
++    uint8_t     paddrNum;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    if (ethAddr & GROUP_ADDRESS)
++        /* Multicast address has no effect in PADDR */
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Multicast address"));
++
++    /* Make sure no PADDR contains this address */
++    for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++)
++        if (p_Tgec->indAddrRegUsed[paddrNum])
++            if (p_Tgec->paddr[paddrNum] == ethAddr)
++                RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG);
++
++    /* Find first unused PADDR */
++    for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++)
++    {
++        if (!(p_Tgec->indAddrRegUsed[paddrNum]))
++        {
++            /* mark this PADDR as used */
++            p_Tgec->indAddrRegUsed[paddrNum] = TRUE;
++            /* store address */
++            p_Tgec->paddr[paddrNum] = ethAddr;
++
++            /* put in hardware */
++            fman_tgec_add_addr_in_paddr(p_Tgec->p_MemMap, (uint8_t*)(*p_EthAddr)/* , paddrNum */);
++            p_Tgec->numOfIndAddrInRegs++;
++
++            return E_OK;
++        }
++    }
++
++    /* No free PADDR */
++    RETURN_ERROR(MAJOR, E_FULL, NO_MSG);
++}
++
++/* ......................................................................... */
++
++static t_Error TgecDelExactMatchMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *) h_Tgec;
++    uint64_t    ethAddr;
++    uint8_t     paddrNum;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    /* Find used PADDR containing this address */
++    for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++)
++    {
++        if ((p_Tgec->indAddrRegUsed[paddrNum]) &&
++            (p_Tgec->paddr[paddrNum] == ethAddr))
++        {
++            /* mark this PADDR as not used */
++            p_Tgec->indAddrRegUsed[paddrNum] = FALSE;
++            /* clear in hardware */
++            fman_tgec_clear_addr_in_paddr(p_Tgec->p_MemMap /*, paddrNum */);
++            p_Tgec->numOfIndAddrInRegs--;
++
++            return E_OK;
++        }
++    }
++
++    RETURN_ERROR(MAJOR, E_NOT_FOUND, NO_MSG);
++}
++
++/* ......................................................................... */
++
++static t_Error TgecAddHashMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
++{
++    t_Tgec          *p_Tgec = (t_Tgec *)h_Tgec;
++    t_EthHashEntry  *p_HashEntry;
++    uint32_t        crc;
++    uint32_t        hash;
++    uint64_t        ethAddr;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
++
++    if (!(ethAddr & GROUP_ADDRESS))
++        /* Unicast addresses not supported in hash */
++        RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unicast Address"));
++
++    /* CRC calculation */
++    crc = GetMacAddrHashCode(ethAddr);
++
++    hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;        /* Take 9 MSB bits */
++
++    /* Create element to be added to the driver hash table */
++    p_HashEntry = (t_EthHashEntry *)XX_Malloc(sizeof(t_EthHashEntry));
++    p_HashEntry->addr = ethAddr;
++    INIT_LIST(&p_HashEntry->node);
++
++    LIST_AddToTail(&(p_HashEntry->node), &(p_Tgec->p_MulticastAddrHash->p_Lsts[hash]));
++    fman_tgec_set_hash_table(p_Tgec->p_MemMap, (hash | TGEC_HASH_MCAST_EN));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecDelHashMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
++{
++    t_Tgec           *p_Tgec = (t_Tgec *)h_Tgec;
++    t_EthHashEntry   *p_HashEntry = NULL;
++    t_List           *p_Pos;
++    uint32_t         crc;
++    uint32_t         hash;
++    uint64_t         ethAddr;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    ethAddr = ((*(uint64_t *)p_EthAddr) >> 16);
++
++    /* CRC calculation */
++    crc = GetMacAddrHashCode(ethAddr);
++
++    hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;        /* Take 9 MSB bits */
++
++    LIST_FOR_EACH(p_Pos, &(p_Tgec->p_MulticastAddrHash->p_Lsts[hash]))
++    {
++        p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos);
++        if (p_HashEntry->addr == ethAddr)
++        {
++            LIST_DelAndInit(&p_HashEntry->node);
++            XX_Free(p_HashEntry);
++            break;
++        }
++    }
++    if (LIST_IsEmpty(&p_Tgec->p_MulticastAddrHash->p_Lsts[hash]))
++        fman_tgec_set_hash_table(p_Tgec->p_MemMap, (hash & ~TGEC_HASH_MCAST_EN));
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecGetId(t_Handle h_Tgec, uint32_t *macId)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    UNUSED(p_Tgec);
++    UNUSED(macId);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("TgecGetId Not Supported"));
++}
++
++/* ......................................................................... */
++
++static t_Error TgecGetVersion(t_Handle h_Tgec, uint32_t *macVersion)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    *macVersion = fman_tgec_get_revision(p_Tgec->p_MemMap);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecSetExcpetion(t_Handle h_Tgec, e_FmMacExceptions exception, bool enable)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++    uint32_t    bitMask = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++
++    GET_EXCEPTION_FLAG(bitMask, exception);
++    if (bitMask)
++    {
++        if (enable)
++            p_Tgec->exceptions |= bitMask;
++        else
++            p_Tgec->exceptions &= ~bitMask;
++   }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    if (enable)
++        fman_tgec_enable_interrupt(p_Tgec->p_MemMap, bitMask);
++    else
++        fman_tgec_disable_interrupt(p_Tgec->p_MemMap, bitMask);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static uint16_t TgecGetMaxFrameLength(t_Handle h_Tgec)
++{
++    t_Tgec      *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_VALUE(p_Tgec, E_INVALID_HANDLE, 0);
++    SANITY_CHECK_RETURN_VALUE(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE, 0);
++
++    return fman_tgec_get_max_frame_len(p_Tgec->p_MemMap);
++}
++
++/* ......................................................................... */
++
++#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
++static t_Error TgecTxEccWorkaround(t_Tgec *p_Tgec)
++{
++    t_Error err;
++
++#if defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)
++    XX_Print("Applying 10G TX ECC workaround (10GMAC-A004) ... ");
++#endif /* (DEBUG_ERRORS > 0) */
++    /* enable and set promiscuous */
++    fman_tgec_enable(p_Tgec->p_MemMap, TRUE, TRUE);
++    fman_tgec_set_promiscuous(p_Tgec->p_MemMap, TRUE);
++    err = Fm10GTxEccWorkaround(p_Tgec->fmMacControllerDriver.h_Fm, p_Tgec->macId);
++    /* disable */
++    fman_tgec_set_promiscuous(p_Tgec->p_MemMap, FALSE);
++    fman_tgec_enable(p_Tgec->p_MemMap, FALSE, FALSE);
++    fman_tgec_reset_stat(p_Tgec->p_MemMap);
++    fman_tgec_ack_event(p_Tgec->p_MemMap, 0xffffffff);
++#if defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)
++    if (err)
++        XX_Print("FAILED!\n");
++    else
++        XX_Print("done.\n");
++#endif /* (DEBUG_ERRORS > 0) */
++
++    return err;
++}
++#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
++
++/*****************************************************************************/
++/*                      FM Init & Free API                                   */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++static t_Error TgecInit(t_Handle h_Tgec)
++{
++    t_Tgec                  *p_Tgec = (t_Tgec *)h_Tgec;
++    struct tgec_cfg         *p_TgecDriverParam;
++    t_EnetAddr              ethAddr;
++    t_Error                 err;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->fmMacControllerDriver.h_Fm, E_INVALID_HANDLE);
++
++    FM_GetRevision(p_Tgec->fmMacControllerDriver.h_Fm, &p_Tgec->fmMacControllerDriver.fmRevInfo);
++    CHECK_INIT_PARAMETERS(p_Tgec, CheckInitParameters);
++
++    p_TgecDriverParam = p_Tgec->p_TgecDriverParam;
++
++    MAKE_ENET_ADDR_FROM_UINT64(p_Tgec->addr, ethAddr);
++    fman_tgec_set_mac_address(p_Tgec->p_MemMap, (uint8_t *)ethAddr);
++
++    /* interrupts */
++#ifdef FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005
++    {
++        if (p_Tgec->fmMacControllerDriver.fmRevInfo.majorRev <=2)
++            p_Tgec->exceptions &= ~(TGEC_IMASK_REM_FAULT | TGEC_IMASK_LOC_FAULT);
++    }
++#endif /* FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 */
++
++#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
++    if (!p_Tgec->p_TgecDriverParam->skip_fman11_workaround &&
++        ((err = TgecTxEccWorkaround(p_Tgec)) != E_OK))
++    {
++        FreeInitResources(p_Tgec);
++        REPORT_ERROR(MINOR, err, ("TgecTxEccWorkaround FAILED"));
++    }
++#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
++
++    err = fman_tgec_init(p_Tgec->p_MemMap, p_TgecDriverParam, p_Tgec->exceptions);
++    if (err)
++    {
++        FreeInitResources(p_Tgec);
++        RETURN_ERROR(MAJOR, err, ("This TGEC version does not support the required i/f mode"));
++    }
++
++    /* Max Frame Length */
++    err = FmSetMacMaxFrame(p_Tgec->fmMacControllerDriver.h_Fm,
++                           e_FM_MAC_10G,
++                           p_Tgec->fmMacControllerDriver.macId,
++                           p_TgecDriverParam->max_frame_length);
++    if (err != E_OK)
++    {
++        FreeInitResources(p_Tgec);
++        RETURN_ERROR(MINOR, err, NO_MSG);
++    }
++/* we consider having no IPC a non crasher... */
++
++#ifdef FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007
++    if (p_Tgec->fmMacControllerDriver.fmRevInfo.majorRev == 2)
++        fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(p_Tgec->p_MemMap);
++#endif /* FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 */
++
++    p_Tgec->p_MulticastAddrHash = AllocHashTable(HASH_TABLE_SIZE);
++    if (!p_Tgec->p_MulticastAddrHash)
++    {
++        FreeInitResources(p_Tgec);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED"));
++    }
++
++    p_Tgec->p_UnicastAddrHash = AllocHashTable(HASH_TABLE_SIZE);
++    if (!p_Tgec->p_UnicastAddrHash)
++    {
++        FreeInitResources(p_Tgec);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED"));
++    }
++
++    FmRegisterIntr(p_Tgec->fmMacControllerDriver.h_Fm,
++                   e_FM_MOD_10G_MAC,
++                   p_Tgec->macId,
++                   e_FM_INTR_TYPE_ERR,
++                   TgecErrException,
++                   p_Tgec);
++    if (p_Tgec->mdioIrq != NO_IRQ)
++    {
++        XX_SetIntr(p_Tgec->mdioIrq, TgecException, p_Tgec);
++        XX_EnableIntr(p_Tgec->mdioIrq);
++    }
++
++    XX_Free(p_TgecDriverParam);
++    p_Tgec->p_TgecDriverParam = NULL;
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static t_Error TgecFree(t_Handle h_Tgec)
++{
++    t_Tgec       *p_Tgec = (t_Tgec *)h_Tgec;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++
++    if (p_Tgec->p_TgecDriverParam)
++    {
++        /* Called after config */
++        XX_Free(p_Tgec->p_TgecDriverParam);
++        p_Tgec->p_TgecDriverParam = NULL;
++    }
++    else
++        /* Called after init */
++        FreeInitResources(p_Tgec);
++
++    XX_Free(p_Tgec);
++
++    return E_OK;
++}
++
++/* ......................................................................... */
++
++static void InitFmMacControllerDriver(t_FmMacControllerDriver *p_FmMacControllerDriver)
++{
++    p_FmMacControllerDriver->f_FM_MAC_Init                      = TgecInit;
++    p_FmMacControllerDriver->f_FM_MAC_Free                      = TgecFree;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetStatistics             = NULL;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback            = TgecConfigLoopback;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength      = TgecConfigMaxFrameLength;
++
++    p_FmMacControllerDriver->f_FM_MAC_ConfigWan                 = TgecConfigWan;
++
++    p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc           = NULL; /* TGEC always works with pad+crc */
++    p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex          = NULL; /* half-duplex is not supported in xgec */
++    p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck         = TgecConfigLengthCheck;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigException           = TgecConfigException;
++    p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit         = NULL;
++
++#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
++    p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround= TgecConfigSkipFman11Workaround;
++#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
++
++    p_FmMacControllerDriver->f_FM_MAC_SetException              = TgecSetExcpetion;
++
++    p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp       = TgecEnable1588TimeStamp;
++    p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp      = TgecDisable1588TimeStamp;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous            = TgecSetPromiscuous;
++    p_FmMacControllerDriver->f_FM_MAC_AdjustLink                = NULL;
++    p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan              = NULL;
++    p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg            = NULL;
++
++    p_FmMacControllerDriver->f_FM_MAC_Enable                    = TgecEnable;
++    p_FmMacControllerDriver->f_FM_MAC_Disable                   = TgecDisable;
++
++    p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames      = TgecTxMacPause;
++    p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames          = TgecSetTxPauseFrames;
++    p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames    = TgecRxIgnoreMacPause;
++
++    p_FmMacControllerDriver->f_FM_MAC_ResetCounters             = TgecResetCounters;
++    p_FmMacControllerDriver->f_FM_MAC_GetStatistics             = TgecGetStatistics;
++
++    p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr             = TgecModifyMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr            = TgecAddHashMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr         = TgecDelHashMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr      = TgecAddExactMatchMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr  = TgecDelExactMatchMacAddress;
++    p_FmMacControllerDriver->f_FM_MAC_GetId                     = TgecGetId;
++    p_FmMacControllerDriver->f_FM_MAC_GetVersion                = TgecGetVersion;
++    p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength         = TgecGetMaxFrameLength;
++
++    p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg           = TGEC_MII_WritePhyReg;
++    p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg            = TGEC_MII_ReadPhyReg;
++}
++
++
++/*****************************************************************************/
++/*                      Tgec Config  Main Entry                             */
++/*****************************************************************************/
++
++/* ......................................................................... */
++
++t_Handle TGEC_Config(t_FmMacParams *p_FmMacParam)
++{
++    t_Tgec              *p_Tgec;
++    struct tgec_cfg     *p_TgecDriverParam;
++    uintptr_t           baseAddr;
++
++    SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_NULL_POINTER, NULL);
++
++    baseAddr = p_FmMacParam->baseAddr;
++    /* allocate memory for the UCC GETH data structure. */
++    p_Tgec = (t_Tgec *)XX_Malloc(sizeof(t_Tgec));
++    if (!p_Tgec)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("10G MAC driver structure"));
++        return NULL;
++    }
++    memset(p_Tgec, 0, sizeof(t_Tgec));
++    InitFmMacControllerDriver(&p_Tgec->fmMacControllerDriver);
++
++    /* allocate memory for the 10G MAC driver parameters data structure. */
++    p_TgecDriverParam = (struct tgec_cfg *) XX_Malloc(sizeof(struct tgec_cfg));
++    if (!p_TgecDriverParam)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("10G MAC driver parameters"));
++        XX_Free(p_Tgec);
++        return NULL;
++    }
++    memset(p_TgecDriverParam, 0, sizeof(struct tgec_cfg));
++
++    /* Plant parameter structure pointer */
++    p_Tgec->p_TgecDriverParam = p_TgecDriverParam;
++
++    fman_tgec_defconfig(p_TgecDriverParam);
++
++    p_Tgec->p_MemMap        = (struct tgec_regs *)UINT_TO_PTR(baseAddr);
++    p_Tgec->p_MiiMemMap     = (t_TgecMiiAccessMemMap *)UINT_TO_PTR(baseAddr + TGEC_TO_MII_OFFSET);
++    p_Tgec->addr            = ENET_ADDR_TO_UINT64(p_FmMacParam->addr);
++    p_Tgec->enetMode        = p_FmMacParam->enetMode;
++    p_Tgec->macId           = p_FmMacParam->macId;
++    p_Tgec->exceptions      = DEFAULT_exceptions;
++    p_Tgec->mdioIrq         = p_FmMacParam->mdioIrq;
++    p_Tgec->f_Exception     = p_FmMacParam->f_Exception;
++    p_Tgec->f_Event         = p_FmMacParam->f_Event;
++    p_Tgec->h_App           = p_FmMacParam->h_App;
++
++    return p_Tgec;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.h
+new file mode 100644
+index 0000000..2aa3923
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.h
+@@ -0,0 +1,151 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          tgec.h
++
++ @Description   FM 10G MAC ...
++*//***************************************************************************/
++#ifndef __TGEC_H
++#define __TGEC_H
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "list_ext.h"
++#include "enet_ext.h"
++
++#include "tgec_mii_acc.h"
++#include "fm_mac.h"
++
++
++#define DEFAULT_exceptions                        \
++    ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT     |  \
++                TGEC_IMASK_REM_FAULT           |  \
++                TGEC_IMASK_LOC_FAULT           |  \
++                TGEC_IMASK_TX_ECC_ER           |  \
++                TGEC_IMASK_TX_FIFO_UNFL        |  \
++                TGEC_IMASK_TX_FIFO_OVFL        |  \
++                TGEC_IMASK_TX_ER               |  \
++                TGEC_IMASK_RX_FIFO_OVFL        |  \
++                TGEC_IMASK_RX_ECC_ER           |  \
++                TGEC_IMASK_RX_JAB_FRM          |  \
++                TGEC_IMASK_RX_OVRSZ_FRM        |  \
++                TGEC_IMASK_RX_RUNT_FRM         |  \
++                TGEC_IMASK_RX_FRAG_FRM         |  \
++                TGEC_IMASK_RX_CRC_ER           |  \
++                TGEC_IMASK_RX_ALIGN_ER))
++
++#define GET_EXCEPTION_FLAG(bitMask, exception)      switch (exception){ \
++    case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO:                           \
++        bitMask = TGEC_IMASK_MDIO_SCAN_EVENT    ; break;                \
++    case e_FM_MAC_EX_10G_MDIO_CMD_CMPL:                                 \
++        bitMask = TGEC_IMASK_MDIO_CMD_CMPL      ; break;                \
++    case e_FM_MAC_EX_10G_REM_FAULT:                                     \
++        bitMask = TGEC_IMASK_REM_FAULT          ; break;                \
++    case e_FM_MAC_EX_10G_LOC_FAULT:                                     \
++        bitMask = TGEC_IMASK_LOC_FAULT          ; break;                \
++    case e_FM_MAC_EX_10G_1TX_ECC_ER:                                    \
++        bitMask = TGEC_IMASK_TX_ECC_ER         ; break;                 \
++    case e_FM_MAC_EX_10G_TX_FIFO_UNFL:                                  \
++        bitMask = TGEC_IMASK_TX_FIFO_UNFL       ; break;                \
++    case e_FM_MAC_EX_10G_TX_FIFO_OVFL:                                  \
++        bitMask = TGEC_IMASK_TX_FIFO_OVFL       ; break;                \
++    case e_FM_MAC_EX_10G_TX_ER:                                         \
++        bitMask = TGEC_IMASK_TX_ER              ; break;                \
++    case e_FM_MAC_EX_10G_RX_FIFO_OVFL:                                  \
++        bitMask = TGEC_IMASK_RX_FIFO_OVFL       ; break;                \
++    case e_FM_MAC_EX_10G_RX_ECC_ER:                                     \
++        bitMask = TGEC_IMASK_RX_ECC_ER          ; break;                \
++    case e_FM_MAC_EX_10G_RX_JAB_FRM:                                    \
++        bitMask = TGEC_IMASK_RX_JAB_FRM         ; break;                \
++    case e_FM_MAC_EX_10G_RX_OVRSZ_FRM:                                  \
++        bitMask = TGEC_IMASK_RX_OVRSZ_FRM       ; break;                \
++    case e_FM_MAC_EX_10G_RX_RUNT_FRM:                                   \
++        bitMask = TGEC_IMASK_RX_RUNT_FRM        ; break;                \
++    case e_FM_MAC_EX_10G_RX_FRAG_FRM:                                   \
++        bitMask = TGEC_IMASK_RX_FRAG_FRM        ; break;                \
++    case e_FM_MAC_EX_10G_RX_LEN_ER:                                     \
++        bitMask = TGEC_IMASK_RX_LEN_ER          ; break;                \
++    case e_FM_MAC_EX_10G_RX_CRC_ER:                                     \
++        bitMask = TGEC_IMASK_RX_CRC_ER          ; break;                \
++    case e_FM_MAC_EX_10G_RX_ALIGN_ER:                                   \
++        bitMask = TGEC_IMASK_RX_ALIGN_ER        ; break;                \
++    default: bitMask = 0;break;}
++
++#define MAX_PACKET_ALIGNMENT        31
++#define MAX_INTER_PACKET_GAP        0x7f
++#define MAX_INTER_PALTERNATE_BEB    0x0f
++#define MAX_RETRANSMISSION          0x0f
++#define MAX_COLLISION_WINDOW        0x03ff
++
++#define TGEC_NUM_OF_PADDRS          1                   /* number of pattern match registers (entries) */
++
++#define GROUP_ADDRESS               0x0000010000000000LL /* Group address bit indication */
++
++#define HASH_TABLE_SIZE             512                 /* Hash table size (= 32 bits * 8 regs) */
++
++#define TGEC_TO_MII_OFFSET          0x1030              /* Offset from the MEM map to the MDIO mem map */
++
++/* 10-gigabit Ethernet MAC Controller ID (10GEC_ID) */
++#define TGEC_ID_ID                  0xffff0000
++#define TGEC_ID_MAC_VERSION         0x0000FF00
++#define TGEC_ID_MAC_REV             0x000000ff
++
++
++typedef struct {
++    t_FmMacControllerDriver     fmMacControllerDriver;              /**< Upper Mac control block */
++    t_Handle                    h_App;                              /**< Handle to the upper layer application  */
++    struct tgec_regs            *p_MemMap;                          /**< pointer to 10G memory mapped registers. */
++    t_TgecMiiAccessMemMap       *p_MiiMemMap;                       /**< pointer to MII memory mapped registers.          */
++    uint64_t                    addr;                               /**< MAC address of device; */
++    e_EnetMode                  enetMode;                           /**< Ethernet physical interface  */
++    t_FmMacExceptionCallback    *f_Exception;
++    int                         mdioIrq;
++    t_FmMacExceptionCallback    *f_Event;
++    bool                        indAddrRegUsed[TGEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
++    uint64_t                    paddr[TGEC_NUM_OF_PADDRS];          /**< MAC address for particular individual address recognition register */
++    uint8_t                     numOfIndAddrInRegs;                 /**< Number of individual addresses in registers for this station. */
++    t_EthHash                   *p_MulticastAddrHash;               /**< pointer to driver's global address hash table  */
++    t_EthHash                   *p_UnicastAddrHash;                 /**< pointer to driver's individual address hash table  */
++    bool                        debugMode;
++    uint8_t                     macId;
++    uint32_t                    exceptions;
++    struct tgec_cfg             *p_TgecDriverParam;
++} t_Tgec;
++
++
++t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t data);
++t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,  uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
++
++
++#endif /* __TGEC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c
+new file mode 100644
+index 0000000..e0fafd1
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c
+@@ -0,0 +1,139 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++
++#include "error_ext.h"
++#include "std_ext.h"
++#include "fm_mac.h"
++#include "tgec.h"
++#include "xx_ext.h"
++
++#include "fm_common.h"
++
++
++/*****************************************************************************/
++t_Error TGEC_MII_WritePhyReg(t_Handle   h_Tgec,
++                             uint8_t    phyAddr,
++                             uint8_t    reg,
++                             uint16_t   data)
++{
++    t_Tgec                  *p_Tgec = (t_Tgec *)h_Tgec;
++    t_TgecMiiAccessMemMap   *p_MiiAccess;
++    uint32_t                cfgStatusReg;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
++
++    p_MiiAccess = p_Tgec->p_MiiMemMap;
++
++    /* Configure MII */
++    cfgStatusReg  = GET_UINT32(p_MiiAccess->mdio_cfg_status);
++    cfgStatusReg &= ~MIIMCOM_DIV_MASK;
++     /* (one half of fm clock => 2.5Mhz) */
++    cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
++    WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
++
++    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
++        XX_UDelay (1);
++
++    WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
++
++    WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
++
++    CORE_MemoryBarrier();
++
++    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
++        XX_UDelay (1);
++
++    WRITE_UINT32(p_MiiAccess->mdio_data, data);
++
++    CORE_MemoryBarrier();
++
++    while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
++        XX_UDelay (1);
++
++    return E_OK;
++}
++
++/*****************************************************************************/
++t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
++                            uint8_t  phyAddr,
++                            uint8_t  reg,
++                            uint16_t *p_Data)
++{
++    t_Tgec                  *p_Tgec = (t_Tgec *)h_Tgec;
++    t_TgecMiiAccessMemMap   *p_MiiAccess;
++    uint32_t                cfgStatusReg;
++
++    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
++
++    p_MiiAccess = p_Tgec->p_MiiMemMap;
++
++    /* Configure MII */
++    cfgStatusReg  = GET_UINT32(p_MiiAccess->mdio_cfg_status);
++    cfgStatusReg &= ~MIIMCOM_DIV_MASK;
++     /* (one half of fm clock => 2.5Mhz) */
++    cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
++    WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
++
++    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
++        XX_UDelay (1);
++
++    WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
++
++    WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
++
++    CORE_MemoryBarrier();
++
++    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
++        XX_UDelay (1);
++
++    WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE));
++
++    CORE_MemoryBarrier();
++
++    while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
++        XX_UDelay (1);
++
++    *p_Data =  (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
++
++    cfgStatusReg  = GET_UINT32(p_MiiAccess->mdio_cfg_status);
++
++    if (cfgStatusReg & MIIMIND_READ_ERROR)
++        RETURN_ERROR(MINOR, E_INVALID_VALUE,
++                     ("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfgStatusReg 0x%x",
++                      ((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfgStatusReg));
++
++    return E_OK;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h
+new file mode 100644
+index 0000000..645cdde
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h
+@@ -0,0 +1,80 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++#ifndef __TGEC_MII_ACC_H
++#define __TGEC_MII_ACC_H
++
++#include "std_ext.h"
++
++
++/* MII  Management Command Register */
++#define MIIMCOM_READ_POST_INCREMENT 0x00004000
++#define MIIMCOM_READ_CYCLE          0x00008000
++#define MIIMCOM_SCAN_CYCLE          0x00000800
++#define MIIMCOM_PREAMBLE_DISABLE    0x00000400
++
++#define MIIMCOM_MDIO_HOLD_1_REG_CLK 0
++#define MIIMCOM_MDIO_HOLD_2_REG_CLK 1
++#define MIIMCOM_MDIO_HOLD_3_REG_CLK 2
++#define MIIMCOM_MDIO_HOLD_4_REG_CLK 3
++
++#define MIIMCOM_DIV_MASK            0x0000ff00
++#define MIIMCOM_DIV_SHIFT           8
++
++/* MII Management Indicator Register */
++#define MIIMIND_BUSY                0x00000001
++#define MIIMIND_READ_ERROR          0x00000002
++
++#define MIIDATA_BUSY                0x80000000
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(push,1)
++#endif /* defined(__MWERKS__) && ... */
++
++/*----------------------------------------------------*/
++/* MII Configuration Control Memory Map Registers     */
++/*----------------------------------------------------*/
++typedef _Packed struct t_TgecMiiAccessMemMap
++{
++    volatile uint32_t   mdio_cfg_status;    /* 0x030  */
++    volatile uint32_t   mdio_command;       /* 0x034  */
++    volatile uint32_t   mdio_data;          /* 0x038  */
++    volatile uint32_t   mdio_regaddr;       /* 0x03c  */
++} _PackedType t_TgecMiiAccessMemMap ;
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(pop)
++#endif /* defined(__MWERKS__) && ... */
++
++
++#endif /* __TGEC_MII_ACC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/Makefile b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/Makefile
+new file mode 100644
+index 0000000..bfa02f5
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/Makefile
+@@ -0,0 +1,15 @@
++#
++# Makefile for the Freescale Ethernet controllers
++#
++ccflags-y           += -DVERSION=\"\"
++#
++#Include netcomm SW specific definitions
++include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
++
++NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
++
++ccflags-y += -I$(NCSW_FM_INC)
++
++obj-y		+= fsl-ncsw-macsec.o
++
++fsl-ncsw-macsec-objs	:= fm_macsec.o fm_macsec_guest.o fm_macsec_master.o fm_macsec_secy.o
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c
+new file mode 100644
+index 0000000..0a1b31f
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c
+@@ -0,0 +1,237 @@
++/*
++ * Copyright 2008-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++/******************************************************************************
++
++ @File          fm_macsec.c
++
++ @Description   FM MACSEC driver routines implementation.
++*//***************************************************************************/
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "xx_ext.h"
++#include "string_ext.h"
++#include "sprint_ext.h"
++#include "debug_ext.h"
++
++#include "fm_macsec.h"
++
++
++/****************************************/
++/*       API Init unit functions        */
++/****************************************/
++t_Handle FM_MACSEC_Config(t_FmMacsecParams *p_FmMacsecParam)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver;
++
++    SANITY_CHECK_RETURN_VALUE(p_FmMacsecParam, E_INVALID_HANDLE, NULL);
++
++    if (p_FmMacsecParam->guestMode)
++        p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_GUEST_Config(p_FmMacsecParam);
++    else
++        p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_MASTER_Config(p_FmMacsecParam);
++
++    if (!p_FmMacsecControllerDriver)
++        return NULL;
++
++    return (t_Handle)p_FmMacsecControllerDriver;
++}
++
++t_Error FM_MACSEC_Init(t_Handle h_FmMacsec)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_Init)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_Init(h_FmMacsec);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_Free(t_Handle h_FmMacsec)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_Free)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_Free(h_FmMacsec);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigUnknownSciFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment(h_FmMacsec, treatMode);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigInvalidTagsFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment(h_FmMacsec, deliverUncontrolled);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(t_Handle h_FmMacsec, bool discardUncontrolled)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(h_FmMacsec, discardUncontrolled);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigUntagFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment(h_FmMacsec, treatMode);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigPnExhaustionThreshold(t_Handle h_FmMacsec, uint32_t pnExhThr)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold(h_FmMacsec, pnExhThr);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigKeysUnreadable(t_Handle h_FmMacsec)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable(h_FmMacsec);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigSectagWithoutSCI(t_Handle h_FmMacsec)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI(h_FmMacsec);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_ConfigException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException(h_FmMacsec, exception, enable);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_GetRevision(t_Handle h_FmMacsec, uint32_t *p_MacsecRevision)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision(h_FmMacsec, p_MacsecRevision);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++
++t_Error FM_MACSEC_Enable(t_Handle h_FmMacsec)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_Enable)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_Enable(h_FmMacsec);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_Disable(t_Handle h_FmMacsec)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_Disable)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_Disable(h_FmMacsec);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_SetException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
++{
++    t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
++
++    if (p_FmMacsecControllerDriver->f_FM_MACSEC_SetException)
++        return p_FmMacsecControllerDriver->f_FM_MACSEC_SetException(h_FmMacsec, exception, enable);
++
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h
+new file mode 100644
+index 0000000..fbe5187
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h
+@@ -0,0 +1,203 @@
++/*
++ * Copyright 2008-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          fm_macsec.h
++
++ @Description   FM MACSEC internal structures and definitions.
++*//***************************************************************************/
++#ifndef __FM_MACSEC_H
++#define __FM_MACSEC_H
++
++#include "error_ext.h"
++#include "std_ext.h"
++#include "fm_macsec_ext.h"
++
++#include "fm_common.h"
++
++
++#define __ERR_MODULE__  MODULE_FM_MACSEC
++
++
++typedef struct
++{
++    t_Error (*f_FM_MACSEC_Init) (t_Handle h_FmMacsec);
++    t_Error (*f_FM_MACSEC_Free) (t_Handle h_FmMacsec);
++
++    t_Error (*f_FM_MACSEC_ConfigUnknownSciFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode);
++    t_Error (*f_FM_MACSEC_ConfigInvalidTagsFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
++    t_Error (*f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment) (t_Handle h_FmMacsec, bool discardUncontrolled);
++    t_Error (*f_FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
++    t_Error (*f_FM_MACSEC_ConfigUntagFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode);
++    t_Error (*f_FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
++    t_Error (*f_FM_MACSEC_ConfigPnExhaustionThreshold) (t_Handle h_FmMacsec, uint32_t pnExhThr);
++    t_Error (*f_FM_MACSEC_ConfigKeysUnreadable) (t_Handle h_FmMacsec);
++    t_Error (*f_FM_MACSEC_ConfigSectagWithoutSCI) (t_Handle h_FmMacsec);
++    t_Error (*f_FM_MACSEC_ConfigException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable);
++
++    t_Error (*f_FM_MACSEC_GetRevision) (t_Handle h_FmMacsec, uint32_t *p_MacsecRevision);
++    t_Error (*f_FM_MACSEC_Enable) (t_Handle h_FmMacsec);
++    t_Error (*f_FM_MACSEC_Disable) (t_Handle h_FmMacsec);
++    t_Error (*f_FM_MACSEC_SetException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable);
++
++} t_FmMacsecControllerDriver;
++
++t_Handle  FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam);
++t_Handle  FM_MACSEC_MASTER_Config(t_FmMacsecParams *p_FmMacsecParams);
++
++/***********************************************************************/
++/*  MACSEC internal routines                                              */
++/***********************************************************************/
++
++/**************************************************************************//**
++
++ @Group         FM_MACSEC_InterModule_grp FM MACSEC Inter-Module Unit
++
++ @Description   FM MACSEC Inter Module functions -
++                These are not User API routines but routines that may be called
++                from other modules. This will be the case in a single core environment,
++                where instead of using the XX messaging mechanism, the routines may be
++                called from other modules. In a multicore environment, the other modules may
++                be run by other cores and therefore these routines may not be called directly.
++
++ @{
++*//***************************************************************************/
++
++#define MAX_NUM_OF_SA_PER_SC        4
++
++typedef enum
++{
++    e_SC_RX = 0,
++    e_SC_TX
++} e_ScType;
++
++typedef enum
++{
++    e_SC_SA_A = 0,
++    e_SC_SA_B ,
++    e_SC_SA_C ,
++    e_SC_SA_D
++} e_ScSaId;
++
++typedef struct
++{
++    uint32_t                        scId;
++    macsecSCI_t                     sci;
++    bool                            replayProtect;
++    uint32_t                        replayWindow;
++    e_FmMacsecValidFrameBehavior    validateFrames;
++    uint16_t                        confidentialityOffset;
++    e_FmMacsecSecYCipherSuite       cipherSuite;
++} t_RxScParams;
++
++typedef struct
++{
++    uint32_t                        scId;
++    macsecSCI_t                     sci;
++    bool                            protectFrames;
++    e_FmMacsecSciInsertionMode      sciInsertionMode;
++    bool                            confidentialityEnable;
++    uint16_t                        confidentialityOffset;
++    e_FmMacsecSecYCipherSuite       cipherSuite;
++} t_TxScParams;
++
++typedef enum e_FmMacsecGlobalExceptions {
++    e_FM_MACSEC_EX_TX_SC,               /**< Tx Sc 0 frame discarded error. */
++    e_FM_MACSEC_EX_ECC                  /**< MACSEC memory ECC multiple-bit error. */
++} e_FmMacsecGlobalExceptions;
++
++typedef enum e_FmMacsecGlobalEvents {
++    e_FM_MACSEC_EV_TX_SC_NEXT_PN        /**< Tx Sc 0 Next Pn exhaustion threshold reached. */
++} e_FmMacsecGlobalEvents;
++
++/**************************************************************************//**
++ @Description   Enum for inter-module interrupts registration
++*//***************************************************************************/
++typedef enum e_FmMacsecEventModules{
++    e_FM_MACSEC_MOD_SC_TX,
++    e_FM_MACSEC_MOD_DUMMY_LAST
++} e_FmMacsecEventModules;
++
++typedef enum e_FmMacsecInterModuleEvent {
++    e_FM_MACSEC_EV_SC_TX,
++    e_FM_MACSEC_EV_ERR_SC_TX,
++    e_FM_MACSEC_EV_DUMMY_LAST
++} e_FmMacsecInterModuleEvent;
++
++#define NUM_OF_INTER_MODULE_EVENTS (NUM_OF_TX_SC * 2)
++
++#define GET_MACSEC_MODULE_EVENT(mod, id, intrType, event) \
++    switch(mod){                                          \
++        case e_FM_MACSEC_MOD_SC_TX:                       \
++             event = (intrType == e_FM_INTR_TYPE_ERR) ?   \
++                        e_FM_MACSEC_EV_ERR_SC_TX:         \
++                        e_FM_MACSEC_EV_SC_TX;             \
++             event += (uint8_t)(2 * id);break;            \
++            break;                                        \
++        default:event = e_FM_MACSEC_EV_DUMMY_LAST;        \
++        break;}
++
++void FmMacsecRegisterIntr(t_Handle                h_FmMacsec,
++                          e_FmMacsecEventModules  module,
++                          uint8_t                 modId,
++                          e_FmIntrType            intrType,
++                          void (*f_Isr) (t_Handle h_Arg, uint32_t id),
++                          t_Handle                h_Arg);
++
++void FmMacsecUnregisterIntr(t_Handle                h_FmMacsec,
++                            e_FmMacsecEventModules  module,
++                            uint8_t                 modId,
++                            e_FmIntrType            intrType);
++
++t_Error FmMacsecAllocScs(t_Handle h_FmMacsec, e_ScType type, bool isPtp, uint32_t numOfScs, uint32_t *p_ScIds);
++t_Error FmMacsecFreeScs(t_Handle h_FmMacsec, e_ScType type, uint32_t numOfScs, uint32_t *p_ScIds);
++t_Error FmMacsecCreateRxSc(t_Handle h_FmMacsec, t_RxScParams *p_RxScParams);
++t_Error FmMacsecDeleteRxSc(t_Handle h_FmMacsec, uint32_t scId);
++t_Error FmMacsecCreateTxSc(t_Handle h_FmMacsec, t_TxScParams *p_RxScParams);
++t_Error FmMacsecDeleteTxSc(t_Handle h_FmMacsec, uint32_t scId);
++t_Error FmMacsecCreateRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key);
++t_Error FmMacsecCreateTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecSAKey_t key);
++t_Error FmMacsecDeleteRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId);
++t_Error FmMacsecDeleteTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId);
++t_Error FmMacsecRxSaSetReceive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, bool enableReceive);
++t_Error FmMacsecRxSaUpdateNextPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtNextPN);
++t_Error FmMacsecRxSaUpdateLowestPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtLowestPN);
++t_Error FmMacsecTxSaSetActive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an);
++t_Error FmMacsecTxSaGetActive(t_Handle h_FmMacsec, uint32_t scId, macsecAN_t *p_An);
++t_Error FmMacsecSetPTP(t_Handle h_FmMacsec, bool enable);
++
++t_Error FmMacsecSetException(t_Handle h_FmMacsec, e_FmMacsecGlobalExceptions exception, uint32_t scId, bool enable);
++t_Error FmMacsecSetEvent(t_Handle h_FmMacsec, e_FmMacsecGlobalEvents event, uint32_t scId, bool enable);
++
++
++
++#endif /* __FM_MACSEC_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_guest.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_guest.c
+new file mode 100644
+index 0000000..31d789d
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_guest.c
+@@ -0,0 +1,59 @@
++/*
++ * Copyright 2008-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          fm_macsec.c
++
++ @Description   FM MACSEC driver routines implementation.
++*//***************************************************************************/
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "xx_ext.h"
++#include "string_ext.h"
++#include "sprint_ext.h"
++#include "debug_ext.h"
++#include "fm_macsec.h"
++
++
++/****************************************/
++/*       static functions               */
++/****************************************/
++
++/****************************************/
++/*       API Init unit functions        */
++/****************************************/
++t_Handle FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam)
++{
++    UNUSED(p_FmMacsecParam);
++    return NULL;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.c
+new file mode 100644
+index 0000000..79260c8
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.c
+@@ -0,0 +1,1031 @@
++/*
++ * Copyright 2008-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          fm_macsec.c
++
++ @Description   FM MACSEC driver routines implementation.
++*//***************************************************************************/
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "xx_ext.h"
++#include "string_ext.h"
++#include "sprint_ext.h"
++#include "fm_mac_ext.h"
++
++#include "fm_macsec_master.h"
++
++
++extern uint16_t    FM_MAC_GetMaxFrameLength(t_Handle FmMac);
++
++
++/****************************************/
++/*       static functions               */
++/****************************************/
++static t_Error CheckFmMacsecParameters(t_FmMacsec *p_FmMacsec)
++{
++    if (!p_FmMacsec->f_Exception)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided"));
++
++    return E_OK;
++}
++
++static void UnimplementedIsr(t_Handle h_Arg, uint32_t id)
++{
++    UNUSED(h_Arg); UNUSED(id);
++
++    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unimplemented Isr!"));
++}
++
++static void MacsecEventIsr(t_Handle h_FmMacsec)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    events,event,i;
++
++    SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE);
++
++    events = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->evr);
++    events |= GET_UINT32(p_FmMacsec->p_FmMacsecRegs->ever);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->evr,events);
++
++    for (i=0; i<NUM_OF_TX_SC; i++)
++        if (events & FM_MACSEC_EV_TX_SC_NEXT_PN(i))
++        {
++            GET_MACSEC_MODULE_EVENT(e_FM_MACSEC_MOD_SC_TX, i, e_FM_INTR_TYPE_NORMAL, event);
++            p_FmMacsec->intrMng[event].f_Isr(p_FmMacsec->intrMng[event].h_SrcHandle, i);
++        }
++}
++
++static void MacsecErrorIsr(t_Handle h_FmMacsec)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    errors,error,i;
++
++    SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE);
++
++    errors = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->err);
++    errors |= GET_UINT32(p_FmMacsec->p_FmMacsecRegs->erer);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->err,errors);
++
++    for (i=0; i<NUM_OF_TX_SC; i++)
++        if (errors & FM_MACSEC_EX_TX_SC(i))
++        {
++            GET_MACSEC_MODULE_EVENT(e_FM_MACSEC_MOD_SC_TX, i, e_FM_INTR_TYPE_ERR, error);
++            p_FmMacsec->intrMng[error].f_Isr(p_FmMacsec->intrMng[error].h_SrcHandle, i);
++        }
++
++    if (errors & FM_MACSEC_EX_ECC)
++    {
++        uint8_t     eccType;
++        uint32_t    tmpReg;
++
++        tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->meec);
++        ASSERT_COND(tmpReg & MECC_CAP);
++        eccType = (uint8_t)((tmpReg & MECC_CET) >> MECC_CET_SHIFT);
++
++        if (!eccType && (p_FmMacsec->userExceptions & FM_MACSEC_USER_EX_SINGLE_BIT_ECC))
++            p_FmMacsec->f_Exception(p_FmMacsec->h_App,e_FM_MACSEC_EX_SINGLE_BIT_ECC);
++        else if (eccType && (p_FmMacsec->userExceptions & FM_MACSEC_USER_EX_MULTI_BIT_ECC))
++            p_FmMacsec->f_Exception(p_FmMacsec->h_App,e_FM_MACSEC_EX_MULTI_BIT_ECC);
++        else
++            WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->meec,tmpReg);
++    }
++}
++
++static t_Error MacsecInit(t_Handle h_FmMacsec)
++{
++    t_FmMacsec                  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_FmMacsecDriverParam       *p_FmMacsecDriverParam = NULL;
++    uint32_t                    tmpReg,i,macId;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    CHECK_INIT_PARAMETERS(p_FmMacsec, CheckFmMacsecParameters);
++
++    p_FmMacsecDriverParam = p_FmMacsec->p_FmMacsecDriverParam;
++
++    for (i=0;i<e_FM_MACSEC_EV_DUMMY_LAST;i++)
++        p_FmMacsec->intrMng[i].f_Isr = UnimplementedIsr;
++
++    tmpReg = 0;
++    tmpReg |= (p_FmMacsecDriverParam->changedTextWithNoEncryptDeliverUncontrolled << CFG_UECT_SHIFT)|
++              (p_FmMacsecDriverParam->onlyScbIsSetDeliverUncontrolled << CFG_ESCBT_SHIFT)           |
++              (p_FmMacsecDriverParam->unknownSciTreatMode << CFG_USFT_SHIFT)                        |
++              (p_FmMacsecDriverParam->invalidTagsDeliverUncontrolled << CFG_ITT_SHIFT)              |
++              (p_FmMacsecDriverParam->encryptWithNoChangedTextDiscardUncontrolled << CFG_KFT_SHIFT) |
++              (p_FmMacsecDriverParam->untagTreatMode << CFG_UFT_SHIFT)                              |
++              (p_FmMacsecDriverParam->keysUnreadable << CFG_KSS_SHIFT)                              |
++              (p_FmMacsecDriverParam->reservedSc0 << CFG_S0I_SHIFT)                                 |
++              (p_FmMacsecDriverParam->byPassMode << CFG_BYPN_SHIFT);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg, tmpReg);
++
++    tmpReg = FM_MAC_GetMaxFrameLength(p_FmMacsec->h_FmMac);
++    /* At least Ethernet FCS (4 bytes) overhead must be subtracted from MFL.
++     * In addition, the SCI (8 bytes) overhead might be subtracted as well. */
++    tmpReg -= p_FmMacsecDriverParam->mflSubtract;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->mfl, tmpReg);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->tpnet, p_FmMacsecDriverParam->pnExhThr);
++
++    if (!p_FmMacsec->userExceptions)
++        p_FmMacsec->exceptions &= ~FM_MACSEC_EX_ECC;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->erer, p_FmMacsec->exceptions);
++
++    p_FmMacsec->numRxScAvailable = NUM_OF_RX_SC;
++    if (p_FmMacsecDriverParam->reservedSc0)
++        p_FmMacsec->numRxScAvailable --;
++    p_FmMacsec->numTxScAvailable = NUM_OF_TX_SC;
++
++    XX_Free(p_FmMacsecDriverParam);
++    p_FmMacsec->p_FmMacsecDriverParam = NULL;
++
++    FM_MAC_GetId(p_FmMacsec->h_FmMac, &macId);
++    FmRegisterIntr(p_FmMacsec->h_Fm,
++                   e_FM_MOD_MACSEC,
++                   (uint8_t)macId,
++                   e_FM_INTR_TYPE_NORMAL,
++                   MacsecEventIsr,
++                   p_FmMacsec);
++
++    FmRegisterIntr(p_FmMacsec->h_Fm,
++                   e_FM_MOD_MACSEC,
++                   0,
++                   e_FM_INTR_TYPE_ERR,
++                   MacsecErrorIsr,
++                   p_FmMacsec);
++
++    return E_OK;
++}
++
++static t_Error MacsecFree(t_Handle h_FmMacsec)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    macId;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    FM_MAC_GetId(p_FmMacsec->h_FmMac, &macId);
++    FmUnregisterIntr(p_FmMacsec->h_Fm,
++                   e_FM_MOD_MACSEC,
++                   (uint8_t)macId,
++                   e_FM_INTR_TYPE_NORMAL);
++
++    FmUnregisterIntr(p_FmMacsec->h_Fm,
++                   e_FM_MOD_MACSEC,
++                   0,
++                   e_FM_INTR_TYPE_ERR);
++
++    if (p_FmMacsec->rxScSpinLock)
++        XX_FreeSpinlock(p_FmMacsec->rxScSpinLock);
++    if (p_FmMacsec->txScSpinLock)
++        XX_FreeSpinlock(p_FmMacsec->txScSpinLock);
++
++    XX_Free(p_FmMacsec);
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigUnknownSciFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->unknownSciTreatMode = treatMode;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigInvalidTagsFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->invalidTagsDeliverUncontrolled = deliverUncontrolled;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigChangedTextWithNoEncryptFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->changedTextWithNoEncryptDeliverUncontrolled = deliverUncontrolled;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigOnlyScbIsSetFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->onlyScbIsSetDeliverUncontrolled = deliverUncontrolled;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigEncryptWithNoChangedTextFrameTreatment(t_Handle h_FmMacsec, bool discardUncontrolled)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->encryptWithNoChangedTextDiscardUncontrolled = discardUncontrolled;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigUntagFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->untagTreatMode = treatMode;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigPnExhaustionThreshold(t_Handle h_FmMacsec, uint32_t pnExhThr)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->pnExhThr = pnExhThr;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigKeysUnreadable(t_Handle h_FmMacsec)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->keysUnreadable = TRUE;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigSectagWithoutSCI(t_Handle h_FmMacsec)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    p_FmMacsec->p_FmMacsecDriverParam->sectagOverhead -= MACSEC_SCI_SIZE;
++    p_FmMacsec->p_FmMacsecDriverParam->mflSubtract += MACSEC_SCI_SIZE;
++
++    return E_OK;
++}
++
++static t_Error MacsecConfigException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    bitMask = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    GET_USER_EXCEPTION_FLAG(bitMask, exception);
++    if (bitMask)
++    {
++        if (enable)
++            p_FmMacsec->userExceptions |= bitMask;
++        else
++            p_FmMacsec->userExceptions &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    return E_OK;
++}
++
++static t_Error MacsecGetRevision(t_Handle h_FmMacsec, uint32_t *p_MacsecRevision)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    *p_MacsecRevision = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->ip_rev1);
++
++    return E_OK;
++}
++
++static t_Error MacsecEnable(t_Handle h_FmMacsec)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    tmpReg;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    tmpReg  = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg);
++    tmpReg |= CFG_BYPN;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg,tmpReg);
++
++    return E_OK;
++}
++
++static t_Error MacsecDisable(t_Handle h_FmMacsec)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    tmpReg;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    tmpReg  = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg);
++    tmpReg &= ~CFG_BYPN;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg,tmpReg);
++
++    return E_OK;
++}
++
++static t_Error MacsecSetException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    bitMask;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    GET_USER_EXCEPTION_FLAG(bitMask, exception);
++    if (bitMask)
++    {
++        if (enable)
++            p_FmMacsec->userExceptions |= bitMask;
++        else
++            p_FmMacsec->userExceptions &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    if (!p_FmMacsec->userExceptions)
++        p_FmMacsec->exceptions &= ~FM_MACSEC_EX_ECC;
++    else
++        p_FmMacsec->exceptions |= FM_MACSEC_EX_ECC;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->erer, p_FmMacsec->exceptions);
++
++    return E_OK;
++}
++
++static void InitFmMacsecControllerDriver(t_FmMacsecControllerDriver *p_FmMacsecControllerDriver)
++{
++    p_FmMacsecControllerDriver->f_FM_MACSEC_Init                                            = MacsecInit;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_Free                                            = MacsecFree;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment                  = MacsecConfigUnknownSciFrameTreatment;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment                 = MacsecConfigInvalidTagsFrameTreatment;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment    = MacsecConfigEncryptWithNoChangedTextFrameTreatment;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment                       = MacsecConfigUntagFrameTreatment;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment    = MacsecConfigChangedTextWithNoEncryptFrameTreatment;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment                = MacsecConfigOnlyScbIsSetFrameTreatment;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold                     = MacsecConfigPnExhaustionThreshold;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable                            = MacsecConfigKeysUnreadable;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI                          = MacsecConfigSectagWithoutSCI;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException                                 = MacsecConfigException;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision                                     = MacsecGetRevision;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_Enable                                          = MacsecEnable;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_Disable                                         = MacsecDisable;
++    p_FmMacsecControllerDriver->f_FM_MACSEC_SetException                                    = MacsecSetException;
++}
++
++/****************************************/
++/*       Inter-Module functions         */
++/****************************************/
++
++void FmMacsecRegisterIntr(t_Handle                h_FmMacsec,
++                          e_FmMacsecEventModules  module,
++                          uint8_t                 modId,
++                          e_FmIntrType            intrType,
++                          void (*f_Isr) (t_Handle h_Arg, uint32_t id),
++                          t_Handle                h_Arg)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint8_t     event= 0;
++
++    SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE);
++
++    GET_MACSEC_MODULE_EVENT(module, modId, intrType, event);
++
++    ASSERT_COND(event != e_FM_MACSEC_EV_DUMMY_LAST);
++    p_FmMacsec->intrMng[event].f_Isr = f_Isr;
++    p_FmMacsec->intrMng[event].h_SrcHandle = h_Arg;
++}
++
++void FmMacsecUnregisterIntr(t_Handle                h_FmMacsec,
++                            e_FmMacsecEventModules  module,
++                            uint8_t                 modId,
++                            e_FmIntrType            intrType)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint8_t     event= 0;
++
++    SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE);
++
++    GET_MACSEC_MODULE_EVENT(module, modId,intrType, event);
++
++    ASSERT_COND(event != e_FM_MACSEC_EV_DUMMY_LAST);
++    p_FmMacsec->intrMng[event].f_Isr = NULL;
++    p_FmMacsec->intrMng[event].h_SrcHandle = NULL;
++}
++
++t_Error FmMacsecAllocScs(t_Handle h_FmMacsec, e_ScType type, bool isPtp, uint32_t numOfScs, uint32_t *p_ScIds)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    bool        *p_ScTable;
++    uint32_t    *p_ScAvailable,i;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_ScIds, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(numOfScs, E_INVALID_HANDLE);
++
++    if (type == e_SC_RX)
++    {
++        p_ScTable       = (bool *)p_FmMacsec->rxScTable;
++        p_ScAvailable   = &p_FmMacsec->numRxScAvailable;
++        i               = (NUM_OF_RX_SC - 1);
++    }
++    else
++    {
++        p_ScTable       = (bool *)p_FmMacsec->txScTable;
++        p_ScAvailable   = &p_FmMacsec->numTxScAvailable;
++        i               = (NUM_OF_TX_SC - 1);
++
++    }
++    if (*p_ScAvailable < numOfScs)
++        RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Not enough SCs available"));
++
++    if (isPtp)
++    {
++        i = 0;
++        if (p_ScTable[i])
++            RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Sc 0 Not available"));
++    }
++
++    for (;numOfScs;i--)
++    {
++        if (p_ScTable[i])
++            continue;
++        numOfScs --;
++        (*p_ScAvailable)--;
++        p_ScIds[numOfScs] = i;
++        p_ScTable[i] = TRUE;
++    }
++
++    return err;
++}
++
++t_Error FmMacsecFreeScs(t_Handle h_FmMacsec, e_ScType type, uint32_t numOfScs, uint32_t *p_ScIds)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    bool        *p_ScTable;
++    uint32_t    *p_ScAvailable,maxNumOfSc,i;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_ScIds, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(numOfScs, E_INVALID_HANDLE);
++
++    if (type == e_SC_RX)
++    {
++        p_ScTable       = (bool *)p_FmMacsec->rxScTable;
++        p_ScAvailable   = &p_FmMacsec->numRxScAvailable;
++        maxNumOfSc      = NUM_OF_RX_SC;
++    }
++    else
++    {
++        p_ScTable       = (bool *)p_FmMacsec->txScTable;
++        p_ScAvailable   = &p_FmMacsec->numTxScAvailable;
++        maxNumOfSc      = NUM_OF_TX_SC;
++    }
++
++    if ((*p_ScAvailable + numOfScs) > maxNumOfSc)
++        RETURN_ERROR(MINOR, E_FULL, ("Too much SCs"));
++
++    for (i=0;i<numOfScs;i++)
++    {
++        p_ScTable[p_ScIds[i]] = FALSE;
++        (*p_ScAvailable)++;
++    }
++
++    return err;
++
++}
++
++t_Error FmMacsecSetPTP(t_Handle h_FmMacsec, bool enable)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    tmpReg = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++
++    tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg);
++    if (enable && (tmpReg & CFG_S0I))
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("MACSEC already in point-to-point mode"));
++
++    if (enable)
++        tmpReg |= CFG_S0I;
++    else
++        tmpReg &= ~CFG_S0I;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg, tmpReg);
++
++    return E_OK;
++}
++
++t_Error FmMacsecCreateRxSc(t_Handle h_FmMacsec, t_RxScParams *p_RxScParams)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_RxScParams, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_RxScParams->scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, p_RxScParams->scId);
++    tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsccfg);
++    if (tmpReg & RX_SCCFG_SCI_EN_MASK)
++    {
++        XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("Rx Sc %d must be disable",p_RxScParams->scId));
++    }
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsci1h, GET_SCI_FIRST_HALF(p_RxScParams->sci));
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsci2h, GET_SCI_SECOND_HALF(p_RxScParams->sci));
++    tmpReg |= ((p_RxScParams->replayProtect << RX_SCCFG_RP_SHIFT) & RX_SCCFG_RP_MASK);
++    tmpReg |= ((p_RxScParams->validateFrames << RX_SCCFG_VF_SHIFT) & RX_SCCFG_VF_MASK);
++    tmpReg |= ((p_RxScParams->confidentialityOffset << RX_SCCFG_CO_SHIFT) & RX_SCCFG_CO_MASK);
++    tmpReg |= RX_SCCFG_SCI_EN_MASK;
++    tmpReg |= (p_RxScParams->cipherSuite << RX_SCCFG_CS_SHIFT);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsccfg, tmpReg);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rpw, p_RxScParams->replayWindow);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecDeleteRxSc(t_Handle h_FmMacsec, uint32_t scId)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock);
++
++    tmpReg &= ~RX_SCCFG_SCI_EN_MASK;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsccfg, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecCreateTxSc(t_Handle h_FmMacsec, t_TxScParams *p_TxScParams)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++    bool        alwaysIncludeSCI = FALSE, useES = FALSE, useSCB = FALSE;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_TxScParams, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_TxScParams->scId < NUM_OF_TX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, p_TxScParams->scId);
++
++    tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg);
++    if (tmpReg & TX_SCCFG_SCE_MASK)
++    {
++        XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags);
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("Tx Sc %d must be disable",p_TxScParams->scId));
++    }
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsci1h, GET_SCI_FIRST_HALF(p_TxScParams->sci));
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsci2h, GET_SCI_SECOND_HALF(p_TxScParams->sci));
++    alwaysIncludeSCI = (p_TxScParams->sciInsertionMode == e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG);
++    useES            = (p_TxScParams->sciInsertionMode == e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_MAC_SA);
++
++    tmpReg |= ((p_TxScParams->protectFrames << TX_SCCFG_PF_SHIFT) & TX_SCCFG_PF_MASK);
++    tmpReg |= ((alwaysIncludeSCI << TX_SCCFG_AIS_SHIFT) & TX_SCCFG_AIS_MASK);
++    tmpReg |= ((useES << TX_SCCFG_UES_SHIFT) & TX_SCCFG_UES_MASK);
++    tmpReg |= ((useSCB << TX_SCCFG_USCB_SHIFT) & TX_SCCFG_USCB_MASK);
++    tmpReg |= ((p_TxScParams->confidentialityEnable << TX_SCCFG_CE_SHIFT) & TX_SCCFG_CE_MASK);
++    tmpReg |= ((p_TxScParams->confidentialityOffset << TX_SCCFG_CO_SHIFT) & TX_SCCFG_CO_MASK);
++    tmpReg |= TX_SCCFG_SCE_MASK;
++    tmpReg |= (p_TxScParams->cipherSuite << TX_SCCFG_CS_SHIFT);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecDeleteTxSc(t_Handle h_FmMacsec, uint32_t scId)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_TX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock);
++
++    tmpReg &= ~TX_SCCFG_SCE_MASK;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecCreateRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsanpn, DEFAULT_initNextPn);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsalpn, lowestPn);
++    Mem2IOCpy32((void*)p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsak, key, sizeof(macsecSAKey_t));
++
++    tmpReg |= RX_SACFG_ACTIVE;
++    tmpReg |= ((an << RX_SACFG_AN_SHIFT) & RX_SACFG_AN_MASK);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecCreateTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecSAKey_t key)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_TX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsanpn, DEFAULT_initNextPn);
++    Mem2IOCpy32((void*)p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsak, key, sizeof(macsecSAKey_t));
++
++    tmpReg |= TX_SACFG_ACTIVE;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsacs, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecDeleteRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, i, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsanpn, 0x0);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsalpn, 0x0);
++    for (i=0; i<4; i++)
++        WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsak[i], 0x0);
++
++    tmpReg |= RX_SACFG_ACTIVE;
++    tmpReg &= ~RX_SACFG_EN_MASK;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecDeleteTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, i, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_TX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsanpn, 0x0);
++    for (i=0; i<4; i++)
++        WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsak[i], 0x0);
++
++    tmpReg |= TX_SACFG_ACTIVE;
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsacs, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecRxSaSetReceive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, bool enableReceive)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId);
++    tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs);
++    if (enableReceive)
++        tmpReg |= RX_SACFG_EN_MASK;
++    else
++        tmpReg &= ~RX_SACFG_EN_MASK;
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecRxSaUpdateNextPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtNextPN)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsanpn, updtNextPN);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecRxSaUpdateLowestPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtLowestPN)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId);
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsalpn, updtLowestPN);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecTxSaSetActive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_TX_SC, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId);
++
++    tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg);
++
++    tmpReg |= ((an << TX_SCCFG_AN_SHIFT) & TX_SCCFG_AN_MASK);
++    tmpReg |= ((saId << TX_SCCFG_ASA_SHIFT) & TX_SCCFG_ASA_MASK);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg, tmpReg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags);
++
++    return err;
++}
++
++t_Error FmMacsecTxSaGetActive(t_Handle h_FmMacsec, uint32_t scId, macsecAN_t *p_An)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    t_Error     err = E_OK;
++    uint32_t    tmpReg = 0, intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_An, E_INVALID_HANDLE);
++
++    intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock);
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId);
++
++    tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg);
++
++    XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags);
++
++    *p_An = (macsecAN_t)((tmpReg & TX_SCCFG_AN_MASK) >> TX_SCCFG_AN_SHIFT);
++
++    return err;
++}
++
++t_Error FmMacsecSetException(t_Handle h_FmMacsec, e_FmMacsecGlobalExceptions exception, uint32_t scId, bool enable)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    bitMask;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    GET_EXCEPTION_FLAG(bitMask, exception, scId);
++    if (bitMask)
++    {
++        if (enable)
++            p_FmMacsec->exceptions |= bitMask;
++        else
++            p_FmMacsec->exceptions &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->erer, p_FmMacsec->exceptions);
++
++    return E_OK;
++}
++
++t_Error FmMacsecSetEvent(t_Handle h_FmMacsec, e_FmMacsecGlobalEvents event, uint32_t scId, bool enable)
++{
++    t_FmMacsec  *p_FmMacsec = (t_FmMacsec*)h_FmMacsec;
++    uint32_t    bitMask;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE);
++
++    GET_EVENT_FLAG(bitMask, event, scId);
++    if (bitMask)
++    {
++        if (enable)
++            p_FmMacsec->events |= bitMask;
++        else
++            p_FmMacsec->events &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined event"));
++
++    WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->ever, p_FmMacsec->events);
++
++    return E_OK;
++}
++
++/****************************************/
++/*       API Init unit functions        */
++/****************************************/
++t_Handle FM_MACSEC_MASTER_Config(t_FmMacsecParams *p_FmMacsecParam)
++{
++    t_FmMacsec  *p_FmMacsec;
++    uint32_t    macId;
++
++    /* Allocate FM MACSEC structure */
++    p_FmMacsec = (t_FmMacsec *) XX_Malloc(sizeof(t_FmMacsec));
++    if (!p_FmMacsec)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC driver structure"));
++        return NULL;
++    }
++    memset(p_FmMacsec, 0, sizeof(t_FmMacsec));
++    InitFmMacsecControllerDriver(&p_FmMacsec->fmMacsecControllerDriver);
++
++    /* Allocate the FM MACSEC driver's parameters structure */
++    p_FmMacsec->p_FmMacsecDriverParam = (t_FmMacsecDriverParam *)XX_Malloc(sizeof(t_FmMacsecDriverParam));
++    if (!p_FmMacsec->p_FmMacsecDriverParam)
++    {
++        XX_Free(p_FmMacsec);
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC driver parameters"));
++        return NULL;
++    }
++    memset(p_FmMacsec->p_FmMacsecDriverParam, 0, sizeof(t_FmMacsecDriverParam));
++
++    /* Initialize FM MACSEC parameters which will be kept by the driver */
++    p_FmMacsec->h_Fm            = p_FmMacsecParam->h_Fm;
++    p_FmMacsec->h_FmMac         = p_FmMacsecParam->nonGuestParams.h_FmMac;
++    p_FmMacsec->p_FmMacsecRegs  = (t_FmMacsecRegs *)UINT_TO_PTR(p_FmMacsecParam->nonGuestParams.baseAddr);
++    p_FmMacsec->f_Exception     = p_FmMacsecParam->nonGuestParams.f_Exception;
++    p_FmMacsec->h_App           = p_FmMacsecParam->nonGuestParams.h_App;
++    p_FmMacsec->userExceptions  = DEFAULT_userExceptions;
++    p_FmMacsec->exceptions      = DEFAULT_exceptions;
++    p_FmMacsec->events          = DEFAULT_events;
++    p_FmMacsec->rxScSpinLock    = XX_InitSpinlock();
++    p_FmMacsec->txScSpinLock    = XX_InitSpinlock();
++
++    /* Initialize FM MACSEC driver parameters parameters (for initialization phase only) */
++    p_FmMacsec->p_FmMacsecDriverParam->unknownSciTreatMode                           = DEFAULT_unknownSciFrameTreatment;
++    p_FmMacsec->p_FmMacsecDriverParam->invalidTagsDeliverUncontrolled                = DEFAULT_invalidTagsFrameTreatment;
++    p_FmMacsec->p_FmMacsecDriverParam->encryptWithNoChangedTextDiscardUncontrolled   = DEFAULT_encryptWithNoChangedTextFrameTreatment;
++    p_FmMacsec->p_FmMacsecDriverParam->untagTreatMode                                = DEFAULT_untagFrameTreatment;
++    p_FmMacsec->p_FmMacsecDriverParam->keysUnreadable                                = DEFAULT_keysUnreadable;
++    p_FmMacsec->p_FmMacsecDriverParam->reservedSc0                                   = DEFAULT_sc0ReservedForPTP;
++    p_FmMacsec->p_FmMacsecDriverParam->byPassMode                                    = !DEFAULT_normalMode;
++    p_FmMacsec->p_FmMacsecDriverParam->pnExhThr                                      = DEFAULT_pnExhThr;
++    p_FmMacsec->p_FmMacsecDriverParam->sectagOverhead                                = DEFAULT_sectagOverhead;
++    p_FmMacsec->p_FmMacsecDriverParam->mflSubtract                                   = DEFAULT_mflSubtract;
++    /* build the FM MACSEC master IPC address */
++    memset(p_FmMacsec->fmMacsecModuleName, 0, (sizeof(char))*MODULE_NAME_SIZE);
++    FM_MAC_GetId(p_FmMacsec->h_FmMac,&macId);
++    if (Sprint (p_FmMacsec->fmMacsecModuleName, "FM-%d-MAC-%d-MACSEC-Master",
++        FmGetId(p_FmMacsec->h_Fm),macId) != 24)
++    {
++        XX_Free(p_FmMacsec->p_FmMacsecDriverParam);
++        XX_Free(p_FmMacsec);
++        REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed"));
++        return NULL;
++    }
++    return p_FmMacsec;
++}
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.h
+new file mode 100644
+index 0000000..2296a0f
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.h
+@@ -0,0 +1,479 @@
++/*
++ * Copyright 2008-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          fm_macsec_master.h
++
++ @Description   FM MACSEC internal structures and definitions.
++*//***************************************************************************/
++#ifndef __FM_MACSEC_MASTER_H
++#define __FM_MACSEC_MASTER_H
++
++#include "error_ext.h"
++#include "std_ext.h"
++
++#include "fm_macsec.h"
++
++
++#define MACSEC_ICV_SIZE             16
++#define MACSEC_SECTAG_SIZE          16
++#define MACSEC_SCI_SIZE             8
++#define MACSEC_FCS_SIZE             4
++
++/**************************************************************************//**
++ @Description       Exceptions
++*//***************************************************************************/
++
++#define FM_MACSEC_EX_TX_SC_0       0x80000000
++#define FM_MACSEC_EX_TX_SC(sc)     (FM_MACSEC_EX_TX_SC_0 >> (sc))
++#define FM_MACSEC_EX_ECC           0x00000001
++
++#define GET_EXCEPTION_FLAG(bitMask, exception, id)  switch (exception){     \
++    case e_FM_MACSEC_EX_TX_SC:                                              \
++        bitMask = FM_MACSEC_EX_TX_SC(id); break;                            \
++    case e_FM_MACSEC_EX_ECC:                                                \
++        bitMask = FM_MACSEC_EX_ECC; break;                                  \
++    default: bitMask = 0;break;}
++
++#define FM_MACSEC_USER_EX_SINGLE_BIT_ECC            0x80000000
++#define FM_MACSEC_USER_EX_MULTI_BIT_ECC             0x40000000
++
++#define GET_USER_EXCEPTION_FLAG(bitMask, exception)     switch (exception){ \
++    case e_FM_MACSEC_EX_SINGLE_BIT_ECC:                                     \
++        bitMask = FM_MACSEC_USER_EX_SINGLE_BIT_ECC; break;                  \
++    case e_FM_MACSEC_EX_MULTI_BIT_ECC:                                      \
++        bitMask = FM_MACSEC_USER_EX_MULTI_BIT_ECC; break;                   \
++    default: bitMask = 0;break;}
++
++/**************************************************************************//**
++ @Description       Events
++*//***************************************************************************/
++
++#define FM_MACSEC_EV_TX_SC_0_NEXT_PN                  0x80000000
++#define FM_MACSEC_EV_TX_SC_NEXT_PN(sc)                (FM_MACSEC_EV_TX_SC_0_NEXT_PN >> (sc))
++
++#define GET_EVENT_FLAG(bitMask, event, id)      switch (event){     \
++    case e_FM_MACSEC_EV_TX_SC_NEXT_PN:                              \
++        bitMask = FM_MACSEC_EV_TX_SC_NEXT_PN(id); break;            \
++    default: bitMask = 0;break;}
++
++/**************************************************************************//**
++ @Description       Defaults
++*//***************************************************************************/
++#define DEFAULT_userExceptions              (FM_MACSEC_USER_EX_SINGLE_BIT_ECC     |\
++                                            FM_MACSEC_USER_EX_MULTI_BIT_ECC)
++
++#define DEFAULT_exceptions                  (FM_MACSEC_EX_TX_SC(0)     |\
++                                            FM_MACSEC_EX_TX_SC(1)      |\
++                                            FM_MACSEC_EX_TX_SC(2)      |\
++                                            FM_MACSEC_EX_TX_SC(3)      |\
++                                            FM_MACSEC_EX_TX_SC(4)      |\
++                                            FM_MACSEC_EX_TX_SC(5)      |\
++                                            FM_MACSEC_EX_TX_SC(6)      |\
++                                            FM_MACSEC_EX_TX_SC(7)      |\
++                                            FM_MACSEC_EX_TX_SC(8)      |\
++                                            FM_MACSEC_EX_TX_SC(9)      |\
++                                            FM_MACSEC_EX_TX_SC(10)     |\
++                                            FM_MACSEC_EX_TX_SC(11)     |\
++                                            FM_MACSEC_EX_TX_SC(12)     |\
++                                            FM_MACSEC_EX_TX_SC(13)     |\
++                                            FM_MACSEC_EX_TX_SC(14)     |\
++                                            FM_MACSEC_EX_TX_SC(15)     |\
++                                            FM_MACSEC_EX_ECC          )
++
++#define DEFAULT_events                      (FM_MACSEC_EV_TX_SC_NEXT_PN(0)   |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(1)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(2)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(3)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(4)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(5)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(6)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(7)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(8)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(9)    |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(10)   |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(11)   |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(12)   |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(13)   |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(14)   |\
++                                            FM_MACSEC_EV_TX_SC_NEXT_PN(15)   )
++
++#define DEFAULT_unknownSciFrameTreatment                e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_BOTH
++#define DEFAULT_invalidTagsFrameTreatment               FALSE
++#define DEFAULT_encryptWithNoChangedTextFrameTreatment  FALSE
++#define DEFAULT_untagFrameTreatment                     e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED
++#define DEFAULT_changedTextWithNoEncryptFrameTreatment  FALSE
++#define DEFAULT_onlyScbIsSetFrameTreatment              FALSE
++#define DEFAULT_keysUnreadable                          FALSE
++#define DEFAULT_normalMode                              TRUE
++#define DEFAULT_sc0ReservedForPTP                       FALSE
++#define DEFAULT_initNextPn                              1
++#define DEFAULT_pnExhThr                                0xffffffff
++#define DEFAULT_sectagOverhead                          (MACSEC_ICV_SIZE + MACSEC_SECTAG_SIZE)
++#define DEFAULT_mflSubtract                             MACSEC_FCS_SIZE
++
++
++/**************************************************************************//**
++ @Description       Memory Mapped Registers
++*//***************************************************************************/
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(push,1)
++#endif /* defined(__MWERKS__) && ... */
++
++typedef _Packed struct
++{
++    /* MACsec configuration */
++    volatile uint32_t   cfg;            /**< MACsec configuration */
++    volatile uint32_t   et;             /**< MACsec EtherType */
++    volatile uint8_t    res1[56];       /**< reserved */
++    volatile uint32_t   mfl;            /**< Maximum Frame Length */
++    volatile uint32_t   tpnet;          /**< TX Packet Number exhaustion threshold */
++    volatile uint8_t    res2[56];       /**< reserved */
++    volatile uint32_t   rxsca;          /**< RX SC access select */
++    volatile uint8_t    res3[60];       /**< reserved */
++    volatile uint32_t   txsca;          /**< TX SC access select */
++    volatile uint8_t    res4[60];       /**< reserved */
++
++    /* RX configuration, status and statistic */
++    volatile uint32_t   rxsci1h;        /**< RX Secure Channel Identifier first half */
++    volatile uint32_t   rxsci2h;        /**< RX Secure Channel Identifier second half */
++    volatile uint8_t    res5[8];        /**< reserved */
++    volatile uint32_t   ifio1hs;        /**< ifInOctets first half Statistic */
++    volatile uint32_t   ifio2hs;        /**< ifInOctets second half Statistic */
++    volatile uint32_t   ifiups;         /**< ifInUcastPkts Statistic */
++    volatile uint8_t    res6[4];        /**< reserved */
++    volatile uint32_t   ifimps;         /**< ifInMulticastPkts Statistic */
++    volatile uint32_t   ifibps;         /**< ifInBroadcastPkts Statistic */
++    volatile uint32_t   rxsccfg;        /**< RX Secure Channel configuration */
++    volatile uint32_t   rpw;            /**< replayWindow */
++    volatile uint8_t    res7[16];       /**< reserved */
++    volatile uint32_t   inov1hs;        /**< InOctetsValidated first half Statistic */
++    volatile uint32_t   inov2hs;        /**< InOctetsValidated second half Statistic */
++    volatile uint32_t   inod1hs;        /**< InOctetsDecrypted first half Statistic */
++    volatile uint32_t   inod2hs;        /**< InOctetsDecrypted second half Statistic */
++    volatile uint32_t   rxscipus;       /**< RX Secure Channel InPktsUnchecked Statistic */
++    volatile uint32_t   rxscipds;       /**< RX Secure Channel InPktsDelayed Statistic */
++    volatile uint32_t   rxscipls;       /**< RX Secure Channel InPktsLate Statistic */
++    volatile uint8_t    res8[4];        /**< reserved */
++    volatile uint32_t   rxaninuss[MAX_NUM_OF_SA_PER_SC];   /**< RX AN 0-3 InNotUsingSA Statistic */
++    volatile uint32_t   rxanipuss[MAX_NUM_OF_SA_PER_SC];   /**< RX AN 0-3 InPktsUnusedSA Statistic */
++    _Packed struct
++    {
++        volatile uint32_t   rxsacs;     /**< RX Security Association configuration and status */
++        volatile uint32_t   rxsanpn;    /**< RX Security Association nextPN */
++        volatile uint32_t   rxsalpn;    /**< RX Security Association lowestPN */
++        volatile uint32_t   rxsaipos;   /**< RX Security Association InPktsOK Statistic */
++        volatile uint32_t   rxsak[4];   /**< RX Security Association key (128 bit) */
++        volatile uint32_t   rxsah[4];   /**< RX Security Association hash (128 bit) */
++        volatile uint32_t   rxsaipis;   /**< RX Security Association InPktsInvalid Statistic */
++        volatile uint32_t   rxsaipnvs;  /**< RX Security Association InPktsNotValid Statistic */
++        volatile uint8_t    res9[8];    /**< reserved */
++    } _PackedType fmMacsecRxScSa[NUM_OF_SA_PER_RX_SC];
++
++    /* TX configuration, status and statistic */
++    volatile uint32_t   txsci1h;        /**< TX Secure Channel Identifier first half */
++    volatile uint32_t   txsci2h;        /**< TX Secure Channel Identifier second half */
++    volatile uint8_t    res10[8];        /**< reserved */
++    volatile uint32_t   ifoo1hs;        /**< ifOutOctets first half Statistic */
++    volatile uint32_t   ifoo2hs;        /**< ifOutOctets second half Statistic */
++    volatile uint32_t   ifoups;         /**< ifOutUcastPkts Statistic */
++    volatile uint32_t   opus;           /**< OutPktsUntagged Statistic */
++    volatile uint32_t   ifomps;         /**< ifOutMulticastPkts Statistic */
++    volatile uint32_t   ifobps;         /**< ifOutBroadcastPkts Statistic */
++    volatile uint32_t   txsccfg;        /**< TX Secure Channel configuration */
++    volatile uint32_t   optls;          /**< OutPktsTooLong Statistic */
++    volatile uint8_t    res11[16];      /**< reserved */
++    volatile uint32_t   oop1hs;         /**< OutOctetsProtected first half Statistic */
++    volatile uint32_t   oop2hs;         /**< OutOctetsProtected second half Statistic */
++    volatile uint32_t   ooe1hs;         /**< OutOctetsEncrypted first half Statistic */
++    volatile uint32_t   ooe2hs;         /**< OutOctetsEncrypted second half Statistic */
++    volatile uint8_t    res12[48];      /**< reserved */
++    _Packed struct
++    {
++        volatile uint32_t   txsacs;     /**< TX Security Association configuration and status */
++        volatile uint32_t   txsanpn;    /**< TX Security Association nextPN */
++        volatile uint32_t   txsaopps;   /**< TX Security Association OutPktsProtected Statistic */
++        volatile uint32_t   txsaopes;   /**< TX Security Association OutPktsEncrypted Statistic */
++        volatile uint32_t   txsak[4];   /**< TX Security Association key (128 bit) */
++        volatile uint32_t   txsah[4];   /**< TX Security Association hash (128 bit) */
++        volatile uint8_t    res13[16];  /**< reserved */
++    } _PackedType fmMacsecTxScSa[NUM_OF_SA_PER_TX_SC];
++    volatile uint8_t    res14[248];     /**< reserved */
++
++    /* Global configuration and status */
++    volatile uint32_t   ip_rev1;        /**< MACsec IP Block Revision 1 register */
++    volatile uint32_t   ip_rev2;        /**< MACsec IP Block Revision 2 register */
++    volatile uint32_t   evr;            /**< MACsec Event Register */
++    volatile uint32_t   ever;           /**< MACsec Event Enable Register */
++    volatile uint32_t   evfr;           /**< MACsec Event Force Register */
++    volatile uint32_t   err;            /**< MACsec Error Register */
++    volatile uint32_t   erer;           /**< MACsec Error Enable Register */
++    volatile uint32_t   erfr;           /**< MACsec Error Force Register */
++    volatile uint8_t    res15[40];      /**< reserved */
++    volatile uint32_t   meec;           /**< MACsec Memory ECC Error Capture Register */
++    volatile uint32_t   idle;           /**< MACsec Idle status Register */
++    volatile uint8_t    res16[184];     /**< reserved */
++    /* DEBUG */
++    volatile uint32_t   rxec;           /**< MACsec RX error capture Register */
++    volatile uint8_t    res17[28];      /**< reserved */
++    volatile uint32_t   txec;           /**< MACsec TX error capture Register */
++    volatile uint8_t    res18[220];     /**< reserved */
++
++    /* Macsec Rx global statistic */
++    volatile uint32_t   ifiocp1hs;      /**< ifInOctetsCp first half Statistic */
++    volatile uint32_t   ifiocp2hs;      /**< ifInOctetsCp second half Statistic */
++    volatile uint32_t   ifiupcps;       /**< ifInUcastPktsCp Statistic */
++    volatile uint8_t    res19[4];       /**< reserved */
++    volatile uint32_t   ifioup1hs;      /**< ifInOctetsUp first half Statistic */
++    volatile uint32_t   ifioup2hs;      /**< ifInOctetsUp second half Statistic */
++    volatile uint32_t   ifiupups;       /**< ifInUcastPktsUp Statistic */
++    volatile uint8_t    res20[4];       /**< reserved */
++    volatile uint32_t   ifimpcps;       /**< ifInMulticastPktsCp Statistic */
++    volatile uint32_t   ifibpcps;       /**< ifInBroadcastPktsCp Statistic */
++    volatile uint32_t   ifimpups;       /**< ifInMulticastPktsUp Statistic */
++    volatile uint32_t   ifibpups;       /**< ifInBroadcastPktsUp Statistic */
++    volatile uint32_t   ipwts;          /**< InPktsWithoutTag Statistic */
++    volatile uint32_t   ipkays;         /**< InPktsKaY Statistic */
++    volatile uint32_t   ipbts;          /**< InPktsBadTag Statistic */
++    volatile uint32_t   ipsnfs;         /**< InPktsSCINotFound Statistic */
++    volatile uint32_t   ipuecs;         /**< InPktsUnsupportedEC Statistic */
++    volatile uint32_t   ipescbs;        /**< InPktsEponSingleCopyBroadcast Statistic */
++    volatile uint32_t   iptls;          /**< InPktsTooLong Statistic */
++    volatile uint8_t    res21[52];      /**< reserved */
++
++    /* Macsec Tx global statistic */
++    volatile uint32_t   opds;           /**< OutPktsDiscarded Statistic */
++#if (DPAA_VERSION >= 11)
++    volatile uint8_t    res22[124];     /**< reserved */
++    _Packed struct
++    {
++        volatile uint32_t   rxsak[8];   /**< RX Security Association key (128/256 bit) */
++        volatile uint8_t    res23[32];  /**< reserved */
++    } _PackedType rxScSaKey[NUM_OF_SA_PER_RX_SC];
++    _Packed struct
++    {
++        volatile uint32_t   txsak[8];   /**< TX Security Association key (128/256 bit) */
++        volatile uint8_t    res24[32];  /**< reserved */
++    } _PackedType txScSaKey[NUM_OF_SA_PER_TX_SC];
++#endif /* (DPAA_VERSION >= 11) */
++} _PackedType t_FmMacsecRegs;
++
++#if defined(__MWERKS__) && !defined(__GNUC__)
++#pragma pack(pop)
++#endif /* defined(__MWERKS__) && ... */
++
++
++/**************************************************************************//**
++ @Description       General defines
++*//***************************************************************************/
++
++#define SCI_HIGH_MASK   0xffffffff00000000LL
++#define SCI_LOW_MASK    0x00000000ffffffffLL
++
++#define LONG_SHIFT      32
++
++#define GET_SCI_FIRST_HALF(sci)     (uint32_t)((macsecSCI_t)((macsecSCI_t)(sci) & SCI_HIGH_MASK) >> LONG_SHIFT)
++#define GET_SCI_SECOND_HALF(sci)    (uint32_t)((macsecSCI_t)(sci) & SCI_LOW_MASK)
++
++/**************************************************************************//**
++ @Description       Configuration defines
++*//***************************************************************************/
++
++/* masks */
++#define CFG_UECT                        0x00000800
++#define CFG_ESCBT                       0x00000400
++#define CFG_USFT                        0x00000300
++#define CFG_ITT                         0x00000080
++#define CFG_KFT                         0x00000040
++#define CFG_UFT                         0x00000030
++#define CFG_KSS                         0x00000004
++#define CFG_BYPN                        0x00000002
++#define CFG_S0I                         0x00000001
++
++#define ET_TYPE                         0x0000ffff
++
++#define MFL_MAX_LEN                     0x0000ffff
++
++#define RXSCA_SC_SEL                    0x0000000f
++
++#define TXSCA_SC_SEL                    0x0000000f
++
++#define IP_REV_1_IP_ID                  0xffff0000
++#define IP_REV_1_IP_MJ                  0x0000ff00
++#define IP_REV_1_IP_MM                  0x000000ff
++
++#define IP_REV_2_IP_INT                 0x00ff0000
++#define IP_REV_2_IP_ERR                 0x0000ff00
++#define IP_REV_2_IP_CFG                 0x000000ff
++
++#define MECC_CAP                        0x80000000
++#define MECC_CET                        0x40000000
++#define MECC_SERCNT                     0x00ff0000
++#define MECC_MEMADDR                    0x000001ff
++
++/* shifts */
++#define CFG_UECT_SHIFT                  (31-20)
++#define CFG_ESCBT_SHIFT                 (31-21)
++#define CFG_USFT_SHIFT                  (31-23)
++#define CFG_ITT_SHIFT                   (31-24)
++#define CFG_KFT_SHIFT                   (31-25)
++#define CFG_UFT_SHIFT                   (31-27)
++#define CFG_KSS_SHIFT                   (31-29)
++#define CFG_BYPN_SHIFT                  (31-30)
++#define CFG_S0I_SHIFT                   (31-31)
++
++#define IP_REV_1_IP_ID_SHIFT            (31-15)
++#define IP_REV_1_IP_MJ_SHIFT            (31-23)
++#define IP_REV_1_IP_MM_SHIFT            (31-31)
++
++#define IP_REV_2_IP_INT_SHIFT           (31-15)
++#define IP_REV_2_IP_ERR_SHIFT           (31-23)
++#define IP_REV_2_IP_CFG_SHIFT           (31-31)
++
++#define MECC_CAP_SHIFT                  (31-0)
++#define MECC_CET_SHIFT                  (31-1)
++#define MECC_SERCNT_SHIFT               (31-15)
++#define MECC_MEMADDR_SHIFT              (31-31)
++
++/**************************************************************************//**
++ @Description       RX SC defines
++*//***************************************************************************/
++
++/* masks */
++#define RX_SCCFG_SCI_EN_MASK            0x00000800
++#define RX_SCCFG_RP_MASK                0x00000400
++#define RX_SCCFG_VF_MASK                0x00000300
++#define RX_SCCFG_CO_MASK                0x0000003f
++
++/* shifts */
++#define RX_SCCFG_SCI_EN_SHIFT           (31-20)
++#define RX_SCCFG_RP_SHIFT               (31-21)
++#define RX_SCCFG_VF_SHIFT               (31-23)
++#define RX_SCCFG_CO_SHIFT               (31-31)
++#define RX_SCCFG_CS_SHIFT               (31-7)
++
++/**************************************************************************//**
++ @Description       RX SA defines
++*//***************************************************************************/
++
++/* masks */
++#define RX_SACFG_ACTIVE                 0x80000000
++#define RX_SACFG_AN_MASK                0x00000006
++#define RX_SACFG_EN_MASK                0x00000001
++
++/* shifts */
++#define RX_SACFG_AN_SHIFT               (31-30)
++#define RX_SACFG_EN_SHIFT               (31-31)
++
++/**************************************************************************//**
++ @Description       TX SC defines
++*//***************************************************************************/
++
++/* masks */
++#define TX_SCCFG_AN_MASK                0x000c0000
++#define TX_SCCFG_ASA_MASK               0x00020000
++#define TX_SCCFG_SCE_MASK               0x00010000
++#define TX_SCCFG_CO_MASK                0x00003f00
++#define TX_SCCFG_CE_MASK                0x00000010
++#define TX_SCCFG_PF_MASK                0x00000008
++#define TX_SCCFG_AIS_MASK               0x00000004
++#define TX_SCCFG_UES_MASK               0x00000002
++#define TX_SCCFG_USCB_MASK              0x00000001
++
++/* shifts */
++#define TX_SCCFG_AN_SHIFT               (31-13)
++#define TX_SCCFG_ASA_SHIFT              (31-14)
++#define TX_SCCFG_SCE_SHIFT              (31-15)
++#define TX_SCCFG_CO_SHIFT               (31-23)
++#define TX_SCCFG_CE_SHIFT               (31-27)
++#define TX_SCCFG_PF_SHIFT               (31-28)
++#define TX_SCCFG_AIS_SHIFT              (31-29)
++#define TX_SCCFG_UES_SHIFT              (31-30)
++#define TX_SCCFG_USCB_SHIFT             (31-31)
++#define TX_SCCFG_CS_SHIFT               (31-7)
++
++/**************************************************************************//**
++ @Description       TX SA defines
++*//***************************************************************************/
++
++/* masks */
++#define TX_SACFG_ACTIVE                 0x80000000
++
++
++typedef struct
++{
++    void        (*f_Isr) (t_Handle h_Arg, uint32_t id);
++    t_Handle    h_SrcHandle;
++} t_FmMacsecIntrSrc;
++
++typedef struct
++{
++    e_FmMacsecUnknownSciFrameTreatment  unknownSciTreatMode;
++    bool                                invalidTagsDeliverUncontrolled;
++    bool                                changedTextWithNoEncryptDeliverUncontrolled;
++    bool                                onlyScbIsSetDeliverUncontrolled;
++    bool                                encryptWithNoChangedTextDiscardUncontrolled;
++    e_FmMacsecUntagFrameTreatment       untagTreatMode;
++    uint32_t                            pnExhThr;
++    bool                                keysUnreadable;
++    bool                                byPassMode;
++    bool                                reservedSc0;
++    uint32_t                            sectagOverhead;
++    uint32_t                            mflSubtract;
++} t_FmMacsecDriverParam;
++
++typedef struct
++{
++    t_FmMacsecControllerDriver      fmMacsecControllerDriver;
++    t_Handle                        h_Fm;
++    t_FmMacsecRegs                  *p_FmMacsecRegs;
++    t_Handle                        h_FmMac;            /**< A handle to the FM MAC object  related to */
++    char                            fmMacsecModuleName[MODULE_NAME_SIZE];
++    t_FmMacsecIntrSrc               intrMng[NUM_OF_INTER_MODULE_EVENTS];
++    uint32_t                        events;
++    uint32_t                        exceptions;
++    uint32_t                        userExceptions;
++    t_FmMacsecExceptionsCallback    *f_Exception;       /**< Exception Callback Routine         */
++    t_Handle                        h_App;              /**< A handle to an application layer object; This handle will
++                                                             be passed by the driver upon calling the above callbacks */
++    bool                            rxScTable[NUM_OF_RX_SC];
++    uint32_t                        numRxScAvailable;
++    bool                            txScTable[NUM_OF_TX_SC];
++    uint32_t                        numTxScAvailable;
++    t_Handle                        rxScSpinLock;
++    t_Handle                        txScSpinLock;
++    t_FmMacsecDriverParam           *p_FmMacsecDriverParam;
++} t_FmMacsec;
++
++
++#endif /* __FM_MACSEC_MASTER_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.c
+new file mode 100644
+index 0000000..7c72dc9
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.c
+@@ -0,0 +1,883 @@
++/*
++ * Copyright 2008-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          fm_macsec_secy.c
++
++ @Description   FM MACSEC SECY driver routines implementation.
++*//***************************************************************************/
++
++#include "std_ext.h"
++#include "error_ext.h"
++#include "xx_ext.h"
++#include "string_ext.h"
++#include "sprint_ext.h"
++
++#include "fm_macsec_secy.h"
++
++
++/****************************************/
++/*       static functions               */
++/****************************************/
++static void FmMacsecSecYExceptionsIsr(t_Handle h_FmMacsecSecY, uint32_t id)
++{
++    t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    UNUSED(id);
++    SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE);
++
++    if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
++        p_FmMacsecSecY->f_Exception(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EX_FRAME_DISCARDED);
++}
++
++static void FmMacsecSecYEventsIsr(t_Handle h_FmMacsecSecY, uint32_t id)
++{
++    t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    UNUSED(id);
++    SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE);
++
++    if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
++        p_FmMacsecSecY->f_Event(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EV_NEXT_PN);
++}
++
++static t_Error CheckFmMacsecSecYParameters(t_FmMacsecSecY *p_FmMacsecSecY)
++{
++    if (!p_FmMacsecSecY->f_Exception)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided"));
++
++    if (!p_FmMacsecSecY->f_Event)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Events callback not provided"));
++
++    if (!p_FmMacsecSecY->numOfRxSc)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Num of Rx Scs must be greater than '0'"));
++
++
++    return E_OK;
++}
++
++static t_Handle FmMacsecSecYCreateSc(t_FmMacsecSecY             *p_FmMacsecSecY,
++                                     macsecSCI_t                sci,
++                                     e_FmMacsecSecYCipherSuite  cipherSuite,
++                                     e_ScType                   type)
++{
++    t_SecYSc        *p_ScTable;
++    void            *p_Params;
++    uint32_t        numOfSc,i;
++    t_Error         err = E_OK;
++    t_RxScParams    rxScParams;
++    t_TxScParams    txScParams;
++
++    ASSERT_COND(p_FmMacsecSecY);
++    ASSERT_COND(p_FmMacsecSecY->h_FmMacsec);
++
++    if (type == e_SC_RX)
++    {
++        memset(&rxScParams, 0, sizeof(rxScParams));
++        i                                   = (NUM_OF_RX_SC - 1);
++        p_ScTable                           = p_FmMacsecSecY->p_RxSc;
++        numOfSc                             = p_FmMacsecSecY->numOfRxSc;
++        rxScParams.confidentialityOffset    = p_FmMacsecSecY->confidentialityOffset;
++        rxScParams.replayProtect            = p_FmMacsecSecY->replayProtect;
++        rxScParams.replayWindow             = p_FmMacsecSecY->replayWindow;
++        rxScParams.validateFrames           = p_FmMacsecSecY->validateFrames;
++        rxScParams.cipherSuite              = cipherSuite;
++        p_Params = &rxScParams;
++    }
++    else
++    {
++        memset(&txScParams, 0, sizeof(txScParams));
++        i                                   = (NUM_OF_TX_SC - 1);
++        p_ScTable                           = p_FmMacsecSecY->p_TxSc;
++        numOfSc                             = p_FmMacsecSecY->numOfTxSc;
++        txScParams.sciInsertionMode         = p_FmMacsecSecY->sciInsertionMode;
++        txScParams.protectFrames            = p_FmMacsecSecY->protectFrames;
++        txScParams.confidentialityEnable    = p_FmMacsecSecY->confidentialityEnable;
++        txScParams.confidentialityOffset    = p_FmMacsecSecY->confidentialityOffset;
++        txScParams.cipherSuite              = cipherSuite;
++        p_Params = &txScParams;
++    }
++
++    for (i=0;i<numOfSc;i++)
++        if (!p_ScTable[i].inUse)
++            break;
++    if (i == numOfSc)
++    {
++        REPORT_ERROR(MAJOR, E_FULL, ("FM MACSEC SECY SC"));
++        return NULL;
++    }
++
++    if (type == e_SC_RX)
++    {
++        ((t_RxScParams *)p_Params)->scId = p_ScTable[i].scId;
++        ((t_RxScParams *)p_Params)->sci  = sci;
++        if ((err = FmMacsecCreateRxSc(p_FmMacsecSecY->h_FmMacsec, (t_RxScParams *)p_Params)) != E_OK)
++        {
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC"));
++            return NULL;
++        }
++    }
++    else
++    {
++        ((t_TxScParams *)p_Params)->scId = p_ScTable[i].scId;
++        ((t_TxScParams *)p_Params)->sci  = sci;
++        if ((err = FmMacsecCreateTxSc(p_FmMacsecSecY->h_FmMacsec, (t_TxScParams *)p_Params)) != E_OK)
++        {
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC"));
++            return NULL;
++        }
++    }
++
++    p_ScTable[i].inUse = TRUE;
++    return &p_ScTable[i];
++}
++
++static t_Error FmMacsecSecYDeleteSc(t_FmMacsecSecY *p_FmMacsecSecY, t_SecYSc *p_FmSecYSc, e_ScType type)
++{
++    t_Error         err = E_OK;
++
++    ASSERT_COND(p_FmMacsecSecY);
++    ASSERT_COND(p_FmMacsecSecY->h_FmMacsec);
++    ASSERT_COND(p_FmSecYSc);
++
++    if (type == e_SC_RX)
++    {
++        if ((err = FmMacsecDeleteRxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK)
++            RETURN_ERROR(MINOR, err, NO_MSG);
++    }
++    else
++        if ((err = FmMacsecDeleteTxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK)
++            RETURN_ERROR(MINOR, err, NO_MSG);
++
++    p_FmSecYSc->inUse = FALSE;
++
++    return err;
++}
++
++/****************************************/
++/*       API Init unit functions        */
++/****************************************/
++t_Handle FM_MACSEC_SECY_Config(t_FmMacsecSecYParams *p_FmMacsecSecYParam)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY;
++
++    /* Allocate FM MACSEC structure */
++    p_FmMacsecSecY = (t_FmMacsecSecY *) XX_Malloc(sizeof(t_FmMacsecSecY));
++    if (!p_FmMacsecSecY)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver structure"));
++        return NULL;
++    }
++    memset(p_FmMacsecSecY, 0, sizeof(t_FmMacsecSecY));
++
++    /* Allocate the FM MACSEC driver's parameters structure */
++    p_FmMacsecSecY->p_FmMacsecSecYDriverParam = (t_FmMacsecSecYDriverParam *)XX_Malloc(sizeof(t_FmMacsecSecYDriverParam));
++    if (!p_FmMacsecSecY->p_FmMacsecSecYDriverParam)
++    {
++        XX_Free(p_FmMacsecSecY);
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver parameters"));
++        return NULL;
++    }
++    memset(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, 0, sizeof(t_FmMacsecSecYDriverParam));
++
++    /* Initialize FM MACSEC SECY parameters which will be kept by the driver */
++    p_FmMacsecSecY->h_FmMacsec              = p_FmMacsecSecYParam->h_FmMacsec;
++    p_FmMacsecSecY->f_Event                 = p_FmMacsecSecYParam->f_Event;
++    p_FmMacsecSecY->f_Exception             = p_FmMacsecSecYParam->f_Exception;
++    p_FmMacsecSecY->h_App                   = p_FmMacsecSecYParam->h_App;
++    p_FmMacsecSecY->confidentialityEnable   = DEFAULT_confidentialityEnable;
++    p_FmMacsecSecY->confidentialityOffset   = DEFAULT_confidentialityOffset;
++    p_FmMacsecSecY->validateFrames          = DEFAULT_validateFrames;
++    p_FmMacsecSecY->replayProtect           = DEFAULT_replayEnable;
++    p_FmMacsecSecY->replayWindow            = DEFAULT_replayWindow;
++    p_FmMacsecSecY->protectFrames           = DEFAULT_protectFrames;
++    p_FmMacsecSecY->sciInsertionMode        = DEFAULT_sciInsertionMode;
++    p_FmMacsecSecY->isPointToPoint          = DEFAULT_ptp;
++    p_FmMacsecSecY->numOfRxSc               = p_FmMacsecSecYParam->numReceiveChannels;
++    p_FmMacsecSecY->numOfTxSc               = DEFAULT_numOfTxSc;
++    p_FmMacsecSecY->exceptions              = DEFAULT_exceptions;
++    p_FmMacsecSecY->events                  = DEFAULT_events;
++
++    memcpy(&p_FmMacsecSecY->p_FmMacsecSecYDriverParam->txScParams,
++           &p_FmMacsecSecYParam->txScParams,
++           sizeof(t_FmMacsecSecYSCParams));
++    return p_FmMacsecSecY;
++}
++
++t_Error FM_MACSEC_SECY_Init(t_Handle h_FmMacsecSecY)
++{
++    t_FmMacsecSecY              *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_FmMacsecSecYDriverParam   *p_FmMacsecSecYDriverParam = NULL;
++    uint32_t                    rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i, j;
++    t_Error                     err;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_HANDLE);
++
++    CHECK_INIT_PARAMETERS(p_FmMacsecSecY, CheckFmMacsecSecYParameters);
++
++    p_FmMacsecSecYDriverParam = p_FmMacsecSecY->p_FmMacsecSecYDriverParam;
++
++    if ((p_FmMacsecSecY->isPointToPoint) &&
++        ((err = FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, TRUE)) != E_OK))
++        RETURN_ERROR(MAJOR, err, ("Can't set Poin-to-Point"));
++
++    /* Rx Sc Allocation */
++    p_FmMacsecSecY->p_RxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc);
++    if (!p_FmMacsecSecY->p_RxSc)
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC"));
++    memset(p_FmMacsecSecY->p_RxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc);
++    if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK)
++    {
++        if (p_FmMacsecSecY->p_TxSc)
++            XX_Free(p_FmMacsecSecY->p_TxSc);
++        if (p_FmMacsecSecY->p_RxSc)
++            XX_Free(p_FmMacsecSecY->p_RxSc);
++        return ERROR_CODE(err);
++    }
++    for (i=0; i<p_FmMacsecSecY->numOfRxSc; i++)
++    {
++        p_FmMacsecSecY->p_RxSc[i].scId  = rxScIds[i];
++        p_FmMacsecSecY->p_RxSc[i].type  = e_SC_RX;
++        for (j=0; j<MAX_NUM_OF_SA_PER_SC;j++)
++            p_FmMacsecSecY->p_RxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
++    }
++
++    /* Tx Sc Allocation */
++    p_FmMacsecSecY->p_TxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc);
++    if (!p_FmMacsecSecY->p_TxSc)
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC"));
++    memset(p_FmMacsecSecY->p_TxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc);
++
++    if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK)
++    {
++        if (p_FmMacsecSecY->p_TxSc)
++            XX_Free(p_FmMacsecSecY->p_TxSc);
++        if (p_FmMacsecSecY->p_RxSc)
++            XX_Free(p_FmMacsecSecY->p_RxSc);
++        return ERROR_CODE(err);
++    }
++    for (i=0; i<p_FmMacsecSecY->numOfTxSc; i++)
++    {
++        p_FmMacsecSecY->p_TxSc[i].scId  = txScIds[i];
++        p_FmMacsecSecY->p_TxSc[i].type  = e_SC_TX;
++        for (j=0; j<MAX_NUM_OF_SA_PER_SC;j++)
++            p_FmMacsecSecY->p_TxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
++        FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec,
++                             e_FM_MACSEC_MOD_SC_TX,
++                             (uint8_t)txScIds[i],
++                             e_FM_INTR_TYPE_ERR,
++                             FmMacsecSecYExceptionsIsr,
++                             p_FmMacsecSecY);
++        FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec,
++                             e_FM_MACSEC_MOD_SC_TX,
++                             (uint8_t)txScIds[i],
++                             e_FM_INTR_TYPE_NORMAL,
++                             FmMacsecSecYEventsIsr,
++                             p_FmMacsecSecY);
++
++        if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
++            FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], TRUE);
++        if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
++            FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], TRUE);
++    }
++
++    FmMacsecSecYCreateSc(p_FmMacsecSecY,
++                         p_FmMacsecSecYDriverParam->txScParams.sci,
++                         p_FmMacsecSecYDriverParam->txScParams.cipherSuite,
++                         e_SC_TX);
++    XX_Free(p_FmMacsecSecYDriverParam);
++    p_FmMacsecSecY->p_FmMacsecSecYDriverParam = NULL;
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_Free(t_Handle h_FmMacsecSecY)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_Error         err             = E_OK;
++    uint32_t        rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    if (p_FmMacsecSecY->isPointToPoint)
++        FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, FALSE);
++    if (p_FmMacsecSecY->p_RxSc)
++    {
++        for (i=0; i<p_FmMacsecSecY->numOfRxSc; i++)
++            rxScIds[i] = p_FmMacsecSecY->p_RxSc[i].scId;
++        if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK)
++            return ERROR_CODE(err);
++        XX_Free(p_FmMacsecSecY->p_RxSc);
++    }
++    if (p_FmMacsecSecY->p_TxSc)
++    {
++       FmMacsecSecYDeleteSc(p_FmMacsecSecY, &p_FmMacsecSecY->p_TxSc[0], e_SC_TX);
++
++       for (i=0; i<p_FmMacsecSecY->numOfTxSc; i++) {
++             txScIds[i] = p_FmMacsecSecY->p_TxSc[i].scId;
++            FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec,
++                                 e_FM_MACSEC_MOD_SC_TX,
++                                 (uint8_t)txScIds[i],
++                                 e_FM_INTR_TYPE_ERR);
++            FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec,
++                                 e_FM_MACSEC_MOD_SC_TX,
++                                 (uint8_t)txScIds[i],
++                                 e_FM_INTR_TYPE_NORMAL);
++
++            if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
++                FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], FALSE);
++            if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
++                FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], FALSE);
++       }
++
++        if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK)
++            return ERROR_CODE(err);
++        XX_Free(p_FmMacsecSecY->p_TxSc);
++    }
++
++    XX_Free(p_FmMacsecSecY);
++
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_ConfigSciInsertionMode(t_Handle h_FmMacsecSecY, e_FmMacsecSciInsertionMode sciInsertionMode)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    p_FmMacsecSecY->sciInsertionMode = sciInsertionMode;
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_ConfigProtectFrames(t_Handle h_FmMacsecSecY, bool protectFrames)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    p_FmMacsecSecY->protectFrames = protectFrames;
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_ConfigReplayWindow(t_Handle h_FmMacsecSecY, bool replayProtect, uint32_t replayWindow)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    p_FmMacsecSecY->replayProtect   = replayProtect;
++    p_FmMacsecSecY->replayWindow    = replayWindow;
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_ConfigValidationMode(t_Handle h_FmMacsecSecY, e_FmMacsecValidFrameBehavior validateFrames)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    p_FmMacsecSecY->validateFrames = validateFrames;
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_ConfigConfidentiality(t_Handle h_FmMacsecSecY, bool confidentialityEnable, uint16_t confidentialityOffset)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    p_FmMacsecSecY->confidentialityEnable = confidentialityEnable;
++    p_FmMacsecSecY->confidentialityOffset = confidentialityOffset;
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_ConfigPointToPoint(t_Handle h_FmMacsecSecY)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    p_FmMacsecSecY->numOfRxSc = 1;
++    p_FmMacsecSecY->isPointToPoint = TRUE;
++    p_FmMacsecSecY->sciInsertionMode = e_FM_MACSEC_SCI_INSERTION_MODE_IMPLICT_PTP;
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_ConfigException(t_Handle h_FmMacsecSecY, e_FmMacsecSecYExceptions exception, bool enable)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    uint32_t        bitMask         = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    GET_EXCEPTION_FLAG(bitMask, exception);
++    if (bitMask)
++    {
++        if (enable)
++            p_FmMacsecSecY->exceptions |= bitMask;
++        else
++            p_FmMacsecSecY->exceptions &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
++
++    return E_OK;
++}
++
++t_Error FM_MACSEC_SECY_ConfigEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    uint32_t        bitMask         = 0;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++
++    GET_EVENT_FLAG(bitMask, event);
++    if (bitMask)
++    {
++        if (enable)
++            p_FmMacsecSecY->events |= bitMask;
++        else
++            p_FmMacsecSecY->events &= ~bitMask;
++    }
++    else
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined event"));
++
++    return E_OK;
++}
++
++t_Handle FM_MACSEC_SECY_CreateRxSc(t_Handle h_FmMacsecSecY, t_FmMacsecSecYSCParams *p_ScParams)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++
++    SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY, E_INVALID_HANDLE, NULL);
++    SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE, NULL);
++    SANITY_CHECK_RETURN_VALUE(p_ScParams, E_NULL_POINTER, NULL);
++    SANITY_CHECK_RETURN_VALUE(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE, NULL);
++
++    return FmMacsecSecYCreateSc(p_FmMacsecSecY, p_ScParams->sci, p_ScParams->cipherSuite, e_SC_RX);
++}
++
++t_Error FM_MACSEC_SECY_DeleteRxSc(t_Handle h_FmMacsecSecY, t_Handle h_Sc)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++
++    return FmMacsecSecYDeleteSc(p_FmMacsecSecY, p_FmSecYSc, e_SC_RX);
++}
++
++t_Error FM_MACSEC_SECY_CreateRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already assigned",an));
++
++    if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, an, lowestPn, key)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++;
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_DeleteRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++    t_Error         err             = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an));
++
++    if ((err = FmMacsecDeleteRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    p_FmSecYSc->numOfSa--;
++    p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
++    /* TODO - check if statistics need to be read*/
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_RxSaEnableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
++
++    if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    p_FmSecYSc->sa[an].active = TRUE;
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_RxSaDisableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
++
++    if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    p_FmSecYSc->sa[an].active = FALSE;
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_RxSaUpdateNextPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtNextPN)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
++
++    if ((err = FmMacsecRxSaUpdateNextPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtNextPN)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_RxSaUpdateLowestPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtLowestPN)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
++
++    if ((err = FmMacsecRxSaUpdateLowestPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtLowestPN)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_RxSaModifyKey(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, macsecSAKey_t key)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc     = (t_SecYSc *)h_Sc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
++
++    if (p_FmSecYSc->sa[an].active)
++        if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK)
++            RETURN_ERROR(MINOR, err, NO_MSG);
++
++    /* TODO - statistics should be read */
++
++    if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, an, 1, key)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    if (p_FmSecYSc->sa[an].active)
++        if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK)
++            RETURN_ERROR(MINOR, err, NO_MSG);
++    return err;
++}
++
++
++t_Error FM_MACSEC_SECY_CreateTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an, macsecSAKey_t key)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, err, ("An %d is already assigned",an));
++
++    if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, key)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++;
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_DeleteTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an));
++
++    if ((err = FmMacsecDeleteTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    p_FmSecYSc->numOfSa--;
++    p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
++    /* TODO - check if statistics need to be read*/
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_TxSaModifyKey(t_Handle h_FmMacsecSecY, macsecAN_t nextActiveAn, macsecSAKey_t key)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc;
++    macsecAN_t      currentAn;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(nextActiveAn < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec,
++                                     p_FmSecYSc->scId,
++                                     &currentAn)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec,
++                                     p_FmSecYSc->scId,
++                                     p_FmSecYSc->sa[nextActiveAn].saId,
++                                     nextActiveAn)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    /* TODO - statistics should be read */
++
++    if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[currentAn].saId, key)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_TxSaSetActive(t_Handle h_FmMacsecSecY, macsecAN_t an)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
++
++    if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
++        RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
++
++    if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec,
++                                     p_FmSecYSc->scId,
++                                     p_FmSecYSc->sa[an].saId,
++                                     an)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_TxSaGetActive(t_Handle h_FmMacsecSecY, macsecAN_t *p_An)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_An, E_INVALID_HANDLE);
++
++    if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec,
++                                     p_FmSecYSc->scId,
++                                     p_An)) != E_OK)
++        RETURN_ERROR(MINOR, err, NO_MSG);
++
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_GetRxScPhysId(t_Handle h_FmMacsecSecY, t_Handle h_Sc, uint32_t *p_ScPhysId)
++{
++    t_SecYSc        *p_FmSecYSc = (t_SecYSc *)h_Sc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(h_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(((t_FmMacsecSecY *)h_FmMacsecSecY)->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!((t_FmMacsecSecY *)h_FmMacsecSecY)->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++#ifdef DISABLE_SANITY_CHECKS
++    UNUSED(h_FmMacsecSecY);
++#endif /* DISABLE_SANITY_CHECKS */
++
++    *p_ScPhysId = p_FmSecYSc->scId;
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_GetTxScPhysId(t_Handle h_FmMacsecSecY, uint32_t *p_ScPhysId)
++{
++    t_FmMacsecSecY  *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
++    t_SecYSc        *p_FmSecYSc;
++    t_Error         err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
++    p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
++    SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
++
++    *p_ScPhysId = p_FmSecYSc->scId;
++    return err;
++}
++
++t_Error FM_MACSEC_SECY_SetException(t_Handle h_FmMacsecSecY, e_FmMacsecExceptions exception, bool enable)
++{
++   UNUSED(h_FmMacsecSecY);UNUSED(exception);UNUSED(enable);
++   RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_SECY_SetEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable)
++{
++    UNUSED(h_FmMacsecSecY);UNUSED(event);UNUSED(enable);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_SECY_GetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYStatistics *p_Statistics)
++{
++    UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_SECY_RxScGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, t_FmMacsecSecYRxScStatistics *p_Statistics)
++{
++    UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(p_Statistics);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_SECY_RxSaGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, t_FmMacsecSecYRxSaStatistics *p_Statistics)
++{
++    UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(an);UNUSED(p_Statistics);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_SECY_TxScGetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYTxScStatistics *p_Statistics)
++{
++    UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
++t_Error FM_MACSEC_SECY_TxSaGetStatistics(t_Handle h_FmMacsecSecY, macsecAN_t an, t_FmMacsecSecYTxSaStatistics *p_Statistics)
++{
++    UNUSED(h_FmMacsecSecY);UNUSED(an);UNUSED(p_Statistics);
++    RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
++}
++
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.h
+new file mode 100644
+index 0000000..0cf624e
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.h
+@@ -0,0 +1,144 @@
++/*
++ * Copyright 2008-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/******************************************************************************
++ @File          fm_macsec_secy.h
++
++ @Description   FM MACSEC SecY internal structures and definitions.
++*//***************************************************************************/
++#ifndef __FM_MACSEC_SECY_H
++#define __FM_MACSEC_SECY_H
++
++#include "error_ext.h"
++#include "std_ext.h"
++
++#include "fm_macsec.h"
++
++
++/**************************************************************************//**
++ @Description       Exceptions
++*//***************************************************************************/
++
++#define FM_MACSEC_SECY_EX_FRAME_DISCARDED           0x80000000
++
++#define GET_EXCEPTION_FLAG(bitMask, exception)  switch (exception){     \
++    case e_FM_MACSEC_SECY_EX_FRAME_DISCARDED:                           \
++        bitMask = FM_MACSEC_SECY_EX_FRAME_DISCARDED; break;             \
++    default: bitMask = 0;break;}
++
++/**************************************************************************//**
++ @Description       Events
++*//***************************************************************************/
++
++#define FM_MACSEC_SECY_EV_NEXT_PN                        0x80000000
++
++#define GET_EVENT_FLAG(bitMask, event)          switch (event){     \
++    case e_FM_MACSEC_SECY_EV_NEXT_PN:                               \
++        bitMask = FM_MACSEC_SECY_EV_NEXT_PN; break;                 \
++    default: bitMask = 0;break;}
++
++/**************************************************************************//**
++ @Description       Defaults
++*//***************************************************************************/
++
++#define DEFAULT_exceptions                  (FM_MACSEC_SECY_EX_FRAME_DISCARDED)
++#define DEFAULT_events                      (FM_MACSEC_SECY_EV_NEXT_PN)
++#define DEFAULT_numOfTxSc                   1
++#define DEFAULT_confidentialityEnable       FALSE
++#define DEFAULT_confidentialityOffset       0
++#define DEFAULT_sciInsertionMode            e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG
++#define DEFAULT_validateFrames              e_FM_MACSEC_VALID_FRAME_BEHAVIOR_STRICT
++#define DEFAULT_replayEnable                FALSE
++#define DEFAULT_replayWindow                0
++#define DEFAULT_protectFrames               TRUE
++#define DEFAULT_ptp                         FALSE
++
++/**************************************************************************//**
++ @Description       General defines
++*//***************************************************************************/
++
++#define SECY_AN_FREE_VALUE              MAX_NUM_OF_SA_PER_SC
++
++
++typedef struct {
++    e_ScSaId                            saId;
++    bool                                active;
++    union {
++        t_FmMacsecSecYRxSaStatistics    rxSaStatistics;
++        t_FmMacsecSecYTxSaStatistics    txSaStatistics;
++    };
++} t_SecYSa;
++
++typedef struct {
++    bool                                inUse;
++    uint32_t                            scId;
++    e_ScType                            type;
++    uint8_t                             numOfSa;
++    t_SecYSa                            sa[MAX_NUM_OF_SA_PER_SC];
++    union {
++        t_FmMacsecSecYRxScStatistics    rxScStatistics;
++        t_FmMacsecSecYTxScStatistics    txScStatistics;
++    };
++} t_SecYSc;
++
++typedef struct {
++    t_FmMacsecSecYSCParams              txScParams;             /**< Tx SC Params */
++} t_FmMacsecSecYDriverParam;
++
++typedef struct {
++    t_Handle                            h_FmMacsec;
++    bool                                confidentialityEnable;  /**< TRUE  - confidentiality protection and integrity protection
++                                                                     FALSE - no confidentiality protection, only integrity protection*/
++    uint16_t                            confidentialityOffset;  /**< The number of initial octets of each MSDU without confidentiality protection
++                                                                     common values are 0, 30, and 50 */
++    bool                                replayProtect;          /**< replay protection function mode */
++    uint32_t                            replayWindow;           /**< the size of the replay window */
++    e_FmMacsecValidFrameBehavior        validateFrames;         /**< validation function mode */
++    e_FmMacsecSciInsertionMode          sciInsertionMode;
++    bool                                protectFrames;
++    bool                                isPointToPoint;
++    e_FmMacsecSecYCipherSuite           cipherSuite;            /**< Cipher suite to be used for this SecY */
++    uint32_t                            numOfRxSc;              /**< Number of receive channels */
++    uint32_t                            numOfTxSc;              /**< Number of transmit channels */
++    t_SecYSc                            *p_RxSc;
++    t_SecYSc                            *p_TxSc;
++    uint32_t                            events;
++    uint32_t                            exceptions;
++    t_FmMacsecSecYExceptionsCallback    *f_Exception;           /**< TODO */
++    t_FmMacsecSecYEventsCallback        *f_Event;               /**< TODO */
++    t_Handle                            h_App;
++    t_FmMacsecSecYStatistics            statistics;
++    t_FmMacsecSecYDriverParam           *p_FmMacsecSecYDriverParam;
++} t_FmMacsecSecY;
++
++
++#endif /* __FM_MACSEC_SECY_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Makefile b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Makefile
+new file mode 100644
+index 0000000..619f660
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Makefile
+@@ -0,0 +1,23 @@
++#
++# Makefile for the Freescale Ethernet controllers
++#
++ccflags-y           += -DVERSION=\"\"
++#
++#Include netcomm SW specific definitions
++include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
++NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
++
++ccflags-y += -I$(NCSW_FM_INC)
++
++
++obj-y		+= fsl-ncsw-PFM1.o
++
++fsl-ncsw-PFM1-objs	:=   fm.o fm_muram.o fman.o
++
++obj-y		+= MAC/
++obj-y		+= Pcd/
++obj-y		+= SP/
++obj-y		+= Port/
++obj-y		+= HC/
++obj-y		+= Rtc/
++obj-y		+= MACSEC/
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/Makefile b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/Makefile
+new file mode 100644
+index 0000000..880c0e1
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/Makefile
+@@ -0,0 +1,23 @@
++#
++# Makefile for the Freescale Ethernet controllers
++#
++ccflags-y           += -DVERSION=\"\"
++#
++#Include netcomm SW specific definitions
++include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
++
++NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
++
++ccflags-y += -I$(NCSW_FM_INC)
++
++obj-y		+= fsl-ncsw-Pcd.o
++
++fsl-ncsw-Pcd-objs	:= fman_kg.o fman_prs.o fm_cc.o fm_kg.o fm_pcd.o fm_plcr.o fm_prs.o fm_manip.o
++
++ifeq ($(CONFIG_FMAN_V3H),y)
++fsl-ncsw-Pcd-objs	+= fm_replic.o
++endif
++ifeq ($(CONFIG_FMAN_V3L),y)
++fsl-ncsw-Pcd-objs       += fm_replic.o
++endif
++
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h
+new file mode 100644
+index 0000000..335ee68
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h
+@@ -0,0 +1,360 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++ /**************************************************************************//**
++ @File          crc64.h
++
++ @Description   brief This file contains the CRC64 Table, and __inline__
++                functions used for calculating crc.
++*//***************************************************************************/
++#ifndef __CRC64_H
++#define __CRC64_H
++
++#include "std_ext.h"
++
++
++#define BITS_PER_BYTE                   8
++
++#define CRC64_EXPON_ECMA_182            0xC96C5795D7870F42ULL
++#define CRC64_DEFAULT_INITVAL           0xFFFFFFFFFFFFFFFFULL
++
++#define CRC64_BYTE_MASK                 0xFF
++#define CRC64_TABLE_ENTRIES             ( 1 << BITS_PER_BYTE )
++#define CRC64_ODD_MASK                  1
++
++
++/**
++ \brief '64 bit crc' Table
++ */
++struct crc64_t {
++    uint64_t initial;                       /**< Initial seed */
++    uint64_t table[CRC64_TABLE_ENTRIES];    /**< CRC table entries */
++};
++
++
++static struct crc64_t CRC64_ECMA_182 = {
++    CRC64_DEFAULT_INITVAL,
++    {
++        0x0000000000000000ULL,
++        0xb32e4cbe03a75f6fULL,
++        0xf4843657a840a05bULL,
++        0x47aa7ae9abe7ff34ULL,
++        0x7bd0c384ff8f5e33ULL,
++        0xc8fe8f3afc28015cULL,
++        0x8f54f5d357cffe68ULL,
++        0x3c7ab96d5468a107ULL,
++        0xf7a18709ff1ebc66ULL,
++        0x448fcbb7fcb9e309ULL,
++        0x0325b15e575e1c3dULL,
++        0xb00bfde054f94352ULL,
++        0x8c71448d0091e255ULL,
++        0x3f5f08330336bd3aULL,
++        0x78f572daa8d1420eULL,
++        0xcbdb3e64ab761d61ULL,
++        0x7d9ba13851336649ULL,
++        0xceb5ed8652943926ULL,
++        0x891f976ff973c612ULL,
++        0x3a31dbd1fad4997dULL,
++        0x064b62bcaebc387aULL,
++        0xb5652e02ad1b6715ULL,
++        0xf2cf54eb06fc9821ULL,
++        0x41e11855055bc74eULL,
++        0x8a3a2631ae2dda2fULL,
++        0x39146a8fad8a8540ULL,
++        0x7ebe1066066d7a74ULL,
++        0xcd905cd805ca251bULL,
++        0xf1eae5b551a2841cULL,
++        0x42c4a90b5205db73ULL,
++        0x056ed3e2f9e22447ULL,
++        0xb6409f5cfa457b28ULL,
++        0xfb374270a266cc92ULL,
++        0x48190ecea1c193fdULL,
++        0x0fb374270a266cc9ULL,
++        0xbc9d3899098133a6ULL,
++        0x80e781f45de992a1ULL,
++        0x33c9cd4a5e4ecdceULL,
++        0x7463b7a3f5a932faULL,
++        0xc74dfb1df60e6d95ULL,
++        0x0c96c5795d7870f4ULL,
++        0xbfb889c75edf2f9bULL,
++        0xf812f32ef538d0afULL,
++        0x4b3cbf90f69f8fc0ULL,
++        0x774606fda2f72ec7ULL,
++        0xc4684a43a15071a8ULL,
++        0x83c230aa0ab78e9cULL,
++        0x30ec7c140910d1f3ULL,
++        0x86ace348f355aadbULL,
++        0x3582aff6f0f2f5b4ULL,
++        0x7228d51f5b150a80ULL,
++        0xc10699a158b255efULL,
++        0xfd7c20cc0cdaf4e8ULL,
++        0x4e526c720f7dab87ULL,
++        0x09f8169ba49a54b3ULL,
++        0xbad65a25a73d0bdcULL,
++        0x710d64410c4b16bdULL,
++        0xc22328ff0fec49d2ULL,
++        0x85895216a40bb6e6ULL,
++        0x36a71ea8a7ace989ULL,
++        0x0adda7c5f3c4488eULL,
++        0xb9f3eb7bf06317e1ULL,
++        0xfe5991925b84e8d5ULL,
++        0x4d77dd2c5823b7baULL,
++        0x64b62bcaebc387a1ULL,
++        0xd7986774e864d8ceULL,
++        0x90321d9d438327faULL,
++        0x231c512340247895ULL,
++        0x1f66e84e144cd992ULL,
++        0xac48a4f017eb86fdULL,
++        0xebe2de19bc0c79c9ULL,
++        0x58cc92a7bfab26a6ULL,
++        0x9317acc314dd3bc7ULL,
++        0x2039e07d177a64a8ULL,
++        0x67939a94bc9d9b9cULL,
++        0xd4bdd62abf3ac4f3ULL,
++        0xe8c76f47eb5265f4ULL,
++        0x5be923f9e8f53a9bULL,
++        0x1c4359104312c5afULL,
++        0xaf6d15ae40b59ac0ULL,
++        0x192d8af2baf0e1e8ULL,
++        0xaa03c64cb957be87ULL,
++        0xeda9bca512b041b3ULL,
++        0x5e87f01b11171edcULL,
++        0x62fd4976457fbfdbULL,
++        0xd1d305c846d8e0b4ULL,
++        0x96797f21ed3f1f80ULL,
++        0x2557339fee9840efULL,
++        0xee8c0dfb45ee5d8eULL,
++        0x5da24145464902e1ULL,
++        0x1a083bacedaefdd5ULL,
++        0xa9267712ee09a2baULL,
++        0x955cce7fba6103bdULL,
++        0x267282c1b9c65cd2ULL,
++        0x61d8f8281221a3e6ULL,
++        0xd2f6b4961186fc89ULL,
++        0x9f8169ba49a54b33ULL,
++        0x2caf25044a02145cULL,
++        0x6b055fede1e5eb68ULL,
++        0xd82b1353e242b407ULL,
++        0xe451aa3eb62a1500ULL,
++        0x577fe680b58d4a6fULL,
++        0x10d59c691e6ab55bULL,
++        0xa3fbd0d71dcdea34ULL,
++        0x6820eeb3b6bbf755ULL,
++        0xdb0ea20db51ca83aULL,
++        0x9ca4d8e41efb570eULL,
++        0x2f8a945a1d5c0861ULL,
++        0x13f02d374934a966ULL,
++        0xa0de61894a93f609ULL,
++        0xe7741b60e174093dULL,
++        0x545a57dee2d35652ULL,
++        0xe21ac88218962d7aULL,
++        0x5134843c1b317215ULL,
++        0x169efed5b0d68d21ULL,
++        0xa5b0b26bb371d24eULL,
++        0x99ca0b06e7197349ULL,
++        0x2ae447b8e4be2c26ULL,
++        0x6d4e3d514f59d312ULL,
++        0xde6071ef4cfe8c7dULL,
++        0x15bb4f8be788911cULL,
++        0xa6950335e42fce73ULL,
++        0xe13f79dc4fc83147ULL,
++        0x521135624c6f6e28ULL,
++        0x6e6b8c0f1807cf2fULL,
++        0xdd45c0b11ba09040ULL,
++        0x9aefba58b0476f74ULL,
++        0x29c1f6e6b3e0301bULL,
++        0xc96c5795d7870f42ULL,
++        0x7a421b2bd420502dULL,
++        0x3de861c27fc7af19ULL,
++        0x8ec62d7c7c60f076ULL,
++        0xb2bc941128085171ULL,
++        0x0192d8af2baf0e1eULL,
++        0x4638a2468048f12aULL,
++        0xf516eef883efae45ULL,
++        0x3ecdd09c2899b324ULL,
++        0x8de39c222b3eec4bULL,
++        0xca49e6cb80d9137fULL,
++        0x7967aa75837e4c10ULL,
++        0x451d1318d716ed17ULL,
++        0xf6335fa6d4b1b278ULL,
++        0xb199254f7f564d4cULL,
++        0x02b769f17cf11223ULL,
++        0xb4f7f6ad86b4690bULL,
++        0x07d9ba1385133664ULL,
++        0x4073c0fa2ef4c950ULL,
++        0xf35d8c442d53963fULL,
++        0xcf273529793b3738ULL,
++        0x7c0979977a9c6857ULL,
++        0x3ba3037ed17b9763ULL,
++        0x888d4fc0d2dcc80cULL,
++        0x435671a479aad56dULL,
++        0xf0783d1a7a0d8a02ULL,
++        0xb7d247f3d1ea7536ULL,
++        0x04fc0b4dd24d2a59ULL,
++        0x3886b22086258b5eULL,
++        0x8ba8fe9e8582d431ULL,
++        0xcc0284772e652b05ULL,
++        0x7f2cc8c92dc2746aULL,
++        0x325b15e575e1c3d0ULL,
++        0x8175595b76469cbfULL,
++        0xc6df23b2dda1638bULL,
++        0x75f16f0cde063ce4ULL,
++        0x498bd6618a6e9de3ULL,
++        0xfaa59adf89c9c28cULL,
++        0xbd0fe036222e3db8ULL,
++        0x0e21ac88218962d7ULL,
++        0xc5fa92ec8aff7fb6ULL,
++        0x76d4de52895820d9ULL,
++        0x317ea4bb22bfdfedULL,
++        0x8250e80521188082ULL,
++        0xbe2a516875702185ULL,
++        0x0d041dd676d77eeaULL,
++        0x4aae673fdd3081deULL,
++        0xf9802b81de97deb1ULL,
++        0x4fc0b4dd24d2a599ULL,
++        0xfceef8632775faf6ULL,
++        0xbb44828a8c9205c2ULL,
++        0x086ace348f355aadULL,
++        0x34107759db5dfbaaULL,
++        0x873e3be7d8faa4c5ULL,
++        0xc094410e731d5bf1ULL,
++        0x73ba0db070ba049eULL,
++        0xb86133d4dbcc19ffULL,
++        0x0b4f7f6ad86b4690ULL,
++        0x4ce50583738cb9a4ULL,
++        0xffcb493d702be6cbULL,
++        0xc3b1f050244347ccULL,
++        0x709fbcee27e418a3ULL,
++        0x3735c6078c03e797ULL,
++        0x841b8ab98fa4b8f8ULL,
++        0xadda7c5f3c4488e3ULL,
++        0x1ef430e13fe3d78cULL,
++        0x595e4a08940428b8ULL,
++        0xea7006b697a377d7ULL,
++        0xd60abfdbc3cbd6d0ULL,
++        0x6524f365c06c89bfULL,
++        0x228e898c6b8b768bULL,
++        0x91a0c532682c29e4ULL,
++        0x5a7bfb56c35a3485ULL,
++        0xe955b7e8c0fd6beaULL,
++        0xaeffcd016b1a94deULL,
++        0x1dd181bf68bdcbb1ULL,
++        0x21ab38d23cd56ab6ULL,
++        0x9285746c3f7235d9ULL,
++        0xd52f0e859495caedULL,
++        0x6601423b97329582ULL,
++        0xd041dd676d77eeaaULL,
++        0x636f91d96ed0b1c5ULL,
++        0x24c5eb30c5374ef1ULL,
++        0x97eba78ec690119eULL,
++        0xab911ee392f8b099ULL,
++        0x18bf525d915feff6ULL,
++        0x5f1528b43ab810c2ULL,
++        0xec3b640a391f4fadULL,
++        0x27e05a6e926952ccULL,
++        0x94ce16d091ce0da3ULL,
++        0xd3646c393a29f297ULL,
++        0x604a2087398eadf8ULL,
++        0x5c3099ea6de60cffULL,
++        0xef1ed5546e415390ULL,
++        0xa8b4afbdc5a6aca4ULL,
++        0x1b9ae303c601f3cbULL,
++        0x56ed3e2f9e224471ULL,
++        0xe5c372919d851b1eULL,
++        0xa26908783662e42aULL,
++        0x114744c635c5bb45ULL,
++        0x2d3dfdab61ad1a42ULL,
++        0x9e13b115620a452dULL,
++        0xd9b9cbfcc9edba19ULL,
++        0x6a978742ca4ae576ULL,
++        0xa14cb926613cf817ULL,
++        0x1262f598629ba778ULL,
++        0x55c88f71c97c584cULL,
++        0xe6e6c3cfcadb0723ULL,
++        0xda9c7aa29eb3a624ULL,
++        0x69b2361c9d14f94bULL,
++        0x2e184cf536f3067fULL,
++        0x9d36004b35545910ULL,
++        0x2b769f17cf112238ULL,
++        0x9858d3a9ccb67d57ULL,
++        0xdff2a94067518263ULL,
++        0x6cdce5fe64f6dd0cULL,
++        0x50a65c93309e7c0bULL,
++        0xe388102d33392364ULL,
++        0xa4226ac498dedc50ULL,
++        0x170c267a9b79833fULL,
++        0xdcd7181e300f9e5eULL,
++        0x6ff954a033a8c131ULL,
++        0x28532e49984f3e05ULL,
++        0x9b7d62f79be8616aULL,
++        0xa707db9acf80c06dULL,
++        0x14299724cc279f02ULL,
++        0x5383edcd67c06036ULL,
++        0xe0ada17364673f59ULL
++    }
++};
++
++
++/**
++ \brief Initializes the crc seed
++ */
++static __inline__ uint64_t crc64_init(void)
++{
++    return CRC64_ECMA_182.initial;
++}
++
++/**
++ \brief Computes 64 bit the crc
++ \param[in] data Pointer to the Data in the frame
++ \param[in] len Length of the Data
++ \param[in] crc seed
++ \return calculated crc
++ */
++static __inline__ uint64_t crc64_compute(void const *data,
++                                         uint32_t   len,
++                                         uint64_t   seed)
++{
++    uint32_t i;
++    uint64_t crc = seed;
++    uint8_t *bdata = (uint8_t *) data;
++
++    for (i = 0; i < len; i++)
++        crc =
++            CRC64_ECMA_182.
++            table[(crc ^ *bdata++) & CRC64_BYTE_MASK] ^ (crc >> 8);
++
++    return crc;
++}
++
++
++#endif /* __CRC64_H */
+diff --git a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c
+new file mode 100644
+index 0000000..51df898
+--- /dev/null
++++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c
+@@ -0,0 +1,7533 @@
++/*
++ * Copyright 2008-2012 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/******************************************************************************
++ @File          fm_cc.c
++
++ @Description   FM Coarse Classifier implementation
++ *//***************************************************************************/
++#include "std_ext.h"
++#include "error_ext.h"
++#include "string_ext.h"
++#include "debug_ext.h"
++#include "fm_pcd_ext.h"
++#include "fm_muram_ext.h"
++
++#include "fm_common.h"
++#include "fm_pcd.h"
++#include "fm_hc.h"
++#include "fm_cc.h"
++#include "crc64.h"
++
++/****************************************/
++/*       static functions               */
++/****************************************/
++
++
++static t_Error CcRootTryLock(t_Handle h_FmPcdCcTree)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree;
++
++    ASSERT_COND(h_FmPcdCcTree);
++
++    if (FmPcdLockTryLock(p_FmPcdCcTree->p_Lock))
++        return E_OK;
++
++    return ERROR_CODE(E_BUSY);
++}
++
++static void CcRootReleaseLock(t_Handle h_FmPcdCcTree)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree;
++
++    ASSERT_COND(h_FmPcdCcTree);
++
++    FmPcdLockUnlock(p_FmPcdCcTree->p_Lock);
++}
++
++static void UpdateNodeOwner(t_FmPcdCcNode *p_CcNode, bool add)
++{
++    uint32_t intFlags;
++
++    ASSERT_COND(p_CcNode);
++
++    intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock);
++
++    if (add)
++        p_CcNode->owners++;
++    else
++    {
++        ASSERT_COND(p_CcNode->owners);
++        p_CcNode->owners--;
++    }
++
++    XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags);
++}
++
++static __inline__ t_FmPcdStatsObj* DequeueStatsObj(t_List *p_List)
++{
++    t_FmPcdStatsObj *p_StatsObj = NULL;
++    t_List *p_Next;
++
++    if (!LIST_IsEmpty(p_List))
++    {
++        p_Next = LIST_FIRST(p_List);
++        p_StatsObj = LIST_OBJECT(p_Next, t_FmPcdStatsObj, node);
++        ASSERT_COND(p_StatsObj);
++        LIST_DelAndInit(p_Next);
++    }
++
++    return p_StatsObj;
++}
++
++static __inline__ void EnqueueStatsObj(t_List *p_List,
++                                       t_FmPcdStatsObj *p_StatsObj)
++{
++    LIST_AddToTail(&p_StatsObj->node, p_List);
++}
++
++static void FreeStatObjects(t_List *p_List, t_Handle h_FmMuram)
++{
++    t_FmPcdStatsObj *p_StatsObj;
++
++    while (!LIST_IsEmpty(p_List))
++    {
++        p_StatsObj = DequeueStatsObj(p_List);
++        ASSERT_COND(p_StatsObj);
++
++        FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsAd);
++        FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsCounters);
++
++        XX_Free(p_StatsObj);
++    }
++}
++
++static t_FmPcdStatsObj* GetStatsObj(t_FmPcdCcNode *p_CcNode)
++{
++    t_FmPcdStatsObj* p_StatsObj;
++    t_Handle h_FmMuram;
++
++    ASSERT_COND(p_CcNode);
++
++    /* If 'maxNumOfKeys' was passed, all statistics object were preallocated
++     upon node initialization */
++    if (p_CcNode->maxNumOfKeys)
++    {
++        p_StatsObj = DequeueStatsObj(&p_CcNode->availableStatsLst);
++    }
++    else
++    {
++        h_FmMuram = ((t_FmPcd *)(p_CcNode->h_FmPcd))->h_FmMuram;
++        ASSERT_COND(h_FmMuram);
++
++        p_StatsObj = XX_Malloc(sizeof(t_FmPcdStatsObj));
++        if (!p_StatsObj)
++        {
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("statistics object"));
++            return NULL;
++        }
++
++        p_StatsObj->h_StatsAd = (t_Handle)FM_MURAM_AllocMem(
++                h_FmMuram, FM_PCD_CC_AD_ENTRY_SIZE, FM_PCD_CC_AD_TABLE_ALIGN);
++        if (!p_StatsObj->h_StatsAd)
++        {
++            XX_Free(p_StatsObj);
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for statistics ADs"));
++            return NULL;
++        }
++        IOMemSet32(p_StatsObj->h_StatsAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
++
++        p_StatsObj->h_StatsCounters = (t_Handle)FM_MURAM_AllocMem(
++                h_FmMuram, p_CcNode->countersArraySize,
++                FM_PCD_CC_AD_TABLE_ALIGN);
++        if (!p_StatsObj->h_StatsCounters)
++        {
++            FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsAd);
++            XX_Free(p_StatsObj);
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for statistics counters"));
++            return NULL;
++        }
++        IOMemSet32(p_StatsObj->h_StatsCounters, 0, p_CcNode->countersArraySize);
++    }
++
++    return p_StatsObj;
++}
++
++static void PutStatsObj(t_FmPcdCcNode *p_CcNode, t_FmPcdStatsObj *p_StatsObj)
++{
++    t_Handle h_FmMuram;
++
++    ASSERT_COND(p_CcNode);
++    ASSERT_COND(p_StatsObj);
++
++    /* If 'maxNumOfKeys' was passed, all statistics object were preallocated
++     upon node initialization and now will be enqueued back to the list */
++    if (p_CcNode->maxNumOfKeys)
++    {
++        /* Nullify counters */
++        IOMemSet32(p_StatsObj->h_StatsCounters, 0, p_CcNode->countersArraySize);
++
++        EnqueueStatsObj(&p_CcNode->availableStatsLst, p_StatsObj);
++    }
++    else
++    {
++        h_FmMuram = ((t_FmPcd *)(p_CcNode->h_FmPcd))->h_FmMuram;
++        ASSERT_COND(h_FmMuram);
++
++        FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsAd);
++        FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsCounters);
++
++        XX_Free(p_StatsObj);
++    }
++}
++
++static void SetStatsCounters(t_AdOfTypeStats *p_StatsAd,
++                             uint32_t statsCountersAddr)
++{
++    uint32_t tmp = (statsCountersAddr & FM_PCD_AD_STATS_COUNTERS_ADDR_MASK);
++
++    WRITE_UINT32(p_StatsAd->statsTableAddr, tmp);
++}
++
++
++static void UpdateStatsAd(t_FmPcdCcStatsParams *p_FmPcdCcStatsParams,
++                          t_Handle h_Ad, uint64_t physicalMuramBase)
++{
++    t_AdOfTypeStats *p_StatsAd;
++    uint32_t statsCountersAddr, nextActionAddr, tmp;
++#if (DPAA_VERSION >= 11)
++    uint32_t frameLengthRangesAddr;
++#endif /* (DPAA_VERSION >= 11) */
++
++    p_StatsAd = (t_AdOfTypeStats *)p_FmPcdCcStatsParams->h_StatsAd;
++
++    tmp = FM_PCD_AD_STATS_TYPE;
++
++#if (DPAA_VERSION >= 11)
++    if (p_FmPcdCcStatsParams->h_StatsFLRs)
++    {
++        frameLengthRangesAddr = (uint32_t)((XX_VirtToPhys(
++                p_FmPcdCcStatsParams->h_StatsFLRs) - physicalMuramBase));
++        tmp |= (frameLengthRangesAddr & FM_PCD_AD_STATS_FLR_ADDR_MASK);
++    }
++#endif /* (DPAA_VERSION >= 11) */
++    WRITE_UINT32(p_StatsAd->profileTableAddr, tmp);
++
++    nextActionAddr = (uint32_t)((XX_VirtToPhys(h_Ad) - physicalMuramBase));
++    tmp = 0;
++    tmp |= (uint32_t)((nextActionAddr << FM_PCD_AD_STATS_NEXT_ACTION_SHIFT)
++            & FM_PCD_AD_STATS_NEXT_ACTION_MASK);
++    tmp |= (FM_PCD_AD_STATS_NAD_EN | FM_PCD_AD_STATS_OP_CODE);
++
++#if (DPAA_VERSION >= 11)
++    if (p_FmPcdCcStatsParams->h_StatsFLRs)
++        tmp |= FM_PCD_AD_STATS_FLR_EN;
++#endif /* (DPAA_VERSION >= 11) */
++
++    WRITE_UINT32(p_StatsAd->nextActionIndx, tmp);
++
++    statsCountersAddr = (uint32_t)((XX_VirtToPhys(
++            p_FmPcdCcStatsParams->h_StatsCounters) - physicalMuramBase));
++    SetStatsCounters(p_StatsAd, statsCountersAddr);
++}
++
++static void FillAdOfTypeContLookup(t_Handle h_Ad,
++                                   t_FmPcdCcStatsParams *p_FmPcdCcStatsParams,
++                                   t_Handle h_FmPcd, t_Handle p_CcNode,
++                                   t_Handle h_Manip, t_Handle h_FrmReplic)
++{
++    t_FmPcdCcNode *p_Node = (t_FmPcdCcNode *)p_CcNode;
++    t_AdOfTypeContLookup *p_AdContLookup = (t_AdOfTypeContLookup *)h_Ad;
++    t_Handle h_TmpAd;
++    t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
++    uint32_t tmpReg32;
++    t_Handle p_AdNewPtr = NULL;
++
++    UNUSED(h_Manip);
++    UNUSED(h_FrmReplic);
++
++    /* there are 3 cases handled in this routine of building a "Continue lookup" type AD.
++     * Case 1: No Manip. The action descriptor is built within the match table.
++     *         p_AdResult = p_AdNewPtr;
++     * Case 2: Manip exists. A new AD is created - p_AdNewPtr. It is initialized
++     *         either in the FmPcdManipUpdateAdResultForCc routine or it was already
++     *         initialized and returned here.
++     *         p_AdResult (within the match table) will be initialized after
++     *         this routine returns and point to the existing AD.
++     * Case 3: Manip exists. The action descriptor is built within the match table.
++     *         FmPcdManipUpdateAdContLookupForCc returns a NULL p_AdNewPtr.
++     */
++
++    /* As default, the "new" ptr is the current one. i.e. the content of the result
++     * AD will be written into the match table itself (case (1))*/
++    p_AdNewPtr = p_AdContLookup;
++
++    /* Initialize an action descriptor, if current statistics mode requires an Ad */
++    if (p_FmPcdCcStatsParams)
++    {
++        ASSERT_COND(p_FmPcdCcStatsParams->h_StatsAd);
++        ASSERT_COND(p_FmPcdCcStatsParams->h_StatsCounters);
++
++        /* Swapping addresses between statistics Ad and the current lookup AD */
++        h_TmpAd = p_FmPcdCcStatsParams->h_StatsAd;
++        p_FmPcdCcStatsParams->h_StatsAd = h_Ad;
++        h_Ad = h_TmpAd;
++
++        p_AdNewPtr = h_Ad;
++        p_AdContLookup = h_Ad;
++
++        /* Init statistics Ad and connect current lookup AD as 'next action' from statistics Ad */
++        UpdateStatsAd(p_FmPcdCcStatsParams, h_Ad, p_FmPcd->physicalMuramBase);
++    }
++
++#if DPAA_VERSION >= 11
++    if (h_Manip && h_FrmReplic)
++        FmPcdManipUpdateAdContLookupForCc(
++                h_Manip,
++                h_Ad,
++                &p_AdNewPtr,
++                (uint32_t)((XX_VirtToPhys(
++                        FrmReplicGroupGetSourceTableDescriptor(h_FrmReplic))
++                        - p_FmPcd->physicalMuramBase)));
++    else
++        if (h_FrmReplic)
++            FrmReplicGroupUpdateAd(h_FrmReplic, h_Ad, &p_AdNewPtr);
++        else
++#endif /* (DPAA_VERSION >= 11) */
++            if (h_Manip)
++                FmPcdManipUpdateAdContLookupForCc(
++                        h_Manip,
++                        h_Ad,
++                        &p_AdNewPtr,
++
++#ifdef FM_CAPWAP_SUPPORT
++                        /*no check for opcode of manip - this step can be reached only with capwap_applic_specific*/
++                        (uint32_t)((XX_VirtToPhys(p_Node->h_AdTable) - p_FmPcd->physicalMuramBase))
++#else  /* not FM_CAPWAP_SUPPORT */
++                        (uint32_t)((XX_VirtToPhys(p_Node->h_Ad)
++                                - p_FmPcd->physicalMuramBase))
++#endif /* not FM_CAPWAP_SUPPORT */
++                        );
++
++    /* if (p_AdNewPtr = NULL) --> Done. (case (3)) */
++    if (p_AdNewPtr)
++    {
++        /* cases (1) & (2) */
++        tmpReg32 = 0;
++        tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE;
++        tmpReg32 |=
++                p_Node->sizeOfExtraction ? ((p_Node->sizeOfExtraction - 1) << 24) :
++                        0;
++        tmpReg32 |= (uint32_t)(XX_VirtToPhys(p_Node->h_AdTable)
++                - p_FmPcd->physicalMuramBase);
++        WRITE_UINT32(p_AdContLookup->ccAdBase, tmpReg32);
++
++        tmpReg32 = 0;
++        tmpReg32 |= p_Node->numOfKeys << 24;
++        tmpReg32 |= (p_Node->lclMask ? FM_PCD_AD_CONT_LOOKUP_LCL_MASK : 0);
++        tmpReg32 |=
++                p_Node->h_KeysMatchTable ? (uint32_t)(XX_VirtToPhys(
++                        p_Node->h_KeysMatchTable) - p_FmPcd->physicalMuramBase) :
++                        0;
++        WRITE_UINT32(p_AdContLookup->matchTblPtr, tmpReg32);
++
++        tmpReg32 = 0;
++        tmpReg32 |= p_Node->prsArrayOffset << 24;
++        tmpReg32 |= p_Node->offset << 16;
++        tmpReg32 |= p_Node->parseCode;
++        WRITE_UINT32(p_AdContLookup->pcAndOffsets, tmpReg32);
++
++        Mem2IOCpy32((void*)&p_AdContLookup->gmask, p_Node->p_GlblMask,
++                        CC_GLBL_MASK_SIZE);
++    }
++}
++
++static t_Error AllocAndFillAdForContLookupManip(t_Handle h_CcNode)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode;
++    uint32_t intFlags;
++
++    ASSERT_COND(p_CcNode);
++
++    intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock);
++
++    if (!p_CcNode->h_Ad)
++    {
++        if (p_CcNode->maxNumOfKeys)
++            p_CcNode->h_Ad = p_CcNode->h_TmpAd;
++        else
++            p_CcNode->h_Ad = (t_Handle)FM_MURAM_AllocMem(
++                    ((t_FmPcd *)(p_CcNode->h_FmPcd))->h_FmMuram,
++                    FM_PCD_CC_AD_ENTRY_SIZE, FM_PCD_CC_AD_TABLE_ALIGN);
++
++        XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags);
++
++        if (!p_CcNode->h_Ad)
++            RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                         ("MURAM allocation for CC action descriptor"));
++
++        IOMemSet32(p_CcNode->h_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE);
++
++        FillAdOfTypeContLookup(p_CcNode->h_Ad, NULL, p_CcNode->h_FmPcd,
++                               p_CcNode, NULL, NULL);
++    }
++    else
++        XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags);
++
++    return E_OK;
++}
++
++static t_Error SetRequiredAction1(
++        t_Handle h_FmPcd, uint32_t requiredAction,
++        t_FmPcdCcKeyAndNextEngineParams *p_CcKeyAndNextEngineParamsTmp,
++        t_Handle h_AdTmp, uint16_t numOfEntries, t_Handle h_Tree)
++{
++    t_AdOfTypeResult *p_AdTmp = (t_AdOfTypeResult *)h_AdTmp;
++    uint32_t tmpReg32;
++    t_Error err;
++    t_FmPcdCcNode *p_CcNode;
++    int i = 0;
++    uint16_t tmp = 0;
++    uint16_t profileId;
++    uint8_t relativeSchemeId, physicalSchemeId;
++    t_CcNodeInformation ccNodeInfo;
++
++    for (i = 0; i < numOfEntries; i++)
++    {
++        if (i == 0)
++            h_AdTmp = PTR_MOVE(h_AdTmp, i*FM_PCD_CC_AD_ENTRY_SIZE);
++        else
++            h_AdTmp = PTR_MOVE(h_AdTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++
++        switch (p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.nextEngine)
++        {
++            case (e_FM_PCD_CC):
++                if (requiredAction)
++                {
++                    p_CcNode =
++                            p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.ccParams.h_CcNode;
++                    ASSERT_COND(p_CcNode);
++                    if (p_CcNode->shadowAction == requiredAction)
++                        break;
++                    if ((requiredAction & UPDATE_CC_WITH_TREE)
++                            && !(p_CcNode->shadowAction & UPDATE_CC_WITH_TREE))
++                    {
++
++                        memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++                        ccNodeInfo.h_CcNode = h_Tree;
++                        EnqueueNodeInfoToRelevantLst(&p_CcNode->ccTreesLst,
++                                                     &ccNodeInfo, NULL);
++                        p_CcKeyAndNextEngineParamsTmp[i].shadowAction |=
++                                UPDATE_CC_WITH_TREE;
++                    }
++                    if ((requiredAction & UPDATE_CC_SHADOW_CLEAR)
++                            && !(p_CcNode->shadowAction & UPDATE_CC_SHADOW_CLEAR))
++                    {
++
++                        p_CcNode->shadowAction = 0;
++                    }
++
++                    if ((requiredAction & UPDATE_CC_WITH_DELETE_TREE)
++                            && !(p_CcNode->shadowAction
++                                    & UPDATE_CC_WITH_DELETE_TREE))
++                    {
++                        DequeueNodeInfoFromRelevantLst(&p_CcNode->ccTreesLst,
++                                                       h_Tree, NULL);
++                        p_CcKeyAndNextEngineParamsTmp[i].shadowAction |=
++                                UPDATE_CC_WITH_DELETE_TREE;
++                    }
++                    if (p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine
++                            != e_FM_PCD_INVALID)
++                        tmp = (uint8_t)(p_CcNode->numOfKeys + 1);
++                    else
++                        tmp = p_CcNode->numOfKeys;
++                    err = SetRequiredAction1(h_FmPcd, requiredAction,
++                                             p_CcNode->keyAndNextEngineParams,
++                                             p_CcNode->h_AdTable, tmp, h_Tree);
++                    if (err != E_OK)
++                        return err;
++                    if (requiredAction != UPDATE_CC_SHADOW_CLEAR)
++                        p_CcNode->shadowAction |= requiredAction;
++                }
++                break;
++
++            case (e_FM_PCD_KG):
++                if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA)
++                        && !(p_CcKeyAndNextEngineParamsTmp[i].shadowAction
++                                & UPDATE_NIA_ENQ_WITHOUT_DMA))
++                {
++                    physicalSchemeId =
++                            FmPcdKgGetSchemeId(
++                                    p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.kgParams.h_DirectScheme);
++                    relativeSchemeId = FmPcdKgGetRelativeSchemeId(
++                            h_FmPcd, physicalSchemeId);
++                    if (relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES)
++                        RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG);
++                    if (!FmPcdKgIsSchemeValidSw(
++                            p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.kgParams.h_DirectScheme))
++                        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                                     ("Invalid direct scheme."));
++                    if (!KgIsSchemeAlwaysDirect(h_FmPcd, relativeSchemeId))
++                        RETURN_ERROR(
++                                MAJOR, E_INVALID_STATE,
++                                ("For this action scheme has to be direct."));
++                    err =
++                            FmPcdKgCcGetSetParams(
++                                    h_FmPcd,
++                                    p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.kgParams.h_DirectScheme,
++                                    requiredAction, 0);
++                    if (err != E_OK)
++                        RETURN_ERROR(MAJOR, err, NO_MSG);
++                    p_CcKeyAndNextEngineParamsTmp[i].shadowAction |=
++                            requiredAction;
++                }
++                break;
++
++            case (e_FM_PCD_PLCR):
++                if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA)
++                        && !(p_CcKeyAndNextEngineParamsTmp[i].shadowAction
++                                & UPDATE_NIA_ENQ_WITHOUT_DMA))
++                {
++                    if (!p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.plcrParams.overrideParams)
++                        RETURN_ERROR(
++                                MAJOR,
++                                E_NOT_SUPPORTED,
++                                ("In this initialization only overrideFqid can be initialized"));
++                    if (!p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.plcrParams.sharedProfile)
++                        RETURN_ERROR(
++                                MAJOR,
++                                E_NOT_SUPPORTED,
++                                ("In this initialization only overrideFqid can be initialized"));
++                    err =
++                            FmPcdPlcrGetAbsoluteIdByProfileParams(
++                                    h_FmPcd,
++                                    e_FM_PCD_PLCR_SHARED,
++                                    NULL,
++                                    p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.plcrParams.newRelativeProfileId,
++                                    &profileId);
++                    if (err != E_OK)
++                        RETURN_ERROR(MAJOR, err, NO_MSG);
++                    err = FmPcdPlcrCcGetSetParams(h_FmPcd, profileId,
++                                                  requiredAction);
++                    if (err != E_OK)
++                        RETURN_ERROR(MAJOR, err, NO_MSG);
++                    p_CcKeyAndNextEngineParamsTmp[i].shadowAction |=
++                            requiredAction;
++                }
++                break;
++
++            case (e_FM_PCD_DONE):
++                if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA)
++                        && !(p_CcKeyAndNextEngineParamsTmp[i].shadowAction
++                                & UPDATE_NIA_ENQ_WITHOUT_DMA))
++                {
++                    tmpReg32 = GET_UINT32(p_AdTmp->nia);
++                    if ((tmpReg32 & GET_NIA_BMI_AC_ENQ_FRAME(h_FmPcd))
++                            != GET_NIA_BMI_AC_ENQ_FRAME(h_FmPcd))
++                        RETURN_ERROR(
++                                MAJOR,
++                                E_INVALID_STATE,
++                                ("Next engine was previously assigned not as PCD_DONE"));
++                    tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA;
++                    WRITE_UINT32(p_AdTmp->nia, tmpReg32);
++                    p_CcKeyAndNextEngineParamsTmp[i].shadowAction |=
++                            requiredAction;
++                }
++                break;
++
++            default:
++                break;
++        }
++    }
++
++    return E_OK;
++}
++
++static t_Error SetRequiredAction(
++        t_Handle h_FmPcd, uint32_t requiredAction,
++        t_FmPcdCcKeyAndNextEngineParams *p_CcKeyAndNextEngineParamsTmp,
++        t_Handle h_AdTmp, uint16_t numOfEntries, t_Handle h_Tree)
++{
++    t_Error err = SetRequiredAction1(h_FmPcd, requiredAction,
++                                     p_CcKeyAndNextEngineParamsTmp, h_AdTmp,
++                                     numOfEntries, h_Tree);
++    if (err != E_OK)
++        return err;
++    return SetRequiredAction1(h_FmPcd, UPDATE_CC_SHADOW_CLEAR,
++                              p_CcKeyAndNextEngineParamsTmp, h_AdTmp,
++                              numOfEntries, h_Tree);
++}
++
++static t_Error ReleaseModifiedDataStructure(
++        t_Handle h_FmPcd, t_List *h_FmPcdOldPointersLst,
++        t_List *h_FmPcdNewPointersLst,
++        t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalParams,
++        bool useShadowStructs)
++{
++    t_List *p_Pos;
++    t_Error err = E_OK;
++    t_CcNodeInformation ccNodeInfo, *p_CcNodeInformation;
++    t_Handle h_Muram;
++    t_FmPcdCcNode *p_FmPcdCcNextNode, *p_FmPcdCcWorkingOnNode;
++    t_List *p_UpdateLst;
++    uint32_t intFlags;
++
++    SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(p_AdditionalParams->h_CurrentNode,
++                              E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(h_FmPcdOldPointersLst, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(h_FmPcdNewPointersLst, E_INVALID_HANDLE);
++
++    /* We don't update subtree of the new node with new tree because it was done in the previous stage */
++    if (p_AdditionalParams->h_NodeForAdd)
++    {
++        p_FmPcdCcNextNode = (t_FmPcdCcNode*)p_AdditionalParams->h_NodeForAdd;
++
++        if (!p_AdditionalParams->tree)
++            p_UpdateLst = &p_FmPcdCcNextNode->ccPrevNodesLst;
++        else
++            p_UpdateLst = &p_FmPcdCcNextNode->ccTreeIdLst;
++
++        p_CcNodeInformation = FindNodeInfoInReleventLst(
++                p_UpdateLst, p_AdditionalParams->h_CurrentNode,
++                p_FmPcdCcNextNode->h_Spinlock);
++
++        if (p_CcNodeInformation)
++            p_CcNodeInformation->index++;
++        else
++        {
++            memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++            ccNodeInfo.h_CcNode = (t_Handle)p_AdditionalParams->h_CurrentNode;
++            ccNodeInfo.index = 1;
++            EnqueueNodeInfoToRelevantLst(p_UpdateLst, &ccNodeInfo,
++                                         p_FmPcdCcNextNode->h_Spinlock);
++        }
++        if (p_AdditionalParams->h_ManipForAdd)
++        {
++            p_CcNodeInformation = FindNodeInfoInReleventLst(
++                    FmPcdManipGetNodeLstPointedOnThisManip(
++                            p_AdditionalParams->h_ManipForAdd),
++                    p_AdditionalParams->h_CurrentNode,
++                    FmPcdManipGetSpinlock(p_AdditionalParams->h_ManipForAdd));
++
++            if (p_CcNodeInformation)
++                p_CcNodeInformation->index++;
++            else
++            {
++                memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++                ccNodeInfo.h_CcNode =
++                        (t_Handle)p_AdditionalParams->h_CurrentNode;
++                ccNodeInfo.index = 1;
++                EnqueueNodeInfoToRelevantLst(
++                        FmPcdManipGetNodeLstPointedOnThisManip(
++                                p_AdditionalParams->h_ManipForAdd),
++                        &ccNodeInfo,
++                        FmPcdManipGetSpinlock(
++                                p_AdditionalParams->h_ManipForAdd));
++            }
++        }
++    }
++
++    if (p_AdditionalParams->h_NodeForRmv)
++    {
++        p_FmPcdCcNextNode = (t_FmPcdCcNode*)p_AdditionalParams->h_NodeForRmv;
++
++        if (!p_AdditionalParams->tree)
++        {
++            p_UpdateLst = &p_FmPcdCcNextNode->ccPrevNodesLst;
++            p_FmPcdCcWorkingOnNode =
++                    (t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode);
++
++            for (p_Pos = LIST_FIRST(&p_FmPcdCcWorkingOnNode->ccTreesLst);
++                    p_Pos != (&p_FmPcdCcWorkingOnNode->ccTreesLst); p_Pos =
++                            LIST_NEXT(p_Pos))
++            {
++                p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos);
++
++                ASSERT_COND(p_CcNodeInformation->h_CcNode);
++
++                err =
++                        SetRequiredAction(
++                                h_FmPcd,
++                                UPDATE_CC_WITH_DELETE_TREE,
++                                &((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams[p_AdditionalParams->savedKeyIndex],
++                                PTR_MOVE(((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_AdTable, p_AdditionalParams->savedKeyIndex*FM_PCD_CC_AD_ENTRY_SIZE),
++                                1, p_CcNodeInformation->h_CcNode);
++            }
++        }
++        else
++        {
++            p_UpdateLst = &p_FmPcdCcNextNode->ccTreeIdLst;
++
++            err =
++                    SetRequiredAction(
++                            h_FmPcd,
++                            UPDATE_CC_WITH_DELETE_TREE,
++                            &((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams[p_AdditionalParams->savedKeyIndex],
++                            UINT_TO_PTR(((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->ccTreeBaseAddr + p_AdditionalParams->savedKeyIndex*FM_PCD_CC_AD_ENTRY_SIZE),
++                            1, p_AdditionalParams->h_CurrentNode);
++        }
++        if (err)
++            return err;
++
++        /* We remove from the subtree of the removed node tree because it wasn't done in the previous stage
++         Update ccPrevNodesLst or ccTreeIdLst of the removed node
++         Update of the node owner */
++        p_CcNodeInformation = FindNodeInfoInReleventLst(
++                p_UpdateLst, p_AdditionalParams->h_CurrentNode,
++                p_FmPcdCcNextNode->h_Spinlock);
++
++        ASSERT_COND(p_CcNodeInformation);
++        ASSERT_COND(p_CcNodeInformation->index);
++
++        p_CcNodeInformation->index--;
++
++        if (p_CcNodeInformation->index == 0)
++            DequeueNodeInfoFromRelevantLst(p_UpdateLst,
++                                           p_AdditionalParams->h_CurrentNode,
++                                           p_FmPcdCcNextNode->h_Spinlock);
++
++        UpdateNodeOwner(p_FmPcdCcNextNode, FALSE);
++
++        if (p_AdditionalParams->h_ManipForRmv)
++        {
++            p_CcNodeInformation = FindNodeInfoInReleventLst(
++                    FmPcdManipGetNodeLstPointedOnThisManip(
++                            p_AdditionalParams->h_ManipForRmv),
++                    p_AdditionalParams->h_CurrentNode,
++                    FmPcdManipGetSpinlock(p_AdditionalParams->h_ManipForRmv));
++
++            ASSERT_COND(p_CcNodeInformation);
++            ASSERT_COND(p_CcNodeInformation->index);
++
++            p_CcNodeInformation->index--;
++
++            if (p_CcNodeInformation->index == 0)
++                DequeueNodeInfoFromRelevantLst(
++                        FmPcdManipGetNodeLstPointedOnThisManip(
++                                p_AdditionalParams->h_ManipForRmv),
++                        p_AdditionalParams->h_CurrentNode,
++                        FmPcdManipGetSpinlock(
++                                p_AdditionalParams->h_ManipForRmv));
++        }
++    }
++
++    if (p_AdditionalParams->h_ManipForRmv)
++        FmPcdManipUpdateOwner(p_AdditionalParams->h_ManipForRmv, FALSE);
++
++    if (p_AdditionalParams->p_StatsObjForRmv)
++        PutStatsObj((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode),
++                    p_AdditionalParams->p_StatsObjForRmv);
++
++#if (DPAA_VERSION >= 11)
++    if (p_AdditionalParams->h_FrmReplicForRmv)
++        FrmReplicGroupUpdateOwner(p_AdditionalParams->h_FrmReplicForRmv,
++                                  FALSE/* remove */);
++#endif /* (DPAA_VERSION >= 11) */
++
++    if (!useShadowStructs)
++    {
++        h_Muram = FmPcdGetMuramHandle(h_FmPcd);
++        ASSERT_COND(h_Muram);
++
++        if ((p_AdditionalParams->tree && !((t_FmPcd *)h_FmPcd)->p_CcShadow)
++                || (!p_AdditionalParams->tree
++                        && !((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->maxNumOfKeys))
++        {
++            /* We release new AD which was allocated and updated for copy from to actual AD */
++            for (p_Pos = LIST_FIRST(h_FmPcdNewPointersLst);
++                    p_Pos != (h_FmPcdNewPointersLst); p_Pos = LIST_NEXT(p_Pos))
++            {
++
++                p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos);
++                ASSERT_COND(p_CcNodeInformation->h_CcNode);
++                FM_MURAM_FreeMem(h_Muram, p_CcNodeInformation->h_CcNode);
++            }
++        }
++
++        /* Free Old data structure if it has to be freed - new data structure was allocated*/
++        if (p_AdditionalParams->p_AdTableOld)
++            FM_MURAM_FreeMem(h_Muram, p_AdditionalParams->p_AdTableOld);
++
++        if (p_AdditionalParams->p_KeysMatchTableOld)
++            FM_MURAM_FreeMem(h_Muram, p_AdditionalParams->p_KeysMatchTableOld);
++    }
++
++    /* Update current modified node with changed fields if it's required*/
++    if (!p_AdditionalParams->tree)
++    {
++        if (p_AdditionalParams->p_AdTableNew)
++            ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_AdTable =
++                    p_AdditionalParams->p_AdTableNew;
++
++        if (p_AdditionalParams->p_KeysMatchTableNew)
++            ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_KeysMatchTable =
++                    p_AdditionalParams->p_KeysMatchTableNew;
++
++        /* Locking node's spinlock before updating 'keys and next engine' structure,
++         as it maybe used to retrieve keys statistics */
++        intFlags =
++                XX_LockIntrSpinlock(
++                        ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_Spinlock);
++
++        ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->numOfKeys =
++                p_AdditionalParams->numOfKeys;
++
++        memcpy(((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams,
++               &p_AdditionalParams->keyAndNextEngineParams,
++               sizeof(t_FmPcdCcKeyAndNextEngineParams) * (CC_MAX_NUM_OF_KEYS));
++
++        XX_UnlockIntrSpinlock(
++                ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_Spinlock,
++                intFlags);
++    }
++    else
++    {
++        uint8_t numEntries =
++                ((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->numOfEntries;
++        ASSERT_COND(numEntries < FM_PCD_MAX_NUM_OF_CC_GROUPS);
++        memcpy(&((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams,
++               &p_AdditionalParams->keyAndNextEngineParams,
++               sizeof(t_FmPcdCcKeyAndNextEngineParams) * numEntries);
++    }
++
++    ReleaseLst(h_FmPcdOldPointersLst);
++    ReleaseLst(h_FmPcdNewPointersLst);
++
++    XX_Free(p_AdditionalParams);
++
++    return E_OK;
++}
++
++static t_Handle BuildNewAd(
++        t_Handle h_Ad,
++        t_FmPcdModifyCcKeyAdditionalParams *p_FmPcdModifyCcKeyAdditionalParams,
++        t_FmPcdCcNode *p_CcNode,
++        t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams)
++{
++    t_FmPcdCcNode *p_FmPcdCcNodeTmp;
++    t_Handle h_OrigAd = NULL;
++
++    p_FmPcdCcNodeTmp = (t_FmPcdCcNode*)XX_Malloc(sizeof(t_FmPcdCcNode));
++    if (!p_FmPcdCcNodeTmp)
++    {
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_FmPcdCcNodeTmp"));
++        return NULL;
++    }
++    memset(p_FmPcdCcNodeTmp, 0, sizeof(t_FmPcdCcNode));
++
++    p_FmPcdCcNodeTmp->numOfKeys = p_FmPcdModifyCcKeyAdditionalParams->numOfKeys;
++    p_FmPcdCcNodeTmp->h_KeysMatchTable =
++            p_FmPcdModifyCcKeyAdditionalParams->p_KeysMatchTableNew;
++    p_FmPcdCcNodeTmp->h_AdTable =
++            p_FmPcdModifyCcKeyAdditionalParams->p_AdTableNew;
++
++    p_FmPcdCcNodeTmp->lclMask = p_CcNode->lclMask;
++    p_FmPcdCcNodeTmp->parseCode = p_CcNode->parseCode;
++    p_FmPcdCcNodeTmp->offset = p_CcNode->offset;
++    p_FmPcdCcNodeTmp->prsArrayOffset = p_CcNode->prsArrayOffset;
++    p_FmPcdCcNodeTmp->ctrlFlow = p_CcNode->ctrlFlow;
++    p_FmPcdCcNodeTmp->ccKeySizeAccExtraction = p_CcNode->ccKeySizeAccExtraction;
++    p_FmPcdCcNodeTmp->sizeOfExtraction = p_CcNode->sizeOfExtraction;
++    p_FmPcdCcNodeTmp->glblMaskSize = p_CcNode->glblMaskSize;
++    p_FmPcdCcNodeTmp->p_GlblMask = p_CcNode->p_GlblMask;
++
++    if (p_FmPcdCcNextEngineParams->nextEngine == e_FM_PCD_CC)
++    {
++        if (p_FmPcdCcNextEngineParams->h_Manip)
++        {
++            h_OrigAd = p_CcNode->h_Ad;
++            if (AllocAndFillAdForContLookupManip(
++                    p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode)
++                    != E_OK)
++            {
++                REPORT_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++                XX_Free(p_FmPcdCcNodeTmp);
++                return NULL;
++            }
++        }
++        FillAdOfTypeContLookup(h_Ad, NULL, p_CcNode->h_FmPcd, p_FmPcdCcNodeTmp,
++                               h_OrigAd ? NULL : p_FmPcdCcNextEngineParams->h_Manip, NULL);
++    }
++
++#if (DPAA_VERSION >= 11)
++    if ((p_FmPcdCcNextEngineParams->nextEngine == e_FM_PCD_FR)
++            && (p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic))
++    {
++        FillAdOfTypeContLookup(
++                h_Ad, NULL, p_CcNode->h_FmPcd, p_FmPcdCcNodeTmp,
++                p_FmPcdCcNextEngineParams->h_Manip,
++                p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic);
++    }
++#endif /* (DPAA_VERSION >= 11) */
++
++    XX_Free(p_FmPcdCcNodeTmp);
++
++    return E_OK;
++}
++
++static t_Error DynamicChangeHc(
++        t_Handle h_FmPcd, t_List *h_OldPointersLst, t_List *h_NewPointersLst,
++        t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalParams,
++        bool useShadowStructs)
++{
++    t_List *p_PosOld, *p_PosNew;
++    uint32_t oldAdAddrOffset, newAdAddrOffset;
++    uint16_t i = 0;
++    t_Error err = E_OK;
++    uint8_t numOfModifiedPtr;
++
++    ASSERT_COND(h_FmPcd);
++    ASSERT_COND(h_OldPointersLst);
++    ASSERT_COND(h_NewPointersLst);
++
++    numOfModifiedPtr = (uint8_t)LIST_NumOfObjs(h_OldPointersLst);
++
++    if (numOfModifiedPtr)
++    {
++        p_PosNew = LIST_FIRST(h_NewPointersLst);
++        p_PosOld = LIST_FIRST(h_OldPointersLst);
++
++        /* Retrieve address of new AD */
++        newAdAddrOffset = FmPcdCcGetNodeAddrOffsetFromNodeInfo(h_FmPcd,
++                                                               p_PosNew);
++        if (newAdAddrOffset == (uint32_t)ILLEGAL_BASE)
++        {
++            ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst,
++                                         h_NewPointersLst,
++                                         p_AdditionalParams, useShadowStructs);
++            RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("New AD address"));
++        }
++
++        for (i = 0; i < numOfModifiedPtr; i++)
++        {
++            /* Retrieve address of current AD */
++            oldAdAddrOffset = FmPcdCcGetNodeAddrOffsetFromNodeInfo(h_FmPcd,
++                                                                   p_PosOld);
++            if (oldAdAddrOffset == (uint32_t)ILLEGAL_BASE)
++            {
++                ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst,
++                                             h_NewPointersLst,
++                                             p_AdditionalParams,
++                                             useShadowStructs);
++                RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Old AD address"));
++            }
++
++            /* Invoke host command to copy from new AD to old AD */
++            err = FmHcPcdCcDoDynamicChange(((t_FmPcd *)h_FmPcd)->h_Hc,
++                                           oldAdAddrOffset, newAdAddrOffset);
++            if (err)
++            {
++                ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst,
++                                             h_NewPointersLst,
++                                             p_AdditionalParams,
++                                             useShadowStructs);
++                RETURN_ERROR(
++                        MAJOR,
++                        err,
++                        ("For part of nodes changes are done - situation is danger"));
++            }
++
++            p_PosOld = LIST_NEXT(p_PosOld);
++        }
++    }
++    return E_OK;
++}
++
++static t_Error DoDynamicChange(
++        t_Handle h_FmPcd, t_List *h_OldPointersLst, t_List *h_NewPointersLst,
++        t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalParams,
++        bool useShadowStructs)
++{
++    t_FmPcdCcNode *p_CcNode =
++            (t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode);
++    t_List *p_PosNew;
++    t_CcNodeInformation *p_CcNodeInfo;
++    t_FmPcdCcNextEngineParams nextEngineParams;
++    t_Handle h_Ad;
++    uint32_t keySize;
++    t_Error err = E_OK;
++    uint8_t numOfModifiedPtr;
++
++    ASSERT_COND(h_FmPcd);
++
++    memset(&nextEngineParams, 0, sizeof(t_FmPcdCcNextEngineParams));
++
++    numOfModifiedPtr = (uint8_t)LIST_NumOfObjs(h_OldPointersLst);
++
++    if (numOfModifiedPtr)
++    {
++
++        p_PosNew = LIST_FIRST(h_NewPointersLst);
++
++        /* Invoke host-command to copy from the new Ad to existing Ads */
++        err = DynamicChangeHc(h_FmPcd, h_OldPointersLst, h_NewPointersLst,
++                              p_AdditionalParams, useShadowStructs);
++        if (err)
++            RETURN_ERROR(MAJOR, err, NO_MSG);
++
++		if (useShadowStructs)
++		{
++			/* When the host-command above has ended, the old structures are 'free'and we can update
++			 them by copying from the new shadow structures. */
++			if (p_CcNode->lclMask)
++				keySize = (uint32_t)(2 * p_CcNode->ccKeySizeAccExtraction);
++			else
++				keySize = p_CcNode->ccKeySizeAccExtraction;
++
++			IO2IOCpy32(p_AdditionalParams->p_KeysMatchTableOld,
++					   p_AdditionalParams->p_KeysMatchTableNew,
++					   p_CcNode->maxNumOfKeys * keySize * sizeof(uint8_t));
++
++			IO2IOCpy32(
++					p_AdditionalParams->p_AdTableOld,
++					p_AdditionalParams->p_AdTableNew,
++					(uint32_t)((p_CcNode->maxNumOfKeys + 1)
++							* FM_PCD_CC_AD_ENTRY_SIZE));
++
++			/* Retrieve the address of the allocated Ad */
++			p_CcNodeInfo = CC_NODE_F_OBJECT(p_PosNew);
++			h_Ad = p_CcNodeInfo->h_CcNode;
++
++			/* Build a new Ad that holds the old (now updated) structures */
++			p_AdditionalParams->p_KeysMatchTableNew =
++					p_AdditionalParams->p_KeysMatchTableOld;
++			p_AdditionalParams->p_AdTableNew = p_AdditionalParams->p_AdTableOld;
++
++			nextEngineParams.nextEngine = e_FM_PCD_CC;
++			nextEngineParams.params.ccParams.h_CcNode = (t_Handle)p_CcNode;
++
++			BuildNewAd(h_Ad, p_AdditionalParams, p_CcNode, &nextEngineParams);
++
++			/* HC to copy from the new Ad (old updated structures) to current Ad (uses shadow structures) */
++			err = DynamicChangeHc(h_FmPcd, h_OldPointersLst, h_NewPointersLst,
++								  p_AdditionalParams, useShadowStructs);
++                        if (err)
++                            RETURN_ERROR(MAJOR, err, NO_MSG);
++		}
++    }
++
++    err = ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst,
++                                       h_NewPointersLst,
++                                       p_AdditionalParams, useShadowStructs);
++    if (err)
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++
++    return E_OK;
++}
++
++#ifdef FM_CAPWAP_SUPPORT
++static bool IsCapwapApplSpecific(t_Handle h_Node)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_Node;
++    bool isManipForCapwapApplSpecificBuild = FALSE;
++    int i = 0;
++
++    ASSERT_COND(h_Node);
++    /* assumption that this function called only for INDEXED_FLOW_ID - so no miss*/
++    for (i = 0; i < p_CcNode->numOfKeys; i++)
++    {
++        if ( p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip &&
++                FmPcdManipIsCapwapApplSpecific(p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip))
++        {
++            isManipForCapwapApplSpecificBuild = TRUE;
++            break;
++        }
++    }
++    return isManipForCapwapApplSpecificBuild;
++
++}
++#endif /* FM_CAPWAP_SUPPORT */
++
++static t_Error CcUpdateParam(
++        t_Handle h_FmPcd, t_Handle h_PcdParams, t_Handle h_FmPort,
++        t_FmPcdCcKeyAndNextEngineParams *p_CcKeyAndNextEngineParams,
++        uint16_t numOfEntries, t_Handle h_Ad, bool validate, uint16_t level,
++        t_Handle h_FmTree, bool modify)
++{
++    t_FmPcdCcNode *p_CcNode;
++    t_Error err;
++    uint16_t tmp = 0;
++    int i = 0;
++    t_FmPcdCcTree *p_CcTree = (t_FmPcdCcTree *)h_FmTree;
++
++    level++;
++
++    if (p_CcTree->h_IpReassemblyManip)
++    {
++        err = FmPcdManipUpdate(h_FmPcd, h_PcdParams, h_FmPort,
++                               p_CcTree->h_IpReassemblyManip, NULL, validate,
++                               level, h_FmTree, modify);
++        if (err)
++            RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    if (p_CcTree->h_CapwapReassemblyManip)
++    {
++        err = FmPcdManipUpdate(h_FmPcd, h_PcdParams, h_FmPort,
++                               p_CcTree->h_CapwapReassemblyManip, NULL, validate,
++                               level, h_FmTree, modify);
++        if (err)
++            RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    if (numOfEntries)
++    {
++        for (i = 0; i < numOfEntries; i++)
++        {
++            if (i == 0)
++                h_Ad = PTR_MOVE(h_Ad, i*FM_PCD_CC_AD_ENTRY_SIZE);
++            else
++                h_Ad = PTR_MOVE(h_Ad, FM_PCD_CC_AD_ENTRY_SIZE);
++
++            if (p_CcKeyAndNextEngineParams[i].nextEngineParams.nextEngine
++                    == e_FM_PCD_CC)
++            {
++                p_CcNode =
++                        p_CcKeyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode;
++                ASSERT_COND(p_CcNode);
++
++                if (p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip)
++                {
++                    err =
++                            FmPcdManipUpdate(
++                                    h_FmPcd,
++                                    NULL,
++                                    h_FmPort,
++                                    p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip,
++                                    h_Ad, validate, level, h_FmTree, modify);
++                    if (err)
++                        RETURN_ERROR(MAJOR, err, NO_MSG);
++                }
++
++                if (p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine
++                        != e_FM_PCD_INVALID)
++                    tmp = (uint8_t)(p_CcNode->numOfKeys + 1);
++                else
++                    tmp = p_CcNode->numOfKeys;
++
++                err = CcUpdateParam(h_FmPcd, h_PcdParams, h_FmPort,
++                                    p_CcNode->keyAndNextEngineParams, tmp,
++                                    p_CcNode->h_AdTable, validate, level,
++                                    h_FmTree, modify);
++                if (err)
++                    RETURN_ERROR(MAJOR, err, NO_MSG);
++            }
++            else
++            {
++                if (p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip)
++                {
++                    err =
++                            FmPcdManipUpdate(
++                                    h_FmPcd,
++                                    NULL,
++                                    h_FmPort,
++                                    p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip,
++                                    h_Ad, validate, level, h_FmTree, modify);
++                    if (err)
++                        RETURN_ERROR(MAJOR, err, NO_MSG);
++                }
++            }
++        }
++    }
++
++    return E_OK;
++}
++
++static ccPrivateInfo_t IcDefineCode(t_FmPcdCcNodeParams *p_CcNodeParam)
++{
++    switch (p_CcNodeParam->extractCcParams.extractNonHdr.action)
++    {
++        case (e_FM_PCD_ACTION_EXACT_MATCH):
++            switch (p_CcNodeParam->extractCcParams.extractNonHdr.src)
++            {
++                case (e_FM_PCD_EXTRACT_FROM_KEY):
++                    return CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH;
++                case (e_FM_PCD_EXTRACT_FROM_HASH):
++                    return CC_PRIVATE_INFO_IC_HASH_EXACT_MATCH;
++                default:
++                    return CC_PRIVATE_INFO_NONE;
++            }
++
++        case (e_FM_PCD_ACTION_INDEXED_LOOKUP):
++            switch (p_CcNodeParam->extractCcParams.extractNonHdr.src)
++            {
++                case (e_FM_PCD_EXTRACT_FROM_HASH):
++                    return CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP;
++                case (e_FM_PCD_EXTRACT_FROM_FLOW_ID):
++                    return CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP;
++                default:
++                    return CC_PRIVATE_INFO_NONE;
++            }
++
++        default:
++            break;
++    }
++
++    return CC_PRIVATE_INFO_NONE;
++}
++
++static t_CcNodeInformation * DequeueAdditionalInfoFromRelevantLst(
++        t_List *p_List)
++{
++    t_CcNodeInformation *p_CcNodeInfo = NULL;
++
++    if (!LIST_IsEmpty(p_List))
++    {
++        p_CcNodeInfo = CC_NODE_F_OBJECT(p_List->p_Next);
++        LIST_DelAndInit(&p_CcNodeInfo->node);
++    }
++
++    return p_CcNodeInfo;
++}
++
++void ReleaseLst(t_List *p_List)
++{
++    t_CcNodeInformation *p_CcNodeInfo = NULL;
++
++    if (!LIST_IsEmpty(p_List))
++    {
++        p_CcNodeInfo = DequeueAdditionalInfoFromRelevantLst(p_List);
++        while (p_CcNodeInfo)
++        {
++            XX_Free(p_CcNodeInfo);
++            p_CcNodeInfo = DequeueAdditionalInfoFromRelevantLst(p_List);
++        }
++    }
++
++    LIST_Del(p_List);
++}
++
++static void DeleteNode(t_FmPcdCcNode *p_CcNode)
++{
++    uint32_t i;
++
++    if (!p_CcNode)
++        return;
++
++    if (p_CcNode->p_GlblMask)
++    {
++        XX_Free(p_CcNode->p_GlblMask);
++        p_CcNode->p_GlblMask = NULL;
++    }
++
++    if (p_CcNode->h_KeysMatchTable)
++    {
++        FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd),
++                         p_CcNode->h_KeysMatchTable);
++        p_CcNode->h_KeysMatchTable = NULL;
++    }
++
++    if (p_CcNode->h_AdTable)
++    {
++        FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd),
++                         p_CcNode->h_AdTable);
++        p_CcNode->h_AdTable = NULL;
++    }
++
++    if (p_CcNode->h_Ad)
++    {
++        FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd),
++                         p_CcNode->h_Ad);
++        p_CcNode->h_Ad = NULL;
++        p_CcNode->h_TmpAd = NULL;
++    }
++
++    if (p_CcNode->h_StatsFLRs)
++    {
++        FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd),
++                         p_CcNode->h_StatsFLRs);
++        p_CcNode->h_StatsFLRs = NULL;
++    }
++
++    if (p_CcNode->h_Spinlock)
++    {
++        XX_FreeSpinlock(p_CcNode->h_Spinlock);
++        p_CcNode->h_Spinlock = NULL;
++    }
++
++    /* Restore the original counters pointer instead of the mutual pointer (mutual to all hash buckets) */
++    if (p_CcNode->isHashBucket
++            && (p_CcNode->statisticsMode != e_FM_PCD_CC_STATS_MODE_NONE))
++        p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].p_StatsObj->h_StatsCounters =
++                p_CcNode->h_PrivMissStatsCounters;
++
++    /* Releasing all currently used statistics objects, including 'miss' entry */
++    for (i = 0; i < p_CcNode->numOfKeys + 1; i++)
++        if (p_CcNode->keyAndNextEngineParams[i].p_StatsObj)
++            PutStatsObj(p_CcNode,
++                        p_CcNode->keyAndNextEngineParams[i].p_StatsObj);
++
++    if (!LIST_IsEmpty(&p_CcNode->availableStatsLst))
++    {
++        t_Handle h_FmMuram = FmPcdGetMuramHandle(p_CcNode->h_FmPcd);
++        ASSERT_COND(h_FmMuram);
++
++        FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram);
++    }
++
++    LIST_Del(&p_CcNode->availableStatsLst);
++
++    ReleaseLst(&p_CcNode->ccPrevNodesLst);
++    ReleaseLst(&p_CcNode->ccTreeIdLst);
++    ReleaseLst(&p_CcNode->ccTreesLst);
++
++    XX_Free(p_CcNode);
++}
++
++static void DeleteTree(t_FmPcdCcTree *p_FmPcdTree, t_FmPcd *p_FmPcd)
++{
++    if (p_FmPcdTree)
++    {
++        if (p_FmPcdTree->ccTreeBaseAddr)
++        {
++            FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_FmPcd),
++                             UINT_TO_PTR(p_FmPcdTree->ccTreeBaseAddr));
++            p_FmPcdTree->ccTreeBaseAddr = 0;
++        }
++
++        ReleaseLst(&p_FmPcdTree->fmPortsLst);
++
++        XX_Free(p_FmPcdTree);
++    }
++}
++
++static void GetCcExtractKeySize(uint8_t parseCodeRealSize,
++                                uint8_t *parseCodeCcSize)
++{
++    if ((parseCodeRealSize > 0) && (parseCodeRealSize < 2))
++        *parseCodeCcSize = 1;
++    else
++        if (parseCodeRealSize == 2)
++            *parseCodeCcSize = 2;
++        else
++            if ((parseCodeRealSize > 2) && (parseCodeRealSize <= 4))
++                *parseCodeCcSize = 4;
++            else
++                if ((parseCodeRealSize > 4) && (parseCodeRealSize <= 8))
++                    *parseCodeCcSize = 8;
++                else
++                    if ((parseCodeRealSize > 8) && (parseCodeRealSize <= 16))
++                        *parseCodeCcSize = 16;
++                    else
++                        if ((parseCodeRealSize > 16)
++                                && (parseCodeRealSize <= 24))
++                            *parseCodeCcSize = 24;
++                        else
++                            if ((parseCodeRealSize > 24)
++                                    && (parseCodeRealSize <= 32))
++                                *parseCodeCcSize = 32;
++                            else
++                                if ((parseCodeRealSize > 32)
++                                        && (parseCodeRealSize <= 40))
++                                    *parseCodeCcSize = 40;
++                                else
++                                    if ((parseCodeRealSize > 40)
++                                            && (parseCodeRealSize <= 48))
++                                        *parseCodeCcSize = 48;
++                                    else
++                                        if ((parseCodeRealSize > 48)
++                                                && (parseCodeRealSize <= 56))
++                                            *parseCodeCcSize = 56;
++                                        else
++                                            *parseCodeCcSize = 0;
++}
++
++static void GetSizeHeaderField(e_NetHeaderType hdr, t_FmPcdFields field,
++		                       uint8_t *parseCodeRealSize)
++{
++    switch (hdr)
++    {
++        case (HEADER_TYPE_ETH):
++            switch (field.eth)
++            {
++                case (NET_HEADER_FIELD_ETH_DA):
++                    *parseCodeRealSize = 6;
++                    break;
++
++                case (NET_HEADER_FIELD_ETH_SA):
++                    *parseCodeRealSize = 6;
++                    break;
++
++                case (NET_HEADER_FIELD_ETH_TYPE):
++                    *parseCodeRealSize = 2;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported1"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_PPPoE):
++            switch (field.pppoe)
++            {
++                case (NET_HEADER_FIELD_PPPoE_PID):
++                    *parseCodeRealSize = 2;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported1"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_VLAN):
++            switch (field.vlan)
++            {
++                case (NET_HEADER_FIELD_VLAN_TCI):
++                    *parseCodeRealSize = 2;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported2"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_MPLS):
++            switch (field.mpls)
++            {
++                case (NET_HEADER_FIELD_MPLS_LABEL_STACK):
++                    *parseCodeRealSize = 4;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported3"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_IPv4):
++            switch (field.ipv4)
++            {
++                case (NET_HEADER_FIELD_IPv4_DST_IP):
++                case (NET_HEADER_FIELD_IPv4_SRC_IP):
++                    *parseCodeRealSize = 4;
++                    break;
++
++                case (NET_HEADER_FIELD_IPv4_TOS):
++                case (NET_HEADER_FIELD_IPv4_PROTO):
++                    *parseCodeRealSize = 1;
++                    break;
++
++                case (NET_HEADER_FIELD_IPv4_DST_IP
++                        | NET_HEADER_FIELD_IPv4_SRC_IP):
++                    *parseCodeRealSize = 8;
++                    break;
++
++                case (NET_HEADER_FIELD_IPv4_TTL):
++                    *parseCodeRealSize = 1;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported4"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_IPv6):
++            switch (field.ipv6)
++            {
++                case (NET_HEADER_FIELD_IPv6_VER | NET_HEADER_FIELD_IPv6_FL
++                        | NET_HEADER_FIELD_IPv6_TC):
++                    *parseCodeRealSize = 4;
++                    break;
++
++                case (NET_HEADER_FIELD_IPv6_NEXT_HDR):
++                case (NET_HEADER_FIELD_IPv6_HOP_LIMIT):
++                    *parseCodeRealSize = 1;
++                    break;
++
++                case (NET_HEADER_FIELD_IPv6_DST_IP):
++                case (NET_HEADER_FIELD_IPv6_SRC_IP):
++                    *parseCodeRealSize = 16;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported5"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_IP):
++            switch (field.ip)
++            {
++                case (NET_HEADER_FIELD_IP_DSCP):
++                case (NET_HEADER_FIELD_IP_PROTO):
++                    *parseCodeRealSize = 1;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported5"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_GRE):
++            switch (field.gre)
++            {
++                case (NET_HEADER_FIELD_GRE_TYPE):
++                    *parseCodeRealSize = 2;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported6"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_MINENCAP):
++            switch (field.minencap)
++            {
++                case (NET_HEADER_FIELD_MINENCAP_TYPE):
++                    *parseCodeRealSize = 1;
++                    break;
++
++                case (NET_HEADER_FIELD_MINENCAP_DST_IP):
++                case (NET_HEADER_FIELD_MINENCAP_SRC_IP):
++                    *parseCodeRealSize = 4;
++                    break;
++
++                case (NET_HEADER_FIELD_MINENCAP_SRC_IP
++                        | NET_HEADER_FIELD_MINENCAP_DST_IP):
++                    *parseCodeRealSize = 8;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported7"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_TCP):
++            switch (field.tcp)
++            {
++                case (NET_HEADER_FIELD_TCP_PORT_SRC):
++                case (NET_HEADER_FIELD_TCP_PORT_DST):
++                    *parseCodeRealSize = 2;
++                    break;
++
++                case (NET_HEADER_FIELD_TCP_PORT_SRC
++                        | NET_HEADER_FIELD_TCP_PORT_DST):
++                    *parseCodeRealSize = 4;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported8"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        case (HEADER_TYPE_UDP):
++            switch (field.udp)
++            {
++                case (NET_HEADER_FIELD_UDP_PORT_SRC):
++                case (NET_HEADER_FIELD_UDP_PORT_DST):
++                    *parseCodeRealSize = 2;
++                    break;
++
++                case (NET_HEADER_FIELD_UDP_PORT_SRC
++                        | NET_HEADER_FIELD_UDP_PORT_DST):
++                    *parseCodeRealSize = 4;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported9"));
++                    *parseCodeRealSize = CC_SIZE_ILLEGAL;
++                    break;
++            }
++            break;
++
++        default:
++            REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported10"));
++            *parseCodeRealSize = CC_SIZE_ILLEGAL;
++            break;
++    }
++}
++
++t_Error ValidateNextEngineParams(
++        t_Handle h_FmPcd, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams,
++        e_FmPcdCcStatsMode statsMode)
++{
++    uint16_t absoluteProfileId;
++    t_Error err = E_OK;
++    uint8_t relativeSchemeId;
++
++    if ((statsMode == e_FM_PCD_CC_STATS_MODE_NONE)
++            && (p_FmPcdCcNextEngineParams->statisticsEn))
++        RETURN_ERROR(
++                MAJOR,
++                E_CONFLICT,
++                ("Statistics are requested for a key, but statistics mode was set"
++                "to 'NONE' upon initialization"));
++
++    switch (p_FmPcdCcNextEngineParams->nextEngine)
++    {
++        case (e_FM_PCD_INVALID):
++            err = E_NOT_SUPPORTED;
++            break;
++
++        case (e_FM_PCD_DONE):
++            if ((p_FmPcdCcNextEngineParams->params.enqueueParams.action
++                    == e_FM_PCD_ENQ_FRAME)
++                    && p_FmPcdCcNextEngineParams->params.enqueueParams.overrideFqid)
++            {
++                if (!p_FmPcdCcNextEngineParams->params.enqueueParams.newFqid)
++                    RETURN_ERROR(
++                            MAJOR,
++                            E_CONFLICT,
++                            ("When overrideFqid is set, newFqid must not be zero"));
++                if (p_FmPcdCcNextEngineParams->params.enqueueParams.newFqid
++                        & ~0x00FFFFFF)
++                    RETURN_ERROR(
++                            MAJOR, E_INVALID_VALUE,
++                            ("fqidForCtrlFlow must be between 1 and 2^24-1"));
++            }
++            break;
++
++        case (e_FM_PCD_KG):
++            relativeSchemeId =
++                    FmPcdKgGetRelativeSchemeId(
++                            h_FmPcd,
++                            FmPcdKgGetSchemeId(
++                                    p_FmPcdCcNextEngineParams->params.kgParams.h_DirectScheme));
++            if (relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES)
++                RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG);
++            if (!FmPcdKgIsSchemeValidSw(
++                    p_FmPcdCcNextEngineParams->params.kgParams.h_DirectScheme))
++                RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                             ("not valid schemeIndex in KG next engine param"));
++            if (!KgIsSchemeAlwaysDirect(h_FmPcd, relativeSchemeId))
++                RETURN_ERROR(
++                        MAJOR,
++                        E_INVALID_STATE,
++                        ("CC Node may point only to a scheme that is always direct."));
++            break;
++
++        case (e_FM_PCD_PLCR):
++            if (p_FmPcdCcNextEngineParams->params.plcrParams.overrideParams)
++            {
++                /* if private policer profile, it may be uninitialized yet, therefore no checks are done at this stage */
++                if (p_FmPcdCcNextEngineParams->params.plcrParams.sharedProfile)
++                {
++                    err =
++                            FmPcdPlcrGetAbsoluteIdByProfileParams(
++                                    h_FmPcd,
++                                    e_FM_PCD_PLCR_SHARED,
++                                    NULL,
++                                    p_FmPcdCcNextEngineParams->params.plcrParams.newRelativeProfileId,
++                                    &absoluteProfileId);
++                    if (err)
++                        RETURN_ERROR(MAJOR, err,
++                                     ("Shared profile offset is out of range"));
++                    if (!FmPcdPlcrIsProfileValid(h_FmPcd, absoluteProfileId))
++                        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                                     ("Invalid profile"));
++                }
++            }
++            break;
++
++        case (e_FM_PCD_HASH):
++            p_FmPcdCcNextEngineParams->nextEngine = e_FM_PCD_CC;
++        case (e_FM_PCD_CC):
++            if (!p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode)
++                RETURN_ERROR(MAJOR, E_NULL_POINTER,
++                             ("handler to next Node is NULL"));
++            break;
++
++#if (DPAA_VERSION >= 11)
++        case (e_FM_PCD_FR):
++            if (!p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic)
++                err = E_NOT_SUPPORTED;
++            break;
++#endif /* (DPAA_VERSION >= 11) */
++
++        default:
++            RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                         ("Next engine is not correct"));
++    }
++
++
++    return err;
++}
++
++static uint8_t GetGenParseCode(e_FmPcdExtractFrom src,
++                               uint32_t offset, bool glblMask,
++                               uint8_t *parseArrayOffset, bool fromIc,
++                               ccPrivateInfo_t icCode)
++{
++    if (!fromIc)
++    {
++        switch (src)
++        {
++            case (e_FM_PCD_EXTRACT_FROM_FRAME_START):
++                if (glblMask)
++                    return CC_PC_GENERIC_WITH_MASK;
++                else
++                    return CC_PC_GENERIC_WITHOUT_MASK;
++
++            case (e_FM_PCD_EXTRACT_FROM_CURR_END_OF_PARSE):
++                *parseArrayOffset = CC_PC_PR_NEXT_HEADER_OFFSET;
++                if (offset)
++                    return CC_PR_OFFSET;
++                else
++                    return CC_PR_WITHOUT_OFFSET;
++
++            default:
++                REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 'extract from' src"));
++                return CC_PC_ILLEGAL;
++        }
++    }
++    else
++    {
++        switch (icCode)
++        {
++            case (CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH):
++                *parseArrayOffset = 0x50;
++                return CC_PC_GENERIC_IC_GMASK;
++
++            case (CC_PRIVATE_INFO_IC_HASH_EXACT_MATCH):
++                *parseArrayOffset = 0x48;
++                return CC_PC_GENERIC_IC_GMASK;
++
++            case (CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP):
++                *parseArrayOffset = 0x48;
++                return CC_PC_GENERIC_IC_HASH_INDEXED;
++
++            case (CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP):
++                *parseArrayOffset = 0x16;
++                return CC_PC_GENERIC_IC_HASH_INDEXED;
++
++            default:
++                REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 'extract from' src"));
++                break;
++        }
++    }
++
++    return CC_PC_ILLEGAL;
++}
++
++static uint8_t GetFullFieldParseCode(e_NetHeaderType hdr, e_FmPcdHdrIndex index,
++                                     t_FmPcdFields field)
++{
++    switch (hdr)
++    {
++        case (HEADER_TYPE_NONE):
++            ASSERT_COND(FALSE);
++            return CC_PC_ILLEGAL;
++
++        case (HEADER_TYPE_ETH):
++            switch (field.eth)
++            {
++                case (NET_HEADER_FIELD_ETH_DA):
++                    return CC_PC_FF_MACDST;
++                case (NET_HEADER_FIELD_ETH_SA):
++                    return CC_PC_FF_MACSRC;
++                case (NET_HEADER_FIELD_ETH_TYPE):
++                    return CC_PC_FF_ETYPE;
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_VLAN):
++            switch (field.vlan)
++            {
++                case (NET_HEADER_FIELD_VLAN_TCI):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_TCI1;
++                    if (index == e_FM_PCD_HDR_INDEX_LAST)
++                        return CC_PC_FF_TCI2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_MPLS):
++            switch (field.mpls)
++            {
++                case (NET_HEADER_FIELD_MPLS_LABEL_STACK):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_MPLS1;
++                    if (index == e_FM_PCD_HDR_INDEX_LAST)
++                        return CC_PC_FF_MPLS_LAST;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal MPLS index"));
++                    return CC_PC_ILLEGAL;
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_IPv4):
++            switch (field.ipv4)
++            {
++                case (NET_HEADER_FIELD_IPv4_DST_IP):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV4DST1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV4DST2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index"));
++                    return CC_PC_ILLEGAL;
++                case (NET_HEADER_FIELD_IPv4_TOS):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV4IPTOS_TC1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV4IPTOS_TC2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index"));
++                    return CC_PC_ILLEGAL;
++                case (NET_HEADER_FIELD_IPv4_PROTO):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV4PTYPE1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV4PTYPE2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index"));
++                    return CC_PC_ILLEGAL;
++                case (NET_HEADER_FIELD_IPv4_SRC_IP):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV4SRC1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV4SRC2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index"));
++                    return CC_PC_ILLEGAL;
++                case (NET_HEADER_FIELD_IPv4_SRC_IP
++                        | NET_HEADER_FIELD_IPv4_DST_IP):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV4SRC1_IPV4DST1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV4SRC2_IPV4DST2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index"));
++                    return CC_PC_ILLEGAL;
++                case (NET_HEADER_FIELD_IPv4_TTL):
++                    return CC_PC_FF_IPV4TTL;
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_IPv6):
++            switch (field.ipv6)
++            {
++                case (NET_HEADER_FIELD_IPv6_VER | NET_HEADER_FIELD_IPv6_FL
++                        | NET_HEADER_FIELD_IPv6_TC):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index"));
++                    return CC_PC_ILLEGAL;
++
++                case (NET_HEADER_FIELD_IPv6_NEXT_HDR):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV6PTYPE1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV6PTYPE2;
++                    if (index == e_FM_PCD_HDR_INDEX_LAST)
++                        return CC_PC_FF_IPPID;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index"));
++                    return CC_PC_ILLEGAL;
++
++                case (NET_HEADER_FIELD_IPv6_DST_IP):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV6DST1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV6DST2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index"));
++                    return CC_PC_ILLEGAL;
++
++                case (NET_HEADER_FIELD_IPv6_SRC_IP):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPV6SRC1;
++                    if (index == e_FM_PCD_HDR_INDEX_2)
++                        return CC_PC_FF_IPV6SRC2;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index"));
++                    return CC_PC_ILLEGAL;
++
++                case (NET_HEADER_FIELD_IPv6_HOP_LIMIT):
++                    return CC_PC_FF_IPV6HOP_LIMIT;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_IP):
++            switch (field.ip)
++            {
++                case (NET_HEADER_FIELD_IP_DSCP):
++                    if ((index == e_FM_PCD_HDR_INDEX_NONE)
++                            || (index == e_FM_PCD_HDR_INDEX_1))
++                        return CC_PC_FF_IPDSCP;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP index"));
++                    return CC_PC_ILLEGAL;
++
++                case (NET_HEADER_FIELD_IP_PROTO):
++                    if (index == e_FM_PCD_HDR_INDEX_LAST)
++                        return CC_PC_FF_IPPID;
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP index"));
++                    return CC_PC_ILLEGAL;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_GRE):
++            switch (field.gre)
++            {
++                case (NET_HEADER_FIELD_GRE_TYPE):
++                    return CC_PC_FF_GREPTYPE;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_MINENCAP):
++            switch (field.minencap)
++            {
++                case (NET_HEADER_FIELD_MINENCAP_TYPE):
++                    return CC_PC_FF_MINENCAP_PTYPE;
++
++                case (NET_HEADER_FIELD_MINENCAP_DST_IP):
++                    return CC_PC_FF_MINENCAP_IPDST;
++
++                case (NET_HEADER_FIELD_MINENCAP_SRC_IP):
++                    return CC_PC_FF_MINENCAP_IPSRC;
++
++                case (NET_HEADER_FIELD_MINENCAP_SRC_IP
++                        | NET_HEADER_FIELD_MINENCAP_DST_IP):
++                    return CC_PC_FF_MINENCAP_IPSRC_IPDST;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_TCP):
++            switch (field.tcp)
++            {
++                case (NET_HEADER_FIELD_TCP_PORT_SRC):
++                    return CC_PC_FF_L4PSRC;
++
++                case (NET_HEADER_FIELD_TCP_PORT_DST):
++                    return CC_PC_FF_L4PDST;
++
++                case (NET_HEADER_FIELD_TCP_PORT_DST
++                        | NET_HEADER_FIELD_TCP_PORT_SRC):
++                    return CC_PC_FF_L4PSRC_L4PDST;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_PPPoE):
++            switch (field.pppoe)
++            {
++                case (NET_HEADER_FIELD_PPPoE_PID):
++                    return CC_PC_FF_PPPPID;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        case (HEADER_TYPE_UDP):
++            switch (field.udp)
++            {
++                case (NET_HEADER_FIELD_UDP_PORT_SRC):
++                    return CC_PC_FF_L4PSRC;
++
++                case (NET_HEADER_FIELD_UDP_PORT_DST):
++                    return CC_PC_FF_L4PDST;
++
++                case (NET_HEADER_FIELD_UDP_PORT_DST
++                        | NET_HEADER_FIELD_UDP_PORT_SRC):
++                    return CC_PC_FF_L4PSRC_L4PDST;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++
++        default:
++            REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++            return CC_PC_ILLEGAL;
++    }
++}
++
++static uint8_t GetPrParseCode(e_NetHeaderType hdr, e_FmPcdHdrIndex hdrIndex,
++                              uint32_t offset, bool glblMask,
++                              uint8_t *parseArrayOffset)
++{
++    bool offsetRelevant = FALSE;
++
++    if (offset)
++        offsetRelevant = TRUE;
++
++    switch (hdr)
++    {
++        case (HEADER_TYPE_NONE):
++            ASSERT_COND(FALSE);
++            return CC_PC_ILLEGAL;
++
++        case (HEADER_TYPE_ETH):
++            *parseArrayOffset = (uint8_t)CC_PC_PR_ETH_OFFSET;
++            break;
++
++        case (HEADER_TYPE_USER_DEFINED_SHIM1):
++            if (offset || glblMask)
++                *parseArrayOffset = (uint8_t)CC_PC_PR_USER_DEFINED_SHIM1_OFFSET;
++            else
++                return CC_PC_PR_SHIM1;
++            break;
++
++        case (HEADER_TYPE_USER_DEFINED_SHIM2):
++            if (offset || glblMask)
++                *parseArrayOffset = (uint8_t)CC_PC_PR_USER_DEFINED_SHIM2_OFFSET;
++            else
++                return CC_PC_PR_SHIM2;
++            break;
++
++        case (HEADER_TYPE_LLC_SNAP):
++            *parseArrayOffset = CC_PC_PR_USER_LLC_SNAP_OFFSET;
++            break;
++
++        case (HEADER_TYPE_PPPoE):
++            *parseArrayOffset = CC_PC_PR_PPPOE_OFFSET;
++            break;
++
++        case (HEADER_TYPE_MPLS):
++            if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE)
++                    || (hdrIndex == e_FM_PCD_HDR_INDEX_1))
++                *parseArrayOffset = CC_PC_PR_MPLS1_OFFSET;
++            else
++                if (hdrIndex == e_FM_PCD_HDR_INDEX_LAST)
++                    *parseArrayOffset = CC_PC_PR_MPLS_LAST_OFFSET;
++                else
++                {
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal MPLS header index"));
++                    return CC_PC_ILLEGAL;
++                }
++            break;
++
++        case (HEADER_TYPE_IPv4):
++        case (HEADER_TYPE_IPv6):
++            if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE)
++                    || (hdrIndex == e_FM_PCD_HDR_INDEX_1))
++                *parseArrayOffset = CC_PC_PR_IP1_OFFSET;
++            else
++                if (hdrIndex == e_FM_PCD_HDR_INDEX_2)
++                    *parseArrayOffset = CC_PC_PR_IP_LAST_OFFSET;
++                else
++                {
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP header index"));
++                    return CC_PC_ILLEGAL;
++                }
++            break;
++
++        case (HEADER_TYPE_MINENCAP):
++            *parseArrayOffset = CC_PC_PR_MINENC_OFFSET;
++            break;
++
++        case (HEADER_TYPE_GRE):
++            *parseArrayOffset = CC_PC_PR_GRE_OFFSET;
++            break;
++
++        case (HEADER_TYPE_TCP):
++        case (HEADER_TYPE_UDP):
++        case (HEADER_TYPE_IPSEC_AH):
++        case (HEADER_TYPE_IPSEC_ESP):
++        case (HEADER_TYPE_DCCP):
++        case (HEADER_TYPE_SCTP):
++            *parseArrayOffset = CC_PC_PR_L4_OFFSET;
++            break;
++
++        default:
++            REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP header for this type of operation"));
++            return CC_PC_ILLEGAL;
++    }
++
++    if (offsetRelevant)
++        return CC_PR_OFFSET;
++    else
++        return CC_PR_WITHOUT_OFFSET;
++}
++
++static uint8_t GetFieldParseCode(e_NetHeaderType hdr, t_FmPcdFields field,
++                                 uint32_t offset, uint8_t *parseArrayOffset,
++                                 e_FmPcdHdrIndex hdrIndex)
++{
++    bool offsetRelevant = FALSE;
++
++    if (offset)
++        offsetRelevant = TRUE;
++
++    switch (hdr)
++    {
++        case (HEADER_TYPE_NONE):
++            ASSERT_COND(FALSE);
++                break;
++        case (HEADER_TYPE_ETH):
++            switch (field.eth)
++            {
++                case (NET_HEADER_FIELD_ETH_TYPE):
++                    *parseArrayOffset = CC_PC_PR_ETYPE_LAST_OFFSET;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++            break;
++
++        case (HEADER_TYPE_VLAN):
++            switch (field.vlan)
++            {
++                case (NET_HEADER_FIELD_VLAN_TCI):
++                    if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE)
++                            || (hdrIndex == e_FM_PCD_HDR_INDEX_1))
++                        *parseArrayOffset = CC_PC_PR_VLAN1_OFFSET;
++                    else
++                        if (hdrIndex == e_FM_PCD_HDR_INDEX_LAST)
++                            *parseArrayOffset = CC_PC_PR_VLAN2_OFFSET;
++                    break;
++
++                default:
++                    REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported"));
++                    return CC_PC_ILLEGAL;
++            }
++            break;
++
++        default:
++            REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal header "));
++            return CC_PC_ILLEGAL;
++    }
++
++    if (offsetRelevant)
++        return CC_PR_OFFSET;
++    else
++        return CC_PR_WITHOUT_OFFSET;
++}
++
++static void FillAdOfTypeResult(t_Handle h_Ad,
++                               t_FmPcdCcStatsParams *p_FmPcdCcStatsParams,
++                               t_FmPcd *p_FmPcd,
++                               t_FmPcdCcNextEngineParams *p_CcNextEngineParams)
++{
++    t_AdOfTypeResult *p_AdResult = (t_AdOfTypeResult *)h_Ad;
++    t_Handle h_TmpAd;
++    uint32_t tmp = 0, tmpNia = 0;
++    uint16_t profileId;
++    t_Handle p_AdNewPtr = NULL;
++
++    /* There are 3 cases handled in this routine of building a "result" type AD.
++     * Case 1: No Manip. The action descriptor is built within the match table.
++     * Case 2: Manip exists. A new AD is created - p_AdNewPtr. It is initialized
++     *         either in the FmPcdManipUpdateAdResultForCc routine or it was already
++     *         initialized and returned here.
++     *         p_AdResult (within the match table) will be initialized after
++     *         this routine returns and point to the existing AD.
++     * Case 3: Manip exists. The action descriptor is built within the match table.
++     *         FmPcdManipUpdateAdResultForCc returns a NULL p_AdNewPtr.
++     *
++     * If statistics were enabled and the statistics mode of this node requires
++     * a statistics Ad, it will be placed after the result Ad and before the
++     * manip Ad, if manip Ad exists here.
++     */
++
++    /* As default, the "new" ptr is the current one. i.e. the content of the result
++     * AD will be written into the match table itself (case (1))*/
++    p_AdNewPtr = p_AdResult;
++
++    /* Initialize an action descriptor, if current statistics mode requires an Ad */
++    if (p_FmPcdCcStatsParams)
++    {
++        ASSERT_COND(p_FmPcdCcStatsParams->h_StatsAd);
++        ASSERT_COND(p_FmPcdCcStatsParams->h_StatsCounters);
++
++        /* Swapping addresses between statistics Ad and the current lookup AD addresses */
++        h_TmpAd = p_FmPcdCcStatsParams->h_StatsAd;
++        p_FmPcdCcStatsParams->h_StatsAd = h_Ad;
++        h_Ad = h_TmpAd;
++
++        p_AdNewPtr = h_Ad;
++        p_AdResult = h_Ad;
++
++        /* Init statistics Ad and connect current lookup AD as 'next action' from statistics Ad */
++        UpdateStatsAd(p_FmPcdCcStatsParams, h_Ad, p_FmPcd->physicalMuramBase);
++    }
++
++    /* Create manip and return p_AdNewPtr to either a new descriptor or NULL */
++    if (p_CcNextEngineParams->h_Manip)
++        FmPcdManipUpdateAdResultForCc(p_CcNextEngineParams->h_Manip,
++                                      p_CcNextEngineParams, h_Ad, &p_AdNewPtr);
++
++    /* if (p_AdNewPtr = NULL) --> Done. (case (3)) */
++    if (p_AdNewPtr)
++    {
++        /* case (1) and (2) */
++        switch (p_CcNextEngineParams->nextEngine)
++        {
++            case (e_FM_PCD_DONE):
++                if (p_CcNextEngineParams->params.enqueueParams.action
++                        == e_FM_PCD_ENQ_FRAME)
++                {
++                    if (p_CcNextEngineParams->params.enqueueParams.overrideFqid)
++                    {
++                        tmp = FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE;
++                        tmp |=
++                                p_CcNextEngineParams->params.enqueueParams.newFqid;
++#if (DPAA_VERSION >= 11)
++                        tmp |=
++                                (p_CcNextEngineParams->params.enqueueParams.newRelativeStorageProfileId
++                                        & FM_PCD_AD_RESULT_VSP_MASK)
++                                        << FM_PCD_AD_RESULT_VSP_SHIFT;
++#endif /* (DPAA_VERSION >= 11) */
++                    }
++                    else
++                    {
++                        tmp = FM_PCD_AD_RESULT_DATA_FLOW_TYPE;
++                        tmp |= FM_PCD_AD_RESULT_PLCR_DIS;
++                    }
++                }
++
++                if (p_CcNextEngineParams->params.enqueueParams.action
++                        == e_FM_PCD_DROP_FRAME)
++                    tmpNia |= GET_NIA_BMI_AC_DISCARD_FRAME(p_FmPcd);
++                else
++                    tmpNia |= GET_NIA_BMI_AC_ENQ_FRAME(p_FmPcd);
++                break;
++
++            case (e_FM_PCD_KG):
++                if (p_CcNextEngineParams->params.kgParams.overrideFqid)
++                {
++                    tmp = FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE;
++                    tmp |= p_CcNextEngineParams->params.kgParams.newFqid;
++#if (DPAA_VERSION >= 11)
++                    tmp |=
++                            (p_CcNextEngineParams->params.kgParams.newRelativeStorageProfileId
++                                    & FM_PCD_AD_RESULT_VSP_MASK)
++                                    << FM_PCD_AD_RESULT_VSP_SHIFT;
++#endif /* (DPAA_VERSION >= 11) */
++                }
++                else
++                {
++                    tmp = FM_PCD_AD_RESULT_DATA_FLOW_TYPE;
++                    tmp |= FM_PCD_AD_RESULT_PLCR_DIS;
++                }
++                tmpNia = NIA_KG_DIRECT;
++                tmpNia |= NIA_ENG_KG;
++                tmpNia |= NIA_KG_CC_EN;
++                tmpNia |= FmPcdKgGetSchemeId(
++                        p_CcNextEngineParams->params.kgParams.h_DirectScheme);
++                break;
++
++            case (e_FM_PCD_PLCR):
++                if (p_CcNextEngineParams->params.plcrParams.overrideParams)
++                {
++                    tmp = FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE;
++
++                    /* if private policer profile, it may be uninitialized yet, therefore no checks are done at this stage */
++                    if (p_CcNextEngineParams->params.plcrParams.sharedProfile)
++                    {
++                        tmpNia |= NIA_PLCR_ABSOLUTE;
++                        FmPcdPlcrGetAbsoluteIdByProfileParams(
++                                (t_Handle)p_FmPcd,
++                                e_FM_PCD_PLCR_SHARED,
++                                NULL,
++                                p_CcNextEngineParams->params.plcrParams.newRelativeProfileId,
++                                &profileId);
++                    }
++                    else
++                        profileId =
++                                p_CcNextEngineParams->params.plcrParams.newRelativeProfileId;
++
++                    tmp |= p_CcNextEngineParams->params.plcrParams.newFqid;
++#if (DPAA_VERSION >= 11)
++                    tmp |=
++                            (p_CcNextEngineParams->params.plcrParams.newRelativeStorageProfileId
++                                    & FM_PCD_AD_RESULT_VSP_MASK)
++                                    << FM_PCD_AD_RESULT_VSP_SHIFT;
++#endif /* (DPAA_VERSION >= 11) */
++                    WRITE_UINT32(
++                            p_AdResult->plcrProfile,
++                            (uint32_t)((uint32_t)profileId << FM_PCD_AD_PROFILEID_FOR_CNTRL_SHIFT));
++                }
++                else
++                    tmp = FM_PCD_AD_RESULT_DATA_FLOW_TYPE;
++
++                tmpNia |=
++                        NIA_ENG_PLCR
++                                | p_CcNextEngineParams->params.plcrParams.newRelativeProfileId;
++                break;
++
++            default:
++                return;
++        }WRITE_UINT32(p_AdResult->fqid, tmp);
++
++        if (p_CcNextEngineParams->h_Manip)
++        {
++            tmp = GET_UINT32(p_AdResult->plcrProfile);
++            tmp |= (uint32_t)(XX_VirtToPhys(p_AdNewPtr)
++                    - (p_FmPcd->physicalMuramBase)) >> 4;
++            WRITE_UINT32(p_AdResult->plcrProfile, tmp);
++
++            tmpNia |= FM_PCD_AD_RESULT_EXTENDED_MODE;
++            tmpNia |= FM_PCD_AD_RESULT_NADEN;
++        }
++
++#if (DPAA_VERSION >= 11)
++        tmpNia |= FM_PCD_AD_RESULT_NO_OM_VSPE;
++#endif /* (DPAA_VERSION >= 11) */
++        WRITE_UINT32(p_AdResult->nia, tmpNia);
++    }
++}
++
++static t_Error CcUpdateParams(t_Handle h_FmPcd, t_Handle h_PcdParams,
++                              t_Handle h_FmPort, t_Handle h_FmTree,
++                              bool validate)
++{
++    t_FmPcdCcTree *p_CcTree = (t_FmPcdCcTree *)h_FmTree;
++
++    return CcUpdateParam(h_FmPcd, h_PcdParams, h_FmPort,
++                         p_CcTree->keyAndNextEngineParams,
++                         p_CcTree->numOfEntries,
++                         UINT_TO_PTR(p_CcTree->ccTreeBaseAddr), validate, 0,
++                         h_FmTree, FALSE);
++}
++
++
++static void ReleaseNewNodeCommonPart(
++        t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo)
++{
++    if (p_AdditionalInfo->p_AdTableNew)
++        FM_MURAM_FreeMem(
++                FmPcdGetMuramHandle(
++                        ((t_FmPcdCcNode *)(p_AdditionalInfo->h_CurrentNode))->h_FmPcd),
++                p_AdditionalInfo->p_AdTableNew);
++
++    if (p_AdditionalInfo->p_KeysMatchTableNew)
++        FM_MURAM_FreeMem(
++                FmPcdGetMuramHandle(
++                        ((t_FmPcdCcNode *)(p_AdditionalInfo->h_CurrentNode))->h_FmPcd),
++                p_AdditionalInfo->p_KeysMatchTableNew);
++}
++
++static t_Error UpdateGblMask(t_FmPcdCcNode *p_CcNode, uint8_t keySize,
++                             uint8_t *p_Mask)
++{
++    uint8_t prvGlblMaskSize = p_CcNode->glblMaskSize;
++
++    if (p_Mask && !p_CcNode->glblMaskUpdated && (keySize <= 4)
++            && !p_CcNode->lclMask)
++    {
++        if (p_CcNode->parseCode && (p_CcNode->parseCode != CC_PC_FF_TCI1)
++                && (p_CcNode->parseCode != CC_PC_FF_TCI2)
++                && (p_CcNode->parseCode != CC_PC_FF_MPLS1)
++                && (p_CcNode->parseCode != CC_PC_FF_MPLS_LAST)
++                && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC1)
++                && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC2)
++                && (p_CcNode->parseCode != CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1)
++                && (p_CcNode->parseCode != CC_PC_FF_IPDSCP)
++                && (p_CcNode->parseCode != CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2))
++        {
++            p_CcNode->glblMaskSize = 0;
++            p_CcNode->lclMask = TRUE;
++        }
++        else
++        {
++            memcpy(p_CcNode->p_GlblMask, p_Mask, (sizeof(uint8_t)) * keySize);
++            p_CcNode->glblMaskUpdated = TRUE;
++            p_CcNode->glblMaskSize = 4;
++        }
++    }
++    else
++        if (p_Mask && (keySize <= 4) && !p_CcNode->lclMask)
++        {
++            if (memcmp(p_CcNode->p_GlblMask, p_Mask, keySize) != 0)
++            {
++                p_CcNode->lclMask = TRUE;
++                p_CcNode->glblMaskSize = 0;
++            }
++        }
++        else
++            if (!p_Mask && p_CcNode->glblMaskUpdated && (keySize <= 4))
++            {
++                uint32_t tmpMask = 0xffffffff;
++                if (memcmp(p_CcNode->p_GlblMask, &tmpMask, 4) != 0)
++                {
++                    p_CcNode->lclMask = TRUE;
++                    p_CcNode->glblMaskSize = 0;
++                }
++            }
++            else
++                if (p_Mask)
++                {
++                    p_CcNode->lclMask = TRUE;
++                    p_CcNode->glblMaskSize = 0;
++                }
++
++    /* In static mode (maxNumOfKeys > 0), local mask is supported
++     only is mask support was enabled at initialization */
++    if (p_CcNode->maxNumOfKeys && (!p_CcNode->maskSupport) && p_CcNode->lclMask)
++    {
++        p_CcNode->lclMask = FALSE;
++        p_CcNode->glblMaskSize = prvGlblMaskSize;
++        return ERROR_CODE(E_NOT_SUPPORTED);
++    }
++
++    return E_OK;
++}
++
++static __inline__ t_Handle GetNewAd(t_Handle h_FmPcdCcNodeOrTree, bool isTree)
++{
++    t_FmPcd *p_FmPcd;
++    t_Handle h_Ad;
++
++    if (isTree)
++        p_FmPcd = (t_FmPcd *)(((t_FmPcdCcTree *)h_FmPcdCcNodeOrTree)->h_FmPcd);
++    else
++        p_FmPcd = (t_FmPcd *)(((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->h_FmPcd);
++
++    if ((isTree && p_FmPcd->p_CcShadow)
++            || (!isTree && ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->maxNumOfKeys))
++    {
++        /* The allocated shadow is divided as follows:
++         0 . . .       16 . . .
++         ---------------------------------------------------
++         |   Shadow   |   Shadow Keys   |   Shadow Next    |
++         |     Ad     |   Match Table   |   Engine Table   |
++         | (16 bytes) | (maximal size)  |  (maximal size)  |
++         ---------------------------------------------------
++         */
++        if (!p_FmPcd->p_CcShadow)
++        {
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("CC Shadow not allocated"));
++            return NULL;
++        }
++
++        h_Ad = p_FmPcd->p_CcShadow;
++    }
++    else
++    {
++        h_Ad = (t_Handle)FM_MURAM_AllocMem(FmPcdGetMuramHandle(p_FmPcd),
++                                           FM_PCD_CC_AD_ENTRY_SIZE,
++                                           FM_PCD_CC_AD_TABLE_ALIGN);
++        if (!h_Ad)
++        {
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for CC node action descriptor"));
++            return NULL;
++        }
++    }
++
++    return h_Ad;
++}
++
++static t_Error BuildNewNodeCommonPart(
++        t_FmPcdCcNode *p_CcNode, int *size,
++        t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo)
++{
++    t_FmPcd *p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++
++    if (p_CcNode->lclMask)
++        *size = 2 * p_CcNode->ccKeySizeAccExtraction;
++    else
++        *size = p_CcNode->ccKeySizeAccExtraction;
++
++    if (p_CcNode->maxNumOfKeys == 0)
++    {
++        p_AdditionalInfo->p_AdTableNew = (t_Handle)FM_MURAM_AllocMem(
++                FmPcdGetMuramHandle(p_FmPcd),
++                (uint32_t)((p_AdditionalInfo->numOfKeys + 1)
++                        * FM_PCD_CC_AD_ENTRY_SIZE),
++                FM_PCD_CC_AD_TABLE_ALIGN);
++        if (!p_AdditionalInfo->p_AdTableNew)
++            RETURN_ERROR(
++                    MAJOR, E_NO_MEMORY,
++                    ("MURAM allocation for CC node action descriptors table"));
++
++        p_AdditionalInfo->p_KeysMatchTableNew = (t_Handle)FM_MURAM_AllocMem(
++                FmPcdGetMuramHandle(p_FmPcd),
++                (uint32_t)(*size * sizeof(uint8_t)
++                        * (p_AdditionalInfo->numOfKeys + 1)),
++                FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN);
++        if (!p_AdditionalInfo->p_KeysMatchTableNew)
++        {
++            FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd),
++                             p_AdditionalInfo->p_AdTableNew);
++            p_AdditionalInfo->p_AdTableNew = NULL;
++            RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                         ("MURAM allocation for CC node key match table"));
++        }
++
++        IOMemSet32(
++                (uint8_t*)p_AdditionalInfo->p_AdTableNew,
++                0,
++                (uint32_t)((p_AdditionalInfo->numOfKeys + 1)
++                        * FM_PCD_CC_AD_ENTRY_SIZE));
++        IOMemSet32((uint8_t*)p_AdditionalInfo->p_KeysMatchTableNew, 0,
++                   *size * sizeof(uint8_t) * (p_AdditionalInfo->numOfKeys + 1));
++    }
++    else
++    {
++        /* The allocated shadow is divided as follows:
++         0 . . .       16 . . .
++         ---------------------------------------------------
++         |   Shadow   |   Shadow Keys   |   Shadow Next    |
++         |     Ad     |   Match Table   |   Engine Table   |
++         | (16 bytes) | (maximal size)  |  (maximal size)  |
++         ---------------------------------------------------
++         */
++
++        if (!p_FmPcd->p_CcShadow)
++            RETURN_ERROR(MAJOR, E_NO_MEMORY, ("CC Shadow not allocated"));
++
++        p_AdditionalInfo->p_KeysMatchTableNew =
++                PTR_MOVE(p_FmPcd->p_CcShadow, FM_PCD_CC_AD_ENTRY_SIZE);
++        p_AdditionalInfo->p_AdTableNew =
++                PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, p_CcNode->keysMatchTableMaxSize);
++
++        IOMemSet32(
++                (uint8_t*)p_AdditionalInfo->p_AdTableNew,
++                0,
++                (uint32_t)((p_CcNode->maxNumOfKeys + 1)
++                        * FM_PCD_CC_AD_ENTRY_SIZE));
++        IOMemSet32((uint8_t*)p_AdditionalInfo->p_KeysMatchTableNew, 0,
++                   (*size) * sizeof(uint8_t) * (p_CcNode->maxNumOfKeys));
++    }
++
++    p_AdditionalInfo->p_AdTableOld = p_CcNode->h_AdTable;
++    p_AdditionalInfo->p_KeysMatchTableOld = p_CcNode->h_KeysMatchTable;
++
++    return E_OK;
++}
++
++static t_Error BuildNewNodeAddOrMdfyKeyAndNextEngine(
++        t_Handle h_FmPcd, t_FmPcdCcNode *p_CcNode, uint16_t keyIndex,
++        t_FmPcdCcKeyParams *p_KeyParams,
++        t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo, bool add)
++{
++    t_Error err = E_OK;
++    t_Handle p_AdTableNewTmp, p_KeysMatchTableNewTmp;
++    t_Handle p_KeysMatchTableOldTmp, p_AdTableOldTmp;
++    int size;
++    int i = 0, j = 0;
++    t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
++    uint32_t requiredAction = 0;
++    bool prvLclMask;
++    t_CcNodeInformation *p_CcNodeInformation;
++    t_FmPcdCcStatsParams statsParams = { 0 };
++    t_List *p_Pos;
++    t_FmPcdStatsObj *p_StatsObj;
++
++    /* Check that new NIA is legal */
++    err = ValidateNextEngineParams(h_FmPcd, &p_KeyParams->ccNextEngineParams,
++                                   p_CcNode->statisticsMode);
++    if (err)
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++
++    prvLclMask = p_CcNode->lclMask;
++
++    /* Check that new key is not require update of localMask */
++    err = UpdateGblMask(p_CcNode, p_CcNode->ccKeySizeAccExtraction,
++                        p_KeyParams->p_Mask);
++    if (err)
++        RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++    /* Update internal data structure with new next engine for the given index */
++    memcpy(&p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams,
++           &p_KeyParams->ccNextEngineParams, sizeof(t_FmPcdCcNextEngineParams));
++
++    memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].key,
++           p_KeyParams->p_Key, p_CcNode->userSizeOfExtraction);
++
++    if ((p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++            == e_FM_PCD_CC)
++            && p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip)
++    {
++        err =
++                AllocAndFillAdForContLookupManip(
++                        p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    if (p_KeyParams->p_Mask)
++        memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask,
++               p_KeyParams->p_Mask, p_CcNode->userSizeOfExtraction);
++    else
++        memset(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask, 0xFF,
++               p_CcNode->userSizeOfExtraction);
++
++    /* Update numOfKeys */
++    if (add)
++        p_AdditionalInfo->numOfKeys = (uint8_t)(p_CcNode->numOfKeys + 1);
++    else
++        p_AdditionalInfo->numOfKeys = (uint8_t)p_CcNode->numOfKeys;
++
++    /* Allocate new tables in MURAM: keys match table and action descriptors table */
++    err = BuildNewNodeCommonPart(p_CcNode, &size, p_AdditionalInfo);
++    if (err)
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++
++    /* Check that manip is legal and what requiredAction is necessary for this manip */
++    if (p_KeyParams->ccNextEngineParams.h_Manip)
++    {
++        err = FmPcdManipCheckParamsForCcNextEngine(
++                &p_KeyParams->ccNextEngineParams, &requiredAction);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction =
++            requiredAction;
++    p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction |=
++            UPDATE_CC_WITH_TREE;
++
++    /* Update new Ad and new Key Table according to new requirement */
++    i = 0;
++    for (j = 0; j < p_AdditionalInfo->numOfKeys; j++)
++    {
++        p_AdTableNewTmp =
++                PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j*FM_PCD_CC_AD_ENTRY_SIZE);
++
++        if (j == keyIndex)
++        {
++            if (p_KeyParams->ccNextEngineParams.statisticsEn)
++            {
++                /* Allocate a statistics object that holds statistics AD and counters.
++                 - For added key - New statistics AD and counters pointer need to be allocated
++                 new statistics object. If statistics were enabled, we need to replace the
++                 existing descriptor with a new descriptor with nullified counters.
++                 */
++                p_StatsObj = GetStatsObj(p_CcNode);
++                ASSERT_COND(p_StatsObj);
++
++                /* Store allocated statistics object */
++                ASSERT_COND(keyIndex < CC_MAX_NUM_OF_KEYS);
++                p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj =
++                        p_StatsObj;
++
++                statsParams.h_StatsAd = p_StatsObj->h_StatsAd;
++                statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters;
++#if (DPAA_VERSION >= 11)
++                statsParams.h_StatsFLRs = p_CcNode->h_StatsFLRs;
++
++#endif /* (DPAA_VERSION >= 11) */
++
++                /* Building action descriptor for the received new key */
++                NextStepAd(p_AdTableNewTmp, &statsParams,
++                           &p_KeyParams->ccNextEngineParams, p_FmPcd);
++            }
++            else
++            {
++                /* Building action descriptor for the received new key */
++                NextStepAd(p_AdTableNewTmp, NULL,
++                           &p_KeyParams->ccNextEngineParams, p_FmPcd);
++            }
++
++            /* Copy the received new key into keys match table */
++            p_KeysMatchTableNewTmp =
++                    PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j*size*sizeof(uint8_t));
++
++            Mem2IOCpy32((void*)p_KeysMatchTableNewTmp, p_KeyParams->p_Key,
++                        p_CcNode->userSizeOfExtraction);
++
++            /* Update mask for the received new key */
++            if (p_CcNode->lclMask)
++            {
++                if (p_KeyParams->p_Mask)
++                {
++                    Mem2IOCpy32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                            p_CcNode->ccKeySizeAccExtraction),
++                                p_KeyParams->p_Mask,
++                                p_CcNode->userSizeOfExtraction);
++                }
++                else
++                    if (p_CcNode->ccKeySizeAccExtraction > 4)
++                    {
++                        IOMemSet32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                                p_CcNode->ccKeySizeAccExtraction),
++                                   0xff, p_CcNode->userSizeOfExtraction);
++                    }
++                    else
++                    {
++                        Mem2IOCpy32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                                p_CcNode->ccKeySizeAccExtraction),
++                                    p_CcNode->p_GlblMask,
++                                    p_CcNode->userSizeOfExtraction);
++                    }
++            }
++
++            /* If key modification requested, the old entry is omitted and replaced by the new parameters */
++            if (!add)
++                i++;
++        }
++        else
++        {
++            /* Copy existing action descriptors to the newly allocated Ad table */
++            p_AdTableOldTmp =
++                    PTR_MOVE(p_AdditionalInfo->p_AdTableOld, i*FM_PCD_CC_AD_ENTRY_SIZE);
++            IO2IOCpy32(p_AdTableNewTmp, p_AdTableOldTmp,
++                       FM_PCD_CC_AD_ENTRY_SIZE);
++
++            /* Copy existing keys and their masks to the newly allocated keys match table */
++            p_KeysMatchTableNewTmp =
++                    PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j * size * sizeof(uint8_t));
++            p_KeysMatchTableOldTmp =
++                    PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableOld, i * size * sizeof(uint8_t));
++
++            if (p_CcNode->lclMask)
++            {
++                if (prvLclMask)
++                {
++                    IO2IOCpy32(
++                            PTR_MOVE(p_KeysMatchTableNewTmp, p_CcNode->ccKeySizeAccExtraction),
++                            PTR_MOVE(p_KeysMatchTableOldTmp, p_CcNode->ccKeySizeAccExtraction),
++                            p_CcNode->ccKeySizeAccExtraction);
++                }
++                else
++                {
++                    p_KeysMatchTableOldTmp =
++                            PTR_MOVE(p_CcNode->h_KeysMatchTable,
++                                    i * (int)p_CcNode->ccKeySizeAccExtraction * sizeof(uint8_t));
++
++                    if (p_CcNode->ccKeySizeAccExtraction > 4)
++                    {
++                        IOMemSet32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                                p_CcNode->ccKeySizeAccExtraction),
++                                   0xff, p_CcNode->userSizeOfExtraction);
++                    }
++                    else
++                    {
++                        IO2IOCpy32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                                p_CcNode->ccKeySizeAccExtraction),
++                                   p_CcNode->p_GlblMask,
++                                   p_CcNode->userSizeOfExtraction);
++                    }
++                }
++            }
++
++            IO2IOCpy32(p_KeysMatchTableNewTmp, p_KeysMatchTableOldTmp,
++                       p_CcNode->ccKeySizeAccExtraction);
++
++            i++;
++        }
++    }
++
++    /* Miss action descriptor */
++    p_AdTableNewTmp =
++            PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j * FM_PCD_CC_AD_ENTRY_SIZE);
++    p_AdTableOldTmp =
++            PTR_MOVE(p_AdditionalInfo->p_AdTableOld, i * FM_PCD_CC_AD_ENTRY_SIZE);
++    IO2IOCpy32(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++
++    if (!LIST_IsEmpty(&p_CcNode->ccTreesLst))
++    {
++        LIST_FOR_EACH(p_Pos, &p_CcNode->ccTreesLst)
++        {
++            p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos);
++            ASSERT_COND(p_CcNodeInformation->h_CcNode);
++            /* Update the manipulation which has to be updated from parameters of the port */
++            /* It's has to be updated with restrictions defined in the function */
++            err =
++                    SetRequiredAction(
++                            p_CcNode->h_FmPcd,
++                            p_CcNode->shadowAction
++                                    | p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction,
++                            &p_AdditionalInfo->keyAndNextEngineParams[keyIndex],
++                            PTR_MOVE(p_AdditionalInfo->p_AdTableNew, keyIndex*FM_PCD_CC_AD_ENTRY_SIZE),
++                            1, p_CcNodeInformation->h_CcNode);
++            if (err)
++                RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++            err =
++                    CcUpdateParam(
++                            p_CcNode->h_FmPcd,
++                            NULL,
++                            NULL,
++                            &p_AdditionalInfo->keyAndNextEngineParams[keyIndex],
++                            1,
++                            PTR_MOVE(p_AdditionalInfo->p_AdTableNew, keyIndex*FM_PCD_CC_AD_ENTRY_SIZE),
++                            TRUE, p_CcNodeInformation->index,
++                            p_CcNodeInformation->h_CcNode, TRUE);
++            if (err)
++                RETURN_ERROR(MAJOR, err, (NO_MSG));
++        }
++    }
++
++    if (p_CcNode->lclMask)
++        memset(p_CcNode->p_GlblMask, 0xff, CC_GLBL_MASK_SIZE * sizeof(uint8_t));
++
++    if (p_KeyParams->ccNextEngineParams.nextEngine == e_FM_PCD_CC)
++        p_AdditionalInfo->h_NodeForAdd =
++                p_KeyParams->ccNextEngineParams.params.ccParams.h_CcNode;
++    if (p_KeyParams->ccNextEngineParams.h_Manip)
++        p_AdditionalInfo->h_ManipForAdd =
++                p_KeyParams->ccNextEngineParams.h_Manip;
++
++#if (DPAA_VERSION >= 11)
++    if ((p_KeyParams->ccNextEngineParams.nextEngine == e_FM_PCD_FR)
++            && (p_KeyParams->ccNextEngineParams.params.frParams.h_FrmReplic))
++        p_AdditionalInfo->h_FrmReplicForAdd =
++                p_KeyParams->ccNextEngineParams.params.frParams.h_FrmReplic;
++#endif /* (DPAA_VERSION >= 11) */
++
++    if (!add)
++    {
++        if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++                == e_FM_PCD_CC)
++            p_AdditionalInfo->h_NodeForRmv =
++                    p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode;
++
++        if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip)
++            p_AdditionalInfo->h_ManipForRmv =
++                    p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip;
++
++        /* If statistics were previously enabled, store the old statistics object to be released */
++        if (p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj)
++        {
++            p_AdditionalInfo->p_StatsObjForRmv =
++                    p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj;
++        }
++
++#if (DPAA_VERSION >= 11)
++        if ((p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++                == e_FM_PCD_FR)
++                && (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic))
++            p_AdditionalInfo->h_FrmReplicForRmv =
++                    p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic;
++#endif /* (DPAA_VERSION >= 11) */
++    }
++
++    return E_OK;
++}
++
++static t_Error BuildNewNodeRemoveKey(
++        t_FmPcdCcNode *p_CcNode, uint16_t keyIndex,
++        t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo)
++{
++    int i = 0, j = 0;
++    t_Handle p_AdTableNewTmp, p_KeysMatchTableNewTmp;
++    t_Handle p_KeysMatchTableOldTmp, p_AdTableOldTmp;
++    int size;
++    t_Error err = E_OK;
++
++    /*save new numOfKeys*/
++    p_AdditionalInfo->numOfKeys = (uint16_t)(p_CcNode->numOfKeys - 1);
++
++    /*function which allocates in the memory new KeyTbl, AdTbl*/
++    err = BuildNewNodeCommonPart(p_CcNode, &size, p_AdditionalInfo);
++    if (err)
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++
++    /*update new Ad and new Key Table according to new requirement*/
++    for (i = 0, j = 0; j < p_CcNode->numOfKeys; i++, j++)
++    {
++        if (j == keyIndex)
++            j++;
++
++        if (j == p_CcNode->numOfKeys)
++            break;
++        p_AdTableNewTmp =
++                PTR_MOVE(p_AdditionalInfo->p_AdTableNew, i * FM_PCD_CC_AD_ENTRY_SIZE);
++        p_AdTableOldTmp =
++                PTR_MOVE(p_AdditionalInfo->p_AdTableOld, j * FM_PCD_CC_AD_ENTRY_SIZE);
++        IO2IOCpy32(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++
++        p_KeysMatchTableOldTmp =
++                PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableOld, j * size * sizeof(uint8_t));
++        p_KeysMatchTableNewTmp =
++                PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, i * size * sizeof(uint8_t));
++        IO2IOCpy32(p_KeysMatchTableNewTmp, p_KeysMatchTableOldTmp,
++                   size * sizeof(uint8_t));
++    }
++
++    p_AdTableNewTmp =
++            PTR_MOVE(p_AdditionalInfo->p_AdTableNew, i * FM_PCD_CC_AD_ENTRY_SIZE);
++    p_AdTableOldTmp =
++            PTR_MOVE(p_AdditionalInfo->p_AdTableOld, j * FM_PCD_CC_AD_ENTRY_SIZE);
++    IO2IOCpy32(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++
++    if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++            == e_FM_PCD_CC)
++        p_AdditionalInfo->h_NodeForRmv =
++                p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode;
++
++    if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip)
++        p_AdditionalInfo->h_ManipForRmv =
++                p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip;
++
++    /* If statistics were previously enabled, store the old statistics object to be released */
++    if (p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj)
++    {
++        p_AdditionalInfo->p_StatsObjForRmv =
++                p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj;
++    }
++
++#if (DPAA_VERSION >= 11)
++    if ((p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++            == e_FM_PCD_FR)
++            && (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic))
++        p_AdditionalInfo->h_FrmReplicForRmv =
++                p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic;
++#endif /* (DPAA_VERSION >= 11) */
++
++    return E_OK;
++}
++
++static t_Error BuildNewNodeModifyKey(
++        t_FmPcdCcNode *p_CcNode, uint16_t keyIndex, uint8_t *p_Key,
++        uint8_t *p_Mask, t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo)
++{
++    t_FmPcd *p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++    t_Error err = E_OK;
++    t_Handle p_AdTableNewTmp, p_KeysMatchTableNewTmp;
++    t_Handle p_KeysMatchTableOldTmp, p_AdTableOldTmp;
++    int size;
++    int i = 0, j = 0;
++    bool prvLclMask;
++    t_FmPcdStatsObj *p_StatsObj, tmpStatsObj;
++    p_AdditionalInfo->numOfKeys = p_CcNode->numOfKeys;
++
++    prvLclMask = p_CcNode->lclMask;
++
++    /* Check that new key is not require update of localMask */
++    err = UpdateGblMask(p_CcNode, p_CcNode->ccKeySizeAccExtraction, p_Mask);
++    if (err)
++        RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++    /* Update internal data structure with new next engine for the given index */
++    memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].key, p_Key,
++           p_CcNode->userSizeOfExtraction);
++
++    if (p_Mask)
++        memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask, p_Mask,
++               p_CcNode->userSizeOfExtraction);
++    else
++        memset(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask, 0xFF,
++               p_CcNode->userSizeOfExtraction);
++
++    /*function which build in the memory new KeyTbl, AdTbl*/
++    err = BuildNewNodeCommonPart(p_CcNode, &size, p_AdditionalInfo);
++    if (err)
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++
++    /*fill the New AdTable and New KeyTable*/
++    for (j = 0, i = 0; j < p_AdditionalInfo->numOfKeys; j++, i++)
++    {
++        p_AdTableNewTmp =
++                PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j*FM_PCD_CC_AD_ENTRY_SIZE);
++        p_AdTableOldTmp =
++                PTR_MOVE(p_AdditionalInfo->p_AdTableOld, i*FM_PCD_CC_AD_ENTRY_SIZE);
++
++        IO2IOCpy32(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++
++        if (j == keyIndex)
++        {
++            ASSERT_COND(keyIndex < CC_MAX_NUM_OF_KEYS);
++            if (p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj)
++            {
++                /* As statistics were enabled, we need to update the existing
++                 statistics descriptor with a new nullified counters. */
++                p_StatsObj = GetStatsObj(p_CcNode);
++                ASSERT_COND(p_StatsObj);
++
++                SetStatsCounters(
++                        p_AdTableNewTmp,
++                        (uint32_t)((XX_VirtToPhys(p_StatsObj->h_StatsCounters)
++                                - p_FmPcd->physicalMuramBase)));
++
++                tmpStatsObj.h_StatsAd = p_StatsObj->h_StatsAd;
++                tmpStatsObj.h_StatsCounters = p_StatsObj->h_StatsCounters;
++
++                /* As we need to replace only the counters, we build a new statistics
++                 object that holds the old AD and the new counters - this will be the
++                 currently used statistics object.
++                 The newly allocated AD is not required and may be released back to
++                 the available objects with the previous counters pointer. */
++                p_StatsObj->h_StatsAd =
++                        p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsAd;
++
++                p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsAd =
++                        tmpStatsObj.h_StatsAd;
++
++                /* Store allocated statistics object */
++                p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj =
++                        p_StatsObj;
++
++                /* As statistics were previously enabled, store the old statistics object to be released */
++                p_AdditionalInfo->p_StatsObjForRmv =
++                        p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj;
++            }
++
++            p_KeysMatchTableNewTmp =
++                    PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j * size * sizeof(uint8_t));
++
++            Mem2IOCpy32(p_KeysMatchTableNewTmp, p_Key,
++                        p_CcNode->userSizeOfExtraction);
++
++            if (p_CcNode->lclMask)
++            {
++                if (p_Mask)
++                    Mem2IOCpy32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                            p_CcNode->ccKeySizeAccExtraction),
++                                p_Mask, p_CcNode->userSizeOfExtraction);
++                else
++                    if (p_CcNode->ccKeySizeAccExtraction > 4)
++                        IOMemSet32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                                p_CcNode->ccKeySizeAccExtraction),
++                                   0xff, p_CcNode->userSizeOfExtraction);
++                    else
++                        Mem2IOCpy32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                                p_CcNode->ccKeySizeAccExtraction),
++                                    p_CcNode->p_GlblMask,
++                                    p_CcNode->userSizeOfExtraction);
++            }
++        }
++        else
++        {
++            p_KeysMatchTableNewTmp =
++                    PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j * size * sizeof(uint8_t));
++            p_KeysMatchTableOldTmp =
++                    PTR_MOVE(p_CcNode->h_KeysMatchTable, i * size * sizeof(uint8_t));
++
++            if (p_CcNode->lclMask)
++            {
++                if (prvLclMask)
++                    IO2IOCpy32(
++                            PTR_MOVE(p_KeysMatchTableNewTmp, p_CcNode->ccKeySizeAccExtraction),
++                            PTR_MOVE(p_KeysMatchTableOldTmp, p_CcNode->ccKeySizeAccExtraction),
++                            p_CcNode->userSizeOfExtraction);
++                else
++                {
++                    p_KeysMatchTableOldTmp =
++                            PTR_MOVE(p_CcNode->h_KeysMatchTable,
++                                     i * (int)p_CcNode->ccKeySizeAccExtraction * sizeof(uint8_t));
++
++                    if (p_CcNode->ccKeySizeAccExtraction > 4)
++                        IOMemSet32(PTR_MOVE(p_KeysMatchTableNewTmp,
++                                p_CcNode->ccKeySizeAccExtraction),
++                                   0xff, p_CcNode->userSizeOfExtraction);
++                    else
++                        IO2IOCpy32(
++                                PTR_MOVE(p_KeysMatchTableNewTmp, p_CcNode->ccKeySizeAccExtraction),
++                                p_CcNode->p_GlblMask,
++                                p_CcNode->userSizeOfExtraction);
++                }
++            }
++            IO2IOCpy32((void*)p_KeysMatchTableNewTmp, p_KeysMatchTableOldTmp,
++                       p_CcNode->ccKeySizeAccExtraction);
++        }
++    }
++
++    p_AdTableNewTmp =
++            PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j * FM_PCD_CC_AD_ENTRY_SIZE);
++    p_AdTableOldTmp = PTR_MOVE(p_CcNode->h_AdTable, i * FM_PCD_CC_AD_ENTRY_SIZE);
++
++    IO2IOCpy32(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++
++    return E_OK;
++}
++
++static t_Error BuildNewNodeModifyNextEngine(
++        t_Handle h_FmPcd, t_Handle h_FmPcdCcNodeOrTree, uint16_t keyIndex,
++        t_FmPcdCcNextEngineParams *p_CcNextEngineParams, t_List *h_OldLst,
++        t_List *h_NewLst, t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo)
++{
++    t_Error err = E_OK;
++    uint32_t requiredAction = 0;
++    t_List *p_Pos;
++    t_CcNodeInformation *p_CcNodeInformation, ccNodeInfo;
++    t_Handle p_Ad;
++    t_FmPcdCcNode *p_FmPcdCcNode1 = NULL;
++    t_FmPcdCcTree *p_FmPcdCcTree = NULL;
++    t_FmPcdStatsObj *p_StatsObj;
++    t_FmPcdCcStatsParams statsParams = { 0 };
++
++    ASSERT_COND(p_CcNextEngineParams);
++
++    /* check that new NIA is legal */
++    if (!p_AdditionalInfo->tree)
++        err = ValidateNextEngineParams(
++                h_FmPcd, p_CcNextEngineParams,
++                ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->statisticsMode);
++    else
++        /* Statistics are not supported for CC root */
++        err = ValidateNextEngineParams(h_FmPcd, p_CcNextEngineParams,
++                                       e_FM_PCD_CC_STATS_MODE_NONE);
++    if (err)
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++
++    /* Update internal data structure for next engine per index (index - key) */
++    memcpy(&p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams,
++           p_CcNextEngineParams, sizeof(t_FmPcdCcNextEngineParams));
++
++    /* Check that manip is legal and what requiredAction is necessary for this manip */
++    if (p_CcNextEngineParams->h_Manip)
++    {
++        err = FmPcdManipCheckParamsForCcNextEngine(p_CcNextEngineParams,
++                                                   &requiredAction);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    if (!p_AdditionalInfo->tree)
++    {
++        p_FmPcdCcNode1 = (t_FmPcdCcNode *)h_FmPcdCcNodeOrTree;
++        p_AdditionalInfo->numOfKeys = p_FmPcdCcNode1->numOfKeys;
++        p_Ad = p_FmPcdCcNode1->h_AdTable;
++
++        if (p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++                == e_FM_PCD_CC)
++            p_AdditionalInfo->h_NodeForRmv =
++                    p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode;
++
++        if (p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip)
++            p_AdditionalInfo->h_ManipForRmv =
++                    p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip;
++
++#if (DPAA_VERSION >= 11)
++        if ((p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++                == e_FM_PCD_FR)
++                && (p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic))
++            p_AdditionalInfo->h_FrmReplicForRmv =
++                    p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic;
++#endif /* (DPAA_VERSION >= 11) */
++    }
++    else
++    {
++        p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcNodeOrTree;
++        p_Ad = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr);
++
++        if (p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++                == e_FM_PCD_CC)
++            p_AdditionalInfo->h_NodeForRmv =
++                    p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode;
++
++        if (p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip)
++            p_AdditionalInfo->h_ManipForRmv =
++                    p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip;
++
++#if (DPAA_VERSION >= 11)
++        if ((p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine
++                == e_FM_PCD_FR)
++                && (p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic))
++            p_AdditionalInfo->h_FrmReplicForRmv =
++                    p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic;
++#endif /* (DPAA_VERSION >= 11) */
++    }
++
++    if ((p_CcNextEngineParams->nextEngine == e_FM_PCD_CC)
++            && p_CcNextEngineParams->h_Manip)
++    {
++        err = AllocAndFillAdForContLookupManip(
++                p_CcNextEngineParams->params.ccParams.h_CcNode);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    ASSERT_COND(p_Ad);
++
++    memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++    ccNodeInfo.h_CcNode = PTR_MOVE(p_Ad, keyIndex * FM_PCD_CC_AD_ENTRY_SIZE);
++
++    /* If statistics were enabled, this Ad is the statistics Ad. Need to follow its
++     nextAction to retrieve the actual Nia-Ad. If statistics should remain enabled,
++     only the actual Nia-Ad should be modified. */
++    if ((!p_AdditionalInfo->tree)
++            && (((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj)
++            && (p_CcNextEngineParams->statisticsEn))
++        ccNodeInfo.h_CcNode =
++                ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsAd;
++
++    EnqueueNodeInfoToRelevantLst(h_OldLst, &ccNodeInfo, NULL);
++
++    memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++    p_Ad = GetNewAd(h_FmPcdCcNodeOrTree, p_AdditionalInfo->tree);
++    if (!p_Ad)
++        RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                     ("MURAM allocation for CC node action descriptor"));
++    IOMemSet32((uint8_t *)p_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE);
++
++    /* If statistics were not enabled before, but requested now -  Allocate a statistics
++     object that holds statistics AD and counters. */
++    if ((!p_AdditionalInfo->tree)
++            && (!((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj)
++            && (p_CcNextEngineParams->statisticsEn))
++    {
++        p_StatsObj = GetStatsObj((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree);
++        ASSERT_COND(p_StatsObj);
++
++        /* Store allocated statistics object */
++        p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj =
++                p_StatsObj;
++
++        statsParams.h_StatsAd = p_StatsObj->h_StatsAd;
++        statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters;
++
++#if (DPAA_VERSION >= 11)
++        statsParams.h_StatsFLRs =
++                ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->h_StatsFLRs;
++
++#endif /* (DPAA_VERSION >= 11) */
++
++        NextStepAd(p_Ad, &statsParams, p_CcNextEngineParams, h_FmPcd);
++    }
++    else
++        NextStepAd(p_Ad, NULL, p_CcNextEngineParams, h_FmPcd);
++
++    ccNodeInfo.h_CcNode = p_Ad;
++    EnqueueNodeInfoToRelevantLst(h_NewLst, &ccNodeInfo, NULL);
++
++    p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction =
++            requiredAction;
++    p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction |=
++            UPDATE_CC_WITH_TREE;
++
++    if (!p_AdditionalInfo->tree)
++    {
++        ASSERT_COND(p_FmPcdCcNode1);
++        if (!LIST_IsEmpty(&p_FmPcdCcNode1->ccTreesLst))
++        {
++            LIST_FOR_EACH(p_Pos, &p_FmPcdCcNode1->ccTreesLst)
++            {
++                p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos);
++
++                ASSERT_COND(p_CcNodeInformation->h_CcNode);
++                /* Update the manipulation which has to be updated from parameters of the port
++                 it's has to be updated with restrictions defined in the function */
++
++                err =
++                        SetRequiredAction(
++                                p_FmPcdCcNode1->h_FmPcd,
++                                p_FmPcdCcNode1->shadowAction
++                                        | p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction,
++                                &p_AdditionalInfo->keyAndNextEngineParams[keyIndex],
++                                p_Ad, 1, p_CcNodeInformation->h_CcNode);
++                if (err)
++                    RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++                err = CcUpdateParam(
++                        p_FmPcdCcNode1->h_FmPcd, NULL, NULL,
++                        &p_AdditionalInfo->keyAndNextEngineParams[keyIndex], 1,
++                        p_Ad, TRUE, p_CcNodeInformation->index,
++                        p_CcNodeInformation->h_CcNode, TRUE);
++                if (err)
++                    RETURN_ERROR(MAJOR, err, (NO_MSG));
++            }
++        }
++    }
++    else
++    {
++        ASSERT_COND(p_FmPcdCcTree);
++
++        err =
++                SetRequiredAction(
++                        h_FmPcd,
++                        p_FmPcdCcTree->requiredAction
++                                | p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction,
++                        &p_AdditionalInfo->keyAndNextEngineParams[keyIndex],
++                        p_Ad, 1, (t_Handle)p_FmPcdCcTree);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++        err = CcUpdateParam(h_FmPcd, NULL, NULL,
++                            &p_AdditionalInfo->keyAndNextEngineParams[keyIndex],
++                            1, p_Ad, TRUE, 0, (t_Handle)p_FmPcdCcTree, TRUE);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    if (p_CcNextEngineParams->nextEngine == e_FM_PCD_CC)
++        p_AdditionalInfo->h_NodeForAdd =
++                p_CcNextEngineParams->params.ccParams.h_CcNode;
++    if (p_CcNextEngineParams->h_Manip)
++        p_AdditionalInfo->h_ManipForAdd = p_CcNextEngineParams->h_Manip;
++
++    /* If statistics were previously enabled, but now are disabled,
++     store the old statistics object to be released */
++    if ((!p_AdditionalInfo->tree)
++            && (((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj)
++            && (!p_CcNextEngineParams->statisticsEn))
++    {
++        p_AdditionalInfo->p_StatsObjForRmv =
++                ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj;
++
++
++        p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj = NULL;
++    }
++#if (DPAA_VERSION >= 11)
++    if ((p_CcNextEngineParams->nextEngine == e_FM_PCD_FR)
++            && (p_CcNextEngineParams->params.frParams.h_FrmReplic))
++        p_AdditionalInfo->h_FrmReplicForAdd =
++                p_CcNextEngineParams->params.frParams.h_FrmReplic;
++#endif /* (DPAA_VERSION >= 11) */
++
++    return E_OK;
++}
++
++static void UpdateAdPtrOfNodesWhichPointsOnCrntMdfNode(
++        t_FmPcdCcNode *p_CrntMdfNode, t_List *h_OldLst,
++        t_FmPcdCcNextEngineParams **p_NextEngineParams)
++{
++    t_CcNodeInformation *p_CcNodeInformation;
++    t_FmPcdCcNode *p_NodePtrOnCurrentMdfNode = NULL;
++    t_List *p_Pos;
++    int i = 0;
++    t_Handle p_AdTablePtOnCrntCurrentMdfNode/*, p_AdTableNewModified*/;
++    t_CcNodeInformation ccNodeInfo;
++
++    LIST_FOR_EACH(p_Pos, &p_CrntMdfNode->ccPrevNodesLst)
++    {
++        p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos);
++        p_NodePtrOnCurrentMdfNode =
++                (t_FmPcdCcNode *)p_CcNodeInformation->h_CcNode;
++
++        ASSERT_COND(p_NodePtrOnCurrentMdfNode);
++
++        /* Search in the previous node which exact index points on this current modified node for getting AD */
++        for (i = 0; i < p_NodePtrOnCurrentMdfNode->numOfKeys + 1; i++)
++        {
++            if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine
++                    == e_FM_PCD_CC)
++            {
++                if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode
++                        == (t_Handle)p_CrntMdfNode)
++                {
++                    if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip)
++                        p_AdTablePtOnCrntCurrentMdfNode = p_CrntMdfNode->h_Ad;
++                    else
++                        if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].p_StatsObj)
++                            p_AdTablePtOnCrntCurrentMdfNode =
++                                    p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].p_StatsObj->h_StatsAd;
++                        else
++                            p_AdTablePtOnCrntCurrentMdfNode =
++                                    PTR_MOVE(p_NodePtrOnCurrentMdfNode->h_AdTable, i*FM_PCD_CC_AD_ENTRY_SIZE);
++
++                    memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++                    ccNodeInfo.h_CcNode = p_AdTablePtOnCrntCurrentMdfNode;
++                    EnqueueNodeInfoToRelevantLst(h_OldLst, &ccNodeInfo, NULL);
++
++                    if (!(*p_NextEngineParams))
++                        *p_NextEngineParams =
++                                &p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams;
++                }
++            }
++        }
++
++        ASSERT_COND(i != p_NodePtrOnCurrentMdfNode->numOfKeys);
++    }
++}
++
++static void UpdateAdPtrOfTreesWhichPointsOnCrntMdfNode(
++        t_FmPcdCcNode *p_CrntMdfNode, t_List *h_OldLst,
++        t_FmPcdCcNextEngineParams **p_NextEngineParams)
++{
++    t_CcNodeInformation *p_CcNodeInformation;
++    t_FmPcdCcTree *p_TreePtrOnCurrentMdfNode = NULL;
++    t_List *p_Pos;
++    int i = 0;
++    t_Handle p_AdTableTmp;
++    t_CcNodeInformation ccNodeInfo;
++
++    LIST_FOR_EACH(p_Pos, &p_CrntMdfNode->ccTreeIdLst)
++    {
++        p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos);
++        p_TreePtrOnCurrentMdfNode =
++                (t_FmPcdCcTree *)p_CcNodeInformation->h_CcNode;
++
++        ASSERT_COND(p_TreePtrOnCurrentMdfNode);
++
++        /*search in the trees which exact index points on this current modified node for getting AD */
++        for (i = 0; i < p_TreePtrOnCurrentMdfNode->numOfEntries; i++)
++        {
++            if (p_TreePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine
++                    == e_FM_PCD_CC)
++            {
++                if (p_TreePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode
++                        == (t_Handle)p_CrntMdfNode)
++                {
++                    p_AdTableTmp =
++                            UINT_TO_PTR(p_TreePtrOnCurrentMdfNode->ccTreeBaseAddr + i*FM_PCD_CC_AD_ENTRY_SIZE);
++                    memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++                    ccNodeInfo.h_CcNode = p_AdTableTmp;
++                    EnqueueNodeInfoToRelevantLst(h_OldLst, &ccNodeInfo, NULL);
++
++                    if (!(*p_NextEngineParams))
++                        *p_NextEngineParams =
++                                &p_TreePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams;
++                }
++            }
++        }
++
++        ASSERT_COND(i == p_TreePtrOnCurrentMdfNode->numOfEntries);
++    }
++}
++
++static t_FmPcdModifyCcKeyAdditionalParams * ModifyNodeCommonPart(
++        t_Handle h_FmPcdCcNodeOrTree, uint16_t keyIndex,
++        e_ModifyState modifyState, bool ttlCheck, bool hashCheck, bool tree)
++{
++    t_FmPcdModifyCcKeyAdditionalParams *p_FmPcdModifyCcKeyAdditionalParams;
++    int i = 0, j = 0;
++    bool wasUpdate = FALSE;
++    t_FmPcdCcNode *p_CcNode = NULL;
++    t_FmPcdCcTree *p_FmPcdCcTree;
++    uint16_t numOfKeys;
++    t_FmPcdCcKeyAndNextEngineParams *p_KeyAndNextEngineParams;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmPcdCcNodeOrTree, E_INVALID_HANDLE, NULL);
++
++    if (!tree)
++    {
++        p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNodeOrTree;
++        numOfKeys = p_CcNode->numOfKeys;
++
++        /* node has to be pointed by another node or tree */
++
++        p_KeyAndNextEngineParams = (t_FmPcdCcKeyAndNextEngineParams *)XX_Malloc(
++                sizeof(t_FmPcdCcKeyAndNextEngineParams) * (numOfKeys + 1));
++        if (!p_KeyAndNextEngineParams)
++        {
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Next engine and required action structure"));
++            return NULL;
++        }
++        memcpy(p_KeyAndNextEngineParams, p_CcNode->keyAndNextEngineParams,
++               (numOfKeys + 1) * sizeof(t_FmPcdCcKeyAndNextEngineParams));
++
++        if (ttlCheck)
++        {
++            if ((p_CcNode->parseCode == CC_PC_FF_IPV4TTL)
++                    || (p_CcNode->parseCode == CC_PC_FF_IPV6HOP_LIMIT))
++            {
++                XX_Free(p_KeyAndNextEngineParams);
++                REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("nodeId of CC_PC_FF_IPV4TTL or CC_PC_FF_IPV6HOP_LIMIT can not be used for this operation"));
++                return NULL;
++            }
++        }
++
++        if (hashCheck)
++        {
++            if (p_CcNode->parseCode == CC_PC_GENERIC_IC_HASH_INDEXED)
++            {
++                XX_Free(p_KeyAndNextEngineParams);
++                REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("nodeId of CC_PC_GENERIC_IC_HASH_INDEXED can not be used for this operation"));
++                return NULL;
++            }
++        }
++    }
++    else
++    {
++        p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcNodeOrTree;
++        numOfKeys = p_FmPcdCcTree->numOfEntries;
++
++        p_KeyAndNextEngineParams = (t_FmPcdCcKeyAndNextEngineParams *)XX_Malloc(
++                sizeof(t_FmPcdCcKeyAndNextEngineParams)
++                        * FM_PCD_MAX_NUM_OF_CC_GROUPS);
++        if (!p_KeyAndNextEngineParams)
++        {
++            REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Next engine and required action structure"));
++            return NULL;
++        }
++        memcpy(p_KeyAndNextEngineParams,
++               p_FmPcdCcTree->keyAndNextEngineParams,
++               FM_PCD_MAX_NUM_OF_CC_GROUPS
++                       * sizeof(t_FmPcdCcKeyAndNextEngineParams));
++    }
++
++    p_FmPcdModifyCcKeyAdditionalParams =
++            (t_FmPcdModifyCcKeyAdditionalParams *)XX_Malloc(
++                    sizeof(t_FmPcdModifyCcKeyAdditionalParams));
++    if (!p_FmPcdModifyCcKeyAdditionalParams)
++    {
++        XX_Free(p_KeyAndNextEngineParams);
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Allocation of internal data structure FAILED"));
++        return NULL;
++    }
++    memset(p_FmPcdModifyCcKeyAdditionalParams, 0,
++           sizeof(t_FmPcdModifyCcKeyAdditionalParams));
++
++    p_FmPcdModifyCcKeyAdditionalParams->h_CurrentNode = h_FmPcdCcNodeOrTree;
++    p_FmPcdModifyCcKeyAdditionalParams->savedKeyIndex = keyIndex;
++
++    while (i < numOfKeys)
++    {
++        if ((j == keyIndex) && !wasUpdate)
++        {
++            if (modifyState == e_MODIFY_STATE_ADD)
++                j++;
++            else
++                if (modifyState == e_MODIFY_STATE_REMOVE)
++                    i++;
++            wasUpdate = TRUE;
++        }
++        else
++        {
++            memcpy(&p_FmPcdModifyCcKeyAdditionalParams->keyAndNextEngineParams[j],
++                   p_KeyAndNextEngineParams + i,
++                   sizeof(t_FmPcdCcKeyAndNextEngineParams));
++            i++;
++            j++;
++        }
++    }
++
++    if (keyIndex == numOfKeys)
++    {
++        if (modifyState == e_MODIFY_STATE_ADD)
++            j++;
++    }
++
++    memcpy(&p_FmPcdModifyCcKeyAdditionalParams->keyAndNextEngineParams[j],
++           p_KeyAndNextEngineParams + numOfKeys,
++           sizeof(t_FmPcdCcKeyAndNextEngineParams));
++
++    XX_Free(p_KeyAndNextEngineParams);
++
++    return p_FmPcdModifyCcKeyAdditionalParams;
++}
++
++static t_Error UpdatePtrWhichPointOnCrntMdfNode(
++        t_FmPcdCcNode *p_CcNode,
++        t_FmPcdModifyCcKeyAdditionalParams *p_FmPcdModifyCcKeyAdditionalParams,
++        t_List *h_OldLst, t_List *h_NewLst)
++{
++    t_FmPcdCcNextEngineParams *p_NextEngineParams = NULL;
++    t_CcNodeInformation ccNodeInfo = { 0 };
++    t_Handle h_NewAd;
++    t_Handle h_OrigAd = NULL;
++
++    /* Building a list of all action descriptors that point to the previous node */
++    if (!LIST_IsEmpty(&p_CcNode->ccPrevNodesLst))
++        UpdateAdPtrOfNodesWhichPointsOnCrntMdfNode(p_CcNode, h_OldLst,
++                                                   &p_NextEngineParams);
++
++    if (!LIST_IsEmpty(&p_CcNode->ccTreeIdLst))
++        UpdateAdPtrOfTreesWhichPointsOnCrntMdfNode(p_CcNode, h_OldLst,
++                                                   &p_NextEngineParams);
++
++    /* This node must be found as next engine of one of its previous nodes or trees*/
++    if (p_NextEngineParams)
++    {
++        /* Building a new action descriptor that points to the modified node */
++        h_NewAd = GetNewAd(p_CcNode, FALSE);
++        if (!h_NewAd)
++            RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG);
++        IOMemSet32(h_NewAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
++
++        h_OrigAd = p_CcNode->h_Ad;
++        BuildNewAd(h_NewAd, p_FmPcdModifyCcKeyAdditionalParams, p_CcNode,
++                   p_NextEngineParams);
++
++        ccNodeInfo.h_CcNode = h_NewAd;
++        EnqueueNodeInfoToRelevantLst(h_NewLst, &ccNodeInfo, NULL);
++
++        if (p_NextEngineParams->h_Manip && !h_OrigAd)
++            FmPcdManipUpdateOwner(p_NextEngineParams->h_Manip, FALSE);
++    }
++    return E_OK;
++}
++
++static void UpdateCcRootOwner(t_FmPcdCcTree *p_FmPcdCcTree, bool add)
++{
++    ASSERT_COND(p_FmPcdCcTree);
++
++    /* this routine must be protected by the calling routine! */
++
++    if (add)
++        p_FmPcdCcTree->owners++;
++    else
++    {
++        ASSERT_COND(p_FmPcdCcTree->owners);
++        p_FmPcdCcTree->owners--;
++    }
++}
++
++static t_Error CheckAndSetManipParamsWithCcNodeParams(t_FmPcdCcNode *p_CcNode)
++{
++    t_Error err = E_OK;
++    int i = 0;
++
++    for (i = 0; i < p_CcNode->numOfKeys; i++)
++    {
++        if (p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip)
++        {
++            err =
++                    FmPcdManipCheckParamsWithCcNodeParams(
++                            p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip,
++                            (t_Handle)p_CcNode);
++            if (err)
++                return err;
++        }
++    }
++
++    return err;
++}
++static t_Error ValidateAndCalcStatsParams(t_FmPcdCcNode *p_CcNode,
++                                          t_FmPcdCcNodeParams *p_CcNodeParam,
++                                          uint32_t *p_NumOfRanges,
++                                          uint32_t *p_CountersArraySize)
++{
++    e_FmPcdCcStatsMode statisticsMode = p_CcNode->statisticsMode;
++    uint32_t i;
++
++    UNUSED(p_CcNodeParam);
++
++    switch (statisticsMode)
++    {
++        case e_FM_PCD_CC_STATS_MODE_NONE:
++            for (i = 0; i < p_CcNode->numOfKeys; i++)
++                if (p_CcNodeParam->keysParams.keyParams[i].ccNextEngineParams.statisticsEn)
++                    RETURN_ERROR(
++                            MAJOR,
++                            E_INVALID_VALUE,
++                            ("Statistics cannot be enabled for key %d when statistics mode was set to 'NONE'", i));
++            return E_OK;
++
++        case e_FM_PCD_CC_STATS_MODE_FRAME:
++        case e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME:
++            *p_NumOfRanges = 1;
++            *p_CountersArraySize = 2 * FM_PCD_CC_STATS_COUNTER_SIZE;
++            return E_OK;
++
++#if (DPAA_VERSION >= 11)
++        case e_FM_PCD_CC_STATS_MODE_RMON:
++        {
++            uint16_t *p_FrameLengthRanges =
++                    p_CcNodeParam->keysParams.frameLengthRanges;
++            uint32_t i;
++
++            if (p_FrameLengthRanges[0] <= 0)
++                RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Statistics mode"));
++
++            if (p_FrameLengthRanges[0] == 0xFFFF)
++            {
++                *p_NumOfRanges = 1;
++                *p_CountersArraySize = 2 * FM_PCD_CC_STATS_COUNTER_SIZE;
++                return E_OK;
++            }
++
++            for (i = 1; i < FM_PCD_CC_STATS_MAX_NUM_OF_FLR; i++)
++            {
++                if (p_FrameLengthRanges[i - 1] >= p_FrameLengthRanges[i])
++                    RETURN_ERROR(
++                            MAJOR,
++                            E_INVALID_VALUE,
++                            ("Frame length range must be larger at least by 1 from preceding range"));
++
++                /* Stop when last range is reached */
++                if (p_FrameLengthRanges[i] == 0xFFFF)
++                    break;
++            }
++
++            if ((i >= FM_PCD_CC_STATS_MAX_NUM_OF_FLR)
++                    || (p_FrameLengthRanges[i] != 0xFFFF))
++                RETURN_ERROR(MAJOR, E_INVALID_VALUE,
++                             ("Last Frame length range must be 0xFFFF"));
++
++            *p_NumOfRanges = i + 1;
++
++            /* Allocate an extra counter for byte count, as counters
++             array always begins with byte count */
++            *p_CountersArraySize = (*p_NumOfRanges + 1)
++                    * FM_PCD_CC_STATS_COUNTER_SIZE;
++
++        }
++            return E_OK;
++#endif /* (DPAA_VERSION >= 11) */
++
++        default:
++            RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Statistics mode"));
++    }
++}
++
++static t_Error CheckParams(t_Handle h_FmPcd, t_FmPcdCcNodeParams *p_CcNodeParam,
++                           t_FmPcdCcNode *p_CcNode, bool *isKeyTblAlloc)
++{
++    int tmp = 0;
++    t_FmPcdCcKeyParams *p_KeyParams;
++    t_Error err;
++    uint32_t requiredAction = 0;
++
++    /* Validate statistics parameters */
++    err = ValidateAndCalcStatsParams(p_CcNode, p_CcNodeParam,
++                                     &(p_CcNode->numOfStatsFLRs),
++                                     &(p_CcNode->countersArraySize));
++    if (err)
++        RETURN_ERROR(MAJOR, err, ("Invalid statistics parameters"));
++
++    /* Validate next engine parameters on Miss */
++    err = ValidateNextEngineParams(
++            h_FmPcd, &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++            p_CcNode->statisticsMode);
++    if (err)
++        RETURN_ERROR(MAJOR, err,
++                     ("For this node MissNextEngineParams are not valid"));
++
++    if (p_CcNodeParam->keysParams.ccNextEngineParamsForMiss.h_Manip)
++    {
++        err = FmPcdManipCheckParamsForCcNextEngine(
++                &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++                &requiredAction);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    memcpy(&p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams,
++           &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++           sizeof(t_FmPcdCcNextEngineParams));
++
++    p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].requiredAction =
++            requiredAction;
++
++    if ((p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine
++            == e_FM_PCD_CC)
++            && p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.h_Manip)
++    {
++        err =
++                AllocAndFillAdForContLookupManip(
++                        p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.params.ccParams.h_CcNode);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++)
++    {
++        p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp];
++
++        if (!p_KeyParams->p_Key)
++            RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_Key is not initialized"));
++
++        err = ValidateNextEngineParams(h_FmPcd,
++                                       &p_KeyParams->ccNextEngineParams,
++                                       p_CcNode->statisticsMode);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++        err = UpdateGblMask(p_CcNode, p_CcNodeParam->keysParams.keySize,
++                            p_KeyParams->p_Mask);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++        if (p_KeyParams->ccNextEngineParams.h_Manip)
++        {
++            err = FmPcdManipCheckParamsForCcNextEngine(
++                    &p_KeyParams->ccNextEngineParams, &requiredAction);
++            if (err)
++                RETURN_ERROR(MAJOR, err, (NO_MSG));
++        }
++
++        /* Store 'key' parameters - key, mask (if passed by the user) */
++        memcpy(p_CcNode->keyAndNextEngineParams[tmp].key, p_KeyParams->p_Key,
++               p_CcNodeParam->keysParams.keySize);
++
++        if (p_KeyParams->p_Mask)
++            memcpy(p_CcNode->keyAndNextEngineParams[tmp].mask,
++                   p_KeyParams->p_Mask, p_CcNodeParam->keysParams.keySize);
++        else
++            memset((void *)(p_CcNode->keyAndNextEngineParams[tmp].mask), 0xFF,
++                   p_CcNodeParam->keysParams.keySize);
++
++        /* Store next engine parameters */
++        memcpy(&p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams,
++               &p_KeyParams->ccNextEngineParams,
++               sizeof(t_FmPcdCcNextEngineParams));
++
++        p_CcNode->keyAndNextEngineParams[tmp].requiredAction = requiredAction;
++
++        if ((p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine
++                == e_FM_PCD_CC)
++                && p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip)
++        {
++            err =
++                    AllocAndFillAdForContLookupManip(
++                            p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode);
++            if (err)
++                RETURN_ERROR(MAJOR, err, (NO_MSG));
++        }
++    }
++
++    if (p_CcNode->maxNumOfKeys)
++    {
++        if (p_CcNode->maxNumOfKeys < p_CcNode->numOfKeys)
++            RETURN_ERROR(
++                    MAJOR,
++                    E_INVALID_VALUE,
++                    ("Number of keys exceed the provided maximal number of keys"));
++    }
++
++    *isKeyTblAlloc = TRUE;
++
++    return E_OK;
++}
++
++static t_Error Ipv4TtlOrIpv6HopLimitCheckParams(
++        t_Handle h_FmPcd, t_FmPcdCcNodeParams *p_CcNodeParam,
++        t_FmPcdCcNode *p_CcNode, bool *isKeyTblAlloc)
++{
++    int tmp = 0;
++    t_FmPcdCcKeyParams *p_KeyParams;
++    t_Error err;
++    uint8_t key = 0x01;
++    uint32_t requiredAction = 0;
++
++    if (p_CcNode->numOfKeys != 1)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT the maximal supported 'numOfKeys' is 1"));
++
++    if ((p_CcNodeParam->keysParams.maxNumOfKeys)
++            && (p_CcNodeParam->keysParams.maxNumOfKeys != 1))
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT the maximal supported 'maxNumOfKeys' is 1"));
++
++    /* Validate statistics parameters */
++    err = ValidateAndCalcStatsParams(p_CcNode, p_CcNodeParam,
++                                     &(p_CcNode->numOfStatsFLRs),
++                                     &(p_CcNode->countersArraySize));
++    if (err)
++        RETURN_ERROR(MAJOR, err, ("Invalid statistics parameters"));
++
++    err = ValidateNextEngineParams(
++            h_FmPcd, &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++            p_CcNodeParam->keysParams.statisticsMode);
++    if (err)
++        RETURN_ERROR(MAJOR, err,
++                     ("For this node MissNextEngineParams are not valid"));
++
++    if (p_CcNodeParam->keysParams.ccNextEngineParamsForMiss.h_Manip)
++    {
++        err = FmPcdManipCheckParamsForCcNextEngine(
++                &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++                &requiredAction);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    memcpy(&p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams,
++           &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++           sizeof(t_FmPcdCcNextEngineParams));
++
++    p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].requiredAction =
++            requiredAction;
++
++    if ((p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine
++            == e_FM_PCD_CC)
++            && p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.h_Manip)
++    {
++        err =
++                AllocAndFillAdForContLookupManip(
++                        p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.params.ccParams.h_CcNode);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++    }
++
++    for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++)
++    {
++        p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp];
++
++        if (p_KeyParams->p_Mask)
++            RETURN_ERROR(
++                    MAJOR,
++                    E_INVALID_VALUE,
++                    ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT p_Mask can not be initialized"));
++
++        if (memcmp(p_KeyParams->p_Key, &key, 1) != 0)
++            RETURN_ERROR(
++                    MAJOR,
++                    E_INVALID_VALUE,
++                    ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT p_Key has to be 1"));
++
++        err = ValidateNextEngineParams(h_FmPcd,
++                                       &p_KeyParams->ccNextEngineParams,
++                                       p_CcNode->statisticsMode);
++        if (err)
++            RETURN_ERROR(MAJOR, err, (NO_MSG));
++
++        if (p_KeyParams->ccNextEngineParams.h_Manip)
++        {
++            err = FmPcdManipCheckParamsForCcNextEngine(
++                    &p_KeyParams->ccNextEngineParams, &requiredAction);
++            if (err)
++                RETURN_ERROR(MAJOR, err, (NO_MSG));
++        }
++
++        /* Store 'key' parameters - key (fixed to 0x01), key size of 1 byte and full mask */
++        p_CcNode->keyAndNextEngineParams[tmp].key[0] = key;
++        p_CcNode->keyAndNextEngineParams[tmp].mask[0] = 0xFF;
++
++        /* Store NextEngine parameters */
++        memcpy(&p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams,
++               &p_KeyParams->ccNextEngineParams,
++               sizeof(t_FmPcdCcNextEngineParams));
++
++        if ((p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine
++                == e_FM_PCD_CC)
++                && p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip)
++        {
++            err =
++                    AllocAndFillAdForContLookupManip(
++                            p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode);
++            if (err)
++                RETURN_ERROR(MAJOR, err, (NO_MSG));
++        }
++        p_CcNode->keyAndNextEngineParams[tmp].requiredAction = requiredAction;
++    }
++
++    *isKeyTblAlloc = FALSE;
++
++    return E_OK;
++}
++
++static t_Error IcHashIndexedCheckParams(t_Handle h_FmPcd,
++                                        t_FmPcdCcNodeParams *p_CcNodeParam,
++                                        t_FmPcdCcNode *p_CcNode,
++                                        bool *isKeyTblAlloc)
++{
++    int tmp = 0, countOnes = 0;
++    t_FmPcdCcKeyParams *p_KeyParams;
++    t_Error err;
++    uint16_t glblMask = p_CcNodeParam->extractCcParams.extractNonHdr.icIndxMask;
++    uint16_t countMask = (uint16_t)(glblMask >> 4);
++    uint32_t requiredAction = 0;
++
++    if (glblMask & 0x000f)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE,
++                     ("icIndxMask has to be with last nibble 0"));
++
++    while (countMask)
++    {
++        countOnes++;
++        countMask = (uint16_t)(countMask >> 1);
++    }
++
++    if (!POWER_OF_2(p_CcNode->numOfKeys))
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("For Node of the type INDEXED numOfKeys has to be powerOfTwo"));
++
++    if (p_CcNode->numOfKeys != ((uint32_t)1 << countOnes))
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("For Node of the type IC_HASH_INDEXED numOfKeys has to be powerOfTwo"));
++
++    if (p_CcNodeParam->keysParams.maxNumOfKeys
++            && (p_CcNodeParam->keysParams.maxNumOfKeys != p_CcNode->numOfKeys))
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("For Node of the type INDEXED 'maxNumOfKeys' should be 0 or equal 'numOfKeys'"));
++
++    /* Validate statistics parameters */
++    err = ValidateAndCalcStatsParams(p_CcNode, p_CcNodeParam,
++                                     &(p_CcNode->numOfStatsFLRs),
++                                     &(p_CcNode->countersArraySize));
++    if (err)
++        RETURN_ERROR(MAJOR, err, ("Invalid statistics parameters"));
++
++    err = ValidateNextEngineParams(
++            h_FmPcd, &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++            p_CcNode->statisticsMode);
++    if (GET_ERROR_TYPE(err) != E_NOT_SUPPORTED)
++        RETURN_ERROR(
++                MAJOR,
++                err,
++                ("MissNextEngineParams for the node of the type IC_INDEX_HASH has to be UnInitialized"));
++
++    for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++)
++    {
++        p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp];
++
++        if (p_KeyParams->p_Mask || p_KeyParams->p_Key)
++            RETURN_ERROR(
++                    MAJOR,
++                    E_INVALID_VALUE,
++                    ("For Node of the type IC_HASH_INDEXED p_Key or p_Mask has to be NULL"));
++
++        if ((glblMask & (tmp * 16)) == (tmp * 16))
++        {
++            err = ValidateNextEngineParams(h_FmPcd,
++                                           &p_KeyParams->ccNextEngineParams,
++                                           p_CcNode->statisticsMode);
++            if (err)
++                RETURN_ERROR(
++                        MAJOR,
++                        err,
++                        ("This index has to be initialized for the node of the type IC_INDEX_HASH according to settings of GlobalMask "));
++
++            if (p_KeyParams->ccNextEngineParams.h_Manip)
++            {
++                err = FmPcdManipCheckParamsForCcNextEngine(
++                        &p_KeyParams->ccNextEngineParams, &requiredAction);
++                if (err)
++                    RETURN_ERROR(MAJOR, err, (NO_MSG));
++                p_CcNode->keyAndNextEngineParams[tmp].requiredAction =
++                        requiredAction;
++            }
++
++            memcpy(&p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams,
++                   &p_KeyParams->ccNextEngineParams,
++                   sizeof(t_FmPcdCcNextEngineParams));
++
++            if ((p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine
++                    == e_FM_PCD_CC)
++                    && p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip)
++            {
++                err =
++                        AllocAndFillAdForContLookupManip(
++                                p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode);
++                if (err)
++                    RETURN_ERROR(MAJOR, err, (NO_MSG));
++            }
++        }
++        else
++        {
++            err = ValidateNextEngineParams(h_FmPcd,
++                                           &p_KeyParams->ccNextEngineParams,
++                                           p_CcNode->statisticsMode);
++            if (GET_ERROR_TYPE(err) != E_NOT_SUPPORTED)
++                RETURN_ERROR(
++                        MAJOR,
++                        err,
++                        ("This index has to be UnInitialized for the node of the type IC_INDEX_HASH according to settings of GlobalMask"));
++        }
++    }
++
++    *isKeyTblAlloc = FALSE;
++    memcpy(PTR_MOVE(p_CcNode->p_GlblMask, 2), &glblMask, 2);
++
++    return E_OK;
++}
++
++static t_Error ModifyNextEngineParamNode(
++        t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, uint16_t keyIndex,
++        t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode;
++    t_FmPcd *p_FmPcd;
++    t_List h_OldPointersLst, h_NewPointersLst;
++    t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams;
++    t_Error err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_VALUE);
++    SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE);
++
++    if (keyIndex >= p_CcNode->numOfKeys)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                     ("keyIndex > previously cleared last index + 1"));
++
++    p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++
++    INIT_LIST(&h_OldPointersLst);
++    INIT_LIST(&h_NewPointersLst);
++
++    p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex,
++                                             e_MODIFY_STATE_CHANGE, FALSE,
++                                             FALSE, FALSE);
++    if (!p_ModifyKeyParams)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++
++    if (p_CcNode->maxNumOfKeys
++            && !TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
++    {
++        XX_Free(p_ModifyKeyParams);
++        return ERROR_CODE(E_BUSY);
++    }
++
++    err = BuildNewNodeModifyNextEngine(h_FmPcd, p_CcNode, keyIndex,
++                                       p_FmPcdCcNextEngineParams,
++                                       &h_OldPointersLst, &h_NewPointersLst,
++                                       p_ModifyKeyParams);
++    if (err)
++    {
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst,
++                          p_ModifyKeyParams, FALSE);
++
++    if (p_CcNode->maxNumOfKeys)
++        RELEASE_LOCK(p_FmPcd->shadowLock);
++
++    return err;
++}
++
++static t_Error FindKeyIndex(t_Handle h_CcNode, uint8_t keySize, uint8_t *p_Key,
++                            uint8_t *p_Mask, uint16_t *p_KeyIndex)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode;
++    uint8_t tmpMask[FM_PCD_MAX_SIZE_OF_KEY];
++    uint16_t i;
++
++    ASSERT_COND(p_Key);
++    ASSERT_COND(p_KeyIndex);
++    ASSERT_COND(keySize < FM_PCD_MAX_SIZE_OF_KEY);
++
++    if (keySize != p_CcNode->userSizeOfExtraction)
++        RETURN_ERROR(
++                MINOR, E_INVALID_VALUE,
++                ("Key size doesn't match the extraction size of the node"));
++
++    /* If user didn't pass a mask for this key, we'll look for full extraction mask */
++    if (!p_Mask)
++        memset(tmpMask, 0xFF, keySize);
++
++    for (i = 0; i < p_CcNode->numOfKeys; i++)
++    {
++        /* Comparing received key */
++        if (memcmp(p_Key, p_CcNode->keyAndNextEngineParams[i].key, keySize)
++                == 0)
++        {
++            if (p_Mask)
++            {
++                /* If a user passed a mask for this key, it must match to the existing key's mask for a correct match */
++                if (memcmp(p_Mask, p_CcNode->keyAndNextEngineParams[i].mask,
++                           keySize) == 0)
++                {
++                    *p_KeyIndex = i;
++                    return E_OK;
++                }
++            }
++            else
++            {
++                /* If user didn't pass a mask for this key, check if the existing key mask is full extraction */
++                if (memcmp(tmpMask, p_CcNode->keyAndNextEngineParams[i].mask,
++                           keySize) == 0)
++                {
++                    *p_KeyIndex = i;
++                    return E_OK;
++                }
++            }
++        }
++    }
++
++    return ERROR_CODE(E_NOT_FOUND);
++}
++
++static t_Error CalcAndUpdateCcShadow(t_FmPcdCcNode *p_CcNode,
++                                     bool isKeyTblAlloc,
++                                     uint32_t *p_MatchTableSize,
++                                     uint32_t *p_AdTableSize)
++{
++    uint32_t shadowSize;
++    t_Error err;
++
++    /* Calculate keys table maximal size - each entry consists of a key and a mask,
++     (if local mask support is requested) */
++    *p_MatchTableSize = p_CcNode->ccKeySizeAccExtraction * sizeof(uint8_t)
++            * p_CcNode->maxNumOfKeys;
++
++    if (p_CcNode->maskSupport)
++        *p_MatchTableSize *= 2;
++
++    /* Calculate next action descriptors table, including one more entry for miss */
++    *p_AdTableSize = (uint32_t)((p_CcNode->maxNumOfKeys + 1)
++            * FM_PCD_CC_AD_ENTRY_SIZE);
++
++    /* Calculate maximal shadow size of this node.
++     All shadow structures will be used for runtime modifications host command. If
++     keys table was allocated for this node, the keys table and next engines table may
++     be modified in run time (entries added or removed), so shadow tables are requires.
++     Otherwise, the only supported runtime modification is a specific next engine update
++     and this requires shadow memory of a single AD */
++
++    /* Shadow size should be enough to hold the following 3 structures:
++     * 1 - an action descriptor */
++    shadowSize = FM_PCD_CC_AD_ENTRY_SIZE;
++
++    /* 2 - keys match table, if was allocated for the current node */
++    if (isKeyTblAlloc)
++        shadowSize += *p_MatchTableSize;
++
++    /* 3 - next action descriptors table */
++    shadowSize += *p_AdTableSize;
++
++    /* Update shadow to the calculated size */
++    err = FmPcdUpdateCcShadow(p_CcNode->h_FmPcd, (uint32_t)shadowSize,
++                              FM_PCD_CC_AD_TABLE_ALIGN);
++    if (err != E_OK)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for CC node shadow"));
++    }
++
++    return E_OK;
++}
++
++static t_Error AllocStatsObjs(t_FmPcdCcNode *p_CcNode)
++{
++    t_FmPcdStatsObj *p_StatsObj;
++    t_Handle h_FmMuram, h_StatsAd, h_StatsCounters;
++    uint32_t i;
++
++    h_FmMuram = FmPcdGetMuramHandle(p_CcNode->h_FmPcd);
++    if (!h_FmMuram)
++        RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM MURAM"));
++
++    /* Allocate statistics ADs and statistics counter. An extra pair (AD + counters)
++     will be allocated to support runtime modifications */
++    for (i = 0; i < p_CcNode->maxNumOfKeys + 2; i++)
++    {
++        /* Allocate list object structure */
++        p_StatsObj = XX_Malloc(sizeof(t_FmPcdStatsObj));
++        if (!p_StatsObj)
++        {
++            FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram);
++            RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Statistics object"));
++        }
++        memset(p_StatsObj, 0, sizeof(t_FmPcdStatsObj));
++
++        /* Allocate statistics AD from MURAM */
++        h_StatsAd = (t_Handle)FM_MURAM_AllocMem(h_FmMuram,
++                                                FM_PCD_CC_AD_ENTRY_SIZE,
++                                                FM_PCD_CC_AD_TABLE_ALIGN);
++        if (!h_StatsAd)
++        {
++            FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram);
++            XX_Free(p_StatsObj);
++            RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                         ("MURAM allocation for statistics ADs"));
++        }
++        IOMemSet32(h_StatsAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
++
++        /* Allocate statistics counters from MURAM */
++        h_StatsCounters = (t_Handle)FM_MURAM_AllocMem(
++                h_FmMuram, p_CcNode->countersArraySize,
++                FM_PCD_CC_AD_TABLE_ALIGN);
++        if (!h_StatsCounters)
++        {
++            FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram);
++            FM_MURAM_FreeMem(h_FmMuram, h_StatsAd);
++            XX_Free(p_StatsObj);
++            RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                         ("MURAM allocation for statistics counters"));
++        }
++        IOMemSet32(h_StatsCounters, 0, p_CcNode->countersArraySize);
++
++        p_StatsObj->h_StatsAd = h_StatsAd;
++        p_StatsObj->h_StatsCounters = h_StatsCounters;
++
++        EnqueueStatsObj(&p_CcNode->availableStatsLst, p_StatsObj);
++    }
++
++    return E_OK;
++}
++
++static t_Error MatchTableGetKeyStatistics(
++        t_FmPcdCcNode *p_CcNode, uint16_t keyIndex,
++        t_FmPcdCcKeyStatistics *p_KeyStatistics)
++{
++    uint32_t *p_StatsCounters, i;
++
++    if (p_CcNode->statisticsMode == e_FM_PCD_CC_STATS_MODE_NONE)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                     ("Statistics were not enabled for this match table"));
++
++    if (!p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                     ("Statistics were not enabled for this key"));
++
++    memset(p_KeyStatistics, 0, sizeof(t_FmPcdCcKeyStatistics));
++
++    p_StatsCounters =
++            p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsCounters;
++    ASSERT_COND(p_StatsCounters);
++
++    p_KeyStatistics->byteCount = GET_UINT32(*p_StatsCounters);
++
++    for (i = 1; i <= p_CcNode->numOfStatsFLRs; i++)
++    {
++        p_StatsCounters =
++                PTR_MOVE(p_StatsCounters, FM_PCD_CC_STATS_COUNTER_SIZE);
++
++        p_KeyStatistics->frameCount += GET_UINT32(*p_StatsCounters);
++
++#if (DPAA_VERSION >= 11)
++        p_KeyStatistics->frameLengthRangeCount[i - 1] =
++                GET_UINT32(*p_StatsCounters);
++#endif /* (DPAA_VERSION >= 11) */
++    }
++
++    return E_OK;
++}
++
++static t_Error MatchTableSet(t_Handle h_FmPcd, t_FmPcdCcNode *p_CcNode,
++                             t_FmPcdCcNodeParams *p_CcNodeParam)
++{
++    t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
++    t_FmPcdCcNode *p_FmPcdCcNextNode;
++    t_Error err = E_OK;
++    uint32_t tmp, keySize;
++    bool glblMask = FALSE;
++    t_FmPcdCcKeyParams *p_KeyParams;
++    t_Handle h_FmMuram, p_KeysMatchTblTmp, p_AdTableTmp;
++#if (DPAA_VERSION >= 11)
++    t_Handle h_StatsFLRs;
++#endif /* (DPAA_VERSION >= 11) */
++    bool fullField = FALSE;
++    ccPrivateInfo_t icCode = CC_PRIVATE_INFO_NONE;
++    bool isKeyTblAlloc, fromIc = FALSE;
++    uint32_t matchTableSize, adTableSize;
++    t_CcNodeInformation ccNodeInfo, *p_CcInformation;
++    t_FmPcdStatsObj *p_StatsObj;
++    t_FmPcdCcStatsParams statsParams = { 0 };
++    t_Handle h_Manip;
++
++    ASSERT_COND(h_FmPcd);
++    ASSERT_COND(p_CcNode);
++    ASSERT_COND(p_CcNodeParam);
++
++    p_CcNode->p_GlblMask = (t_Handle)XX_Malloc(
++            CC_GLBL_MASK_SIZE * sizeof(uint8_t));
++    memset(p_CcNode->p_GlblMask, 0, CC_GLBL_MASK_SIZE * sizeof(uint8_t));
++
++    p_CcNode->h_FmPcd = h_FmPcd;
++    p_CcNode->numOfKeys = p_CcNodeParam->keysParams.numOfKeys;
++    p_CcNode->maxNumOfKeys = p_CcNodeParam->keysParams.maxNumOfKeys;
++    p_CcNode->maskSupport = p_CcNodeParam->keysParams.maskSupport;
++    p_CcNode->statisticsMode = p_CcNodeParam->keysParams.statisticsMode;
++
++    /* For backward compatibility - even if statistics mode is nullified,
++     we'll fix it to frame mode so we can support per-key request for
++     statistics using 'statisticsEn' in next engine parameters */
++    if (!p_CcNode->maxNumOfKeys
++            && (p_CcNode->statisticsMode == e_FM_PCD_CC_STATS_MODE_NONE))
++        p_CcNode->statisticsMode = e_FM_PCD_CC_STATS_MODE_FRAME;
++
++    h_FmMuram = FmPcdGetMuramHandle(h_FmPcd);
++    if (!h_FmMuram)
++        RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM MURAM"));
++
++    INIT_LIST(&p_CcNode->ccPrevNodesLst);
++    INIT_LIST(&p_CcNode->ccTreeIdLst);
++    INIT_LIST(&p_CcNode->ccTreesLst);
++    INIT_LIST(&p_CcNode->availableStatsLst);
++
++    p_CcNode->h_Spinlock = XX_InitSpinlock();
++    if (!p_CcNode->h_Spinlock)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY, ("CC node spinlock"));
++    }
++
++    if ((p_CcNodeParam->extractCcParams.type == e_FM_PCD_EXTRACT_BY_HDR)
++            && ((p_CcNodeParam->extractCcParams.extractByHdr.hdr
++                    == HEADER_TYPE_IPv4)
++                    || (p_CcNodeParam->extractCcParams.extractByHdr.hdr
++                            == HEADER_TYPE_IPv6))
++            && (p_CcNodeParam->extractCcParams.extractByHdr.type
++                    == e_FM_PCD_EXTRACT_FULL_FIELD)
++            && ((p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField.ipv6
++                    == NET_HEADER_FIELD_IPv6_HOP_LIMIT)
++                    || (p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField.ipv4
++                            == NET_HEADER_FIELD_IPv4_TTL)))
++    {
++        err = Ipv4TtlOrIpv6HopLimitCheckParams(h_FmPcd, p_CcNodeParam, p_CcNode,
++                                               &isKeyTblAlloc);
++        glblMask = FALSE;
++    }
++    else
++        if ((p_CcNodeParam->extractCcParams.type == e_FM_PCD_EXTRACT_NON_HDR)
++                && ((p_CcNodeParam->extractCcParams.extractNonHdr.src
++                        == e_FM_PCD_EXTRACT_FROM_KEY)
++                        || (p_CcNodeParam->extractCcParams.extractNonHdr.src
++                                == e_FM_PCD_EXTRACT_FROM_HASH)
++                        || (p_CcNodeParam->extractCcParams.extractNonHdr.src
++                                == e_FM_PCD_EXTRACT_FROM_FLOW_ID)))
++        {
++            if ((p_CcNodeParam->extractCcParams.extractNonHdr.src
++                    == e_FM_PCD_EXTRACT_FROM_FLOW_ID)
++                    && (p_CcNodeParam->extractCcParams.extractNonHdr.offset != 0))
++            {
++                DeleteNode(p_CcNode);
++                RETURN_ERROR(
++                        MAJOR,
++                        E_INVALID_VALUE,
++                        ("In the case of the extraction from e_FM_PCD_EXTRACT_FROM_FLOW_ID offset has to be 0"));
++            }
++
++            icCode = IcDefineCode(p_CcNodeParam);
++            fromIc = TRUE;
++            if (icCode == CC_PRIVATE_INFO_NONE)
++            {
++                DeleteNode(p_CcNode);
++                RETURN_ERROR(
++                        MAJOR,
++                        E_INVALID_STATE,
++                        ("user asked extraction from IC and field in internal context or action wasn't initialized in the right way"));
++            }
++
++            if ((icCode == CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP)
++                    || (icCode == CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP))
++            {
++                err = IcHashIndexedCheckParams(h_FmPcd, p_CcNodeParam, p_CcNode,
++                                               &isKeyTblAlloc);
++                glblMask = TRUE;
++            }
++            else
++            {
++                err = CheckParams(h_FmPcd, p_CcNodeParam, p_CcNode,
++                                  &isKeyTblAlloc);
++                if (p_CcNode->glblMaskSize)
++                    glblMask = TRUE;
++            }
++        }
++        else
++        {
++            err = CheckParams(h_FmPcd, p_CcNodeParam, p_CcNode, &isKeyTblAlloc);
++            if (p_CcNode->glblMaskSize)
++                glblMask = TRUE;
++        }
++
++    if (err)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    switch (p_CcNodeParam->extractCcParams.type)
++    {
++        case (e_FM_PCD_EXTRACT_BY_HDR):
++            switch (p_CcNodeParam->extractCcParams.extractByHdr.type)
++            {
++                case (e_FM_PCD_EXTRACT_FULL_FIELD):
++                    p_CcNode->parseCode =
++                            GetFullFieldParseCode(
++                                    p_CcNodeParam->extractCcParams.extractByHdr.hdr,
++                                    p_CcNodeParam->extractCcParams.extractByHdr.hdrIndex,
++                                    p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField);
++                    GetSizeHeaderField(
++                            p_CcNodeParam->extractCcParams.extractByHdr.hdr,
++                            p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField,
++                            &p_CcNode->sizeOfExtraction);
++                    fullField = TRUE;
++                    if ((p_CcNode->parseCode != CC_PC_FF_TCI1)
++                            && (p_CcNode->parseCode != CC_PC_FF_TCI2)
++                            && (p_CcNode->parseCode != CC_PC_FF_MPLS1)
++                            && (p_CcNode->parseCode != CC_PC_FF_MPLS_LAST)
++                            && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC1)
++                            && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC2)
++                            && (p_CcNode->parseCode
++                                    != CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1)
++                            && (p_CcNode->parseCode != CC_PC_FF_IPDSCP)
++                            && (p_CcNode->parseCode
++                                    != CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2)
++                            && glblMask)
++                    {
++                        glblMask = FALSE;
++                        p_CcNode->glblMaskSize = 4;
++                        p_CcNode->lclMask = TRUE;
++                    }
++                    break;
++
++                case (e_FM_PCD_EXTRACT_FROM_HDR):
++                    p_CcNode->sizeOfExtraction =
++                            p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromHdr.size;
++                    p_CcNode->offset =
++                            p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromHdr.offset;
++                    p_CcNode->userOffset =
++                            p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromHdr.offset;
++                    p_CcNode->parseCode =
++                            GetPrParseCode(
++                                    p_CcNodeParam->extractCcParams.extractByHdr.hdr,
++                                    p_CcNodeParam->extractCcParams.extractByHdr.hdrIndex,
++                                    p_CcNode->offset, glblMask,
++                                    &p_CcNode->prsArrayOffset);
++                    break;
++
++                case (e_FM_PCD_EXTRACT_FROM_FIELD):
++                    p_CcNode->offset =
++                            p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.offset;
++                    p_CcNode->userOffset =
++                            p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.offset;
++                    p_CcNode->sizeOfExtraction =
++                            p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.size;
++                    p_CcNode->parseCode =
++                            GetFieldParseCode(
++                                    p_CcNodeParam->extractCcParams.extractByHdr.hdr,
++                                    p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.field,
++                                    p_CcNode->offset,
++                                    &p_CcNode->prsArrayOffset,
++                                    p_CcNodeParam->extractCcParams.extractByHdr.hdrIndex);
++                    break;
++
++                default:
++                    DeleteNode(p_CcNode);
++                    RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG);
++            }
++            break;
++
++        case (e_FM_PCD_EXTRACT_NON_HDR):
++            /* get the field code for the generic extract */
++            p_CcNode->sizeOfExtraction =
++                    p_CcNodeParam->extractCcParams.extractNonHdr.size;
++            p_CcNode->offset =
++                    p_CcNodeParam->extractCcParams.extractNonHdr.offset;
++            p_CcNode->userOffset =
++                    p_CcNodeParam->extractCcParams.extractNonHdr.offset;
++            p_CcNode->parseCode = GetGenParseCode(
++                    p_CcNodeParam->extractCcParams.extractNonHdr.src,
++                    p_CcNode->offset, glblMask, &p_CcNode->prsArrayOffset,
++                    fromIc, icCode);
++
++            if (p_CcNode->parseCode == CC_PC_GENERIC_IC_HASH_INDEXED)
++            {
++                if ((p_CcNode->offset + p_CcNode->sizeOfExtraction) > 8)
++                {
++                    DeleteNode(p_CcNode);
++                    RETURN_ERROR(
++                            MAJOR,
++                            E_INVALID_SELECTION,
++                            ("when node of the type CC_PC_GENERIC_IC_HASH_INDEXED offset + size can not be bigger then size of HASH 64 bits (8 bytes)"));
++                }
++            }
++            if ((p_CcNode->parseCode == CC_PC_GENERIC_IC_GMASK)
++                    || (p_CcNode->parseCode == CC_PC_GENERIC_IC_HASH_INDEXED))
++            {
++                p_CcNode->offset += p_CcNode->prsArrayOffset;
++                p_CcNode->prsArrayOffset = 0;
++            }
++            break;
++
++        default:
++            DeleteNode(p_CcNode);
++            RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG);
++    }
++
++    if (p_CcNode->parseCode == CC_PC_ILLEGAL)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("illegal extraction type"));
++    }
++
++    if ((p_CcNode->sizeOfExtraction > FM_PCD_MAX_SIZE_OF_KEY)
++            || !p_CcNode->sizeOfExtraction)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE,
++                     ("sizeOfExatrction can not be greater than 56 and not 0"));
++    }
++
++    if (p_CcNodeParam->keysParams.keySize != p_CcNode->sizeOfExtraction)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE,
++                     ("keySize has to be equal to sizeOfExtraction"));
++    }
++
++    p_CcNode->userSizeOfExtraction = p_CcNode->sizeOfExtraction;
++
++    if (!glblMask)
++        memset(p_CcNode->p_GlblMask, 0xff, CC_GLBL_MASK_SIZE * sizeof(uint8_t));
++
++    err = CheckAndSetManipParamsWithCcNodeParams(p_CcNode);
++    if (err != E_OK)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE,
++                     ("keySize has to be equal to sizeOfExtraction"));
++    }
++
++    /* Calculating matching table entry size by rounding up the user-defined size of extraction to valid entry size */
++    GetCcExtractKeySize(p_CcNode->sizeOfExtraction,
++                        &p_CcNode->ccKeySizeAccExtraction);
++
++    /* If local mask is used, it is stored next to each key in the keys match table */
++    if (p_CcNode->lclMask)
++        keySize = (uint32_t)(2 * p_CcNode->ccKeySizeAccExtraction);
++    else
++        keySize = p_CcNode->ccKeySizeAccExtraction;
++
++    /* Update CC shadow with maximal size required by this node */
++    if (p_CcNode->maxNumOfKeys)
++    {
++        err = CalcAndUpdateCcShadow(p_CcNode, isKeyTblAlloc, &matchTableSize,
++                                    &adTableSize);
++        if (err != E_OK)
++        {
++            DeleteNode(p_CcNode);
++            RETURN_ERROR(MAJOR, err, NO_MSG);
++        }
++
++        p_CcNode->keysMatchTableMaxSize = matchTableSize;
++
++        if (p_CcNode->statisticsMode != e_FM_PCD_CC_STATS_MODE_NONE)
++        {
++            err = AllocStatsObjs(p_CcNode);
++            if (err != E_OK)
++            {
++                DeleteNode(p_CcNode);
++                RETURN_ERROR(MAJOR, err, NO_MSG);
++            }
++        }
++
++        /* If manipulation will be initialized before this node, it will use the table
++         descriptor in the AD table of previous node and this node will need an extra
++         AD as his table descriptor. */
++        p_CcNode->h_TmpAd = (t_Handle)FM_MURAM_AllocMem(
++                h_FmMuram, FM_PCD_CC_AD_ENTRY_SIZE, FM_PCD_CC_AD_TABLE_ALIGN);
++        if (!p_CcNode->h_TmpAd)
++        {
++            DeleteNode(p_CcNode);
++            RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                         ("MURAM allocation for CC action descriptor"));
++        }
++    }
++    else
++    {
++        matchTableSize = (uint32_t)(keySize * sizeof(uint8_t)
++                * (p_CcNode->numOfKeys + 1));
++        adTableSize = (uint32_t)(FM_PCD_CC_AD_ENTRY_SIZE
++                * (p_CcNode->numOfKeys + 1));
++    }
++
++#if (DPAA_VERSION >= 11)
++    switch (p_CcNode->statisticsMode)
++    {
++
++        case e_FM_PCD_CC_STATS_MODE_RMON:
++            /* If RMON statistics or RMON conditional statistics modes are requested,
++             allocate frame length ranges array */
++            p_CcNode->h_StatsFLRs = FM_MURAM_AllocMem(
++                    h_FmMuram,
++                    (uint32_t)(p_CcNode->numOfStatsFLRs)
++                            * FM_PCD_CC_STATS_FLR_SIZE,
++                    FM_PCD_CC_AD_TABLE_ALIGN);
++
++            if (!p_CcNode->h_StatsFLRs)
++            {
++                DeleteNode(p_CcNode);
++                RETURN_ERROR(
++                        MAJOR, E_NO_MEMORY,
++                        ("MURAM allocation for CC frame length ranges array"));
++            }
++
++            /* Initialize using value received from the user */
++            for (tmp = 0; tmp < p_CcNode->numOfStatsFLRs; tmp++)
++            {
++                h_StatsFLRs =
++                        PTR_MOVE(p_CcNode->h_StatsFLRs, tmp * FM_PCD_CC_STATS_FLR_SIZE);
++
++                Mem2IOCpy32(h_StatsFLRs,
++                            &(p_CcNodeParam->keysParams.frameLengthRanges[tmp]),
++                            FM_PCD_CC_STATS_FLR_SIZE);
++            }
++            break;
++
++        default:
++            break;
++    }
++#endif /* (DPAA_VERSION >= 11) */
++
++    /* Allocate keys match table. Not required for some CC nodes, for example for IPv4 TTL
++     identification, IPv6 hop count identification, etc. */
++    if (isKeyTblAlloc)
++    {
++        p_CcNode->h_KeysMatchTable = (t_Handle)FM_MURAM_AllocMem(
++                h_FmMuram, matchTableSize, FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN);
++        if (!p_CcNode->h_KeysMatchTable)
++        {
++            DeleteNode(p_CcNode);
++            RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                         ("MURAM allocation for CC node key match table"));
++        }
++        IOMemSet32((uint8_t *)p_CcNode->h_KeysMatchTable, 0, matchTableSize);
++    }
++
++    /* Allocate action descriptors table */
++    p_CcNode->h_AdTable = (t_Handle)FM_MURAM_AllocMem(h_FmMuram, adTableSize,
++                                                      FM_PCD_CC_AD_TABLE_ALIGN);
++    if (!p_CcNode->h_AdTable)
++    {
++        DeleteNode(p_CcNode);
++        RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                     ("MURAM allocation for CC node action descriptors table"));
++    }
++    IOMemSet32((uint8_t *)p_CcNode->h_AdTable, 0, adTableSize);
++
++    p_KeysMatchTblTmp = p_CcNode->h_KeysMatchTable;
++    p_AdTableTmp = p_CcNode->h_AdTable;
++
++    /* For each key, create the key and the next step AD */
++    for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++)
++    {
++        p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp];
++
++        if (p_KeysMatchTblTmp)
++        {
++            /* Copy the key */
++            Mem2IOCpy32((void*)p_KeysMatchTblTmp, p_KeyParams->p_Key,
++                        p_CcNode->sizeOfExtraction);
++
++            /* Copy the key mask or initialize it to 0xFF..F */
++            if (p_CcNode->lclMask && p_KeyParams->p_Mask)
++            {
++                Mem2IOCpy32(PTR_MOVE(p_KeysMatchTblTmp,
++                        p_CcNode->ccKeySizeAccExtraction), /* User's size of extraction rounded up to a valid matching table entry size */
++                            p_KeyParams->p_Mask, p_CcNode->sizeOfExtraction); /* Exact size of extraction as received from the user */
++            }
++            else
++                if (p_CcNode->lclMask)
++                {
++                    IOMemSet32(PTR_MOVE(p_KeysMatchTblTmp,
++                            p_CcNode->ccKeySizeAccExtraction), /* User's size of extraction rounded up to a valid matching table entry size */
++                               0xff, p_CcNode->sizeOfExtraction); /* Exact size of extraction as received from the user */
++                }
++
++            p_KeysMatchTblTmp =
++                    PTR_MOVE(p_KeysMatchTblTmp, keySize * sizeof(uint8_t));
++        }
++
++        /* Create the next action descriptor in the match table */
++        if (p_KeyParams->ccNextEngineParams.statisticsEn)
++        {
++            p_StatsObj = GetStatsObj(p_CcNode);
++            ASSERT_COND(p_StatsObj);
++
++            statsParams.h_StatsAd = p_StatsObj->h_StatsAd;
++            statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters;
++#if (DPAA_VERSION >= 11)
++            statsParams.h_StatsFLRs = p_CcNode->h_StatsFLRs;
++
++#endif /* (DPAA_VERSION >= 11) */
++            NextStepAd(p_AdTableTmp, &statsParams,
++                       &p_KeyParams->ccNextEngineParams, p_FmPcd);
++
++            p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = p_StatsObj;
++        }
++        else
++        {
++            NextStepAd(p_AdTableTmp, NULL, &p_KeyParams->ccNextEngineParams,
++                       p_FmPcd);
++
++            p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = NULL;
++        }
++
++        p_AdTableTmp = PTR_MOVE(p_AdTableTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++    }
++
++    /* Update next engine for the 'miss' entry */
++    if (p_CcNodeParam->keysParams.ccNextEngineParamsForMiss.statisticsEn)
++    {
++        p_StatsObj = GetStatsObj(p_CcNode);
++        ASSERT_COND(p_StatsObj);
++
++        /* All 'bucket' nodes of a hash table should share the same statistics counters,
++         allocated by the hash table. So, if this node is a bucket of a hash table,
++         we'll replace the locally allocated counters with the shared counters. */
++        if (p_CcNode->isHashBucket)
++        {
++            ASSERT_COND(p_CcNode->h_MissStatsCounters);
++
++            /* Store original counters pointer and replace it with mutual preallocated pointer */
++            p_CcNode->h_PrivMissStatsCounters = p_StatsObj->h_StatsCounters;
++            p_StatsObj->h_StatsCounters = p_CcNode->h_MissStatsCounters;
++        }
++
++        statsParams.h_StatsAd = p_StatsObj->h_StatsAd;
++        statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters;
++#if (DPAA_VERSION >= 11)
++        statsParams.h_StatsFLRs = p_CcNode->h_StatsFLRs;
++
++#endif /* (DPAA_VERSION >= 11) */
++
++        NextStepAd(p_AdTableTmp, &statsParams,
++                   &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++                   p_FmPcd);
++
++        p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = p_StatsObj;
++    }
++    else
++    {
++        NextStepAd(p_AdTableTmp, NULL,
++                   &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss,
++                   p_FmPcd);
++
++        p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = NULL;
++    }
++
++    /* This parameter will be used to initialize the "key length" field in the action descriptor
++     that points to this node and it should be 0 for full field extraction */
++    if (fullField == TRUE)
++        p_CcNode->sizeOfExtraction = 0;
++
++    for (tmp = 0; tmp < MIN(p_CcNode->numOfKeys + 1, CC_MAX_NUM_OF_KEYS); tmp++)
++    {
++        if (p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine
++                == e_FM_PCD_CC)
++        {
++            p_FmPcdCcNextNode =
++                    (t_FmPcdCcNode*)p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode;
++            p_CcInformation = FindNodeInfoInReleventLst(
++                    &p_FmPcdCcNextNode->ccPrevNodesLst, (t_Handle)p_CcNode,
++                    p_FmPcdCcNextNode->h_Spinlock);
++            if (!p_CcInformation)
++            {
++                memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++                ccNodeInfo.h_CcNode = (t_Handle)p_CcNode;
++                ccNodeInfo.index = 1;
++                EnqueueNodeInfoToRelevantLst(&p_FmPcdCcNextNode->ccPrevNodesLst,
++                                             &ccNodeInfo,
++                                             p_FmPcdCcNextNode->h_Spinlock);
++            }
++            else
++                p_CcInformation->index++;
++
++            if (p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip)
++            {
++                h_Manip =
++                        p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip;
++                p_CcInformation = FindNodeInfoInReleventLst(
++                        FmPcdManipGetNodeLstPointedOnThisManip(h_Manip),
++                        (t_Handle)p_CcNode, FmPcdManipGetSpinlock(h_Manip));
++                if (!p_CcInformation)
++                {
++                    memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++                    ccNodeInfo.h_CcNode = (t_Handle)p_CcNode;
++                    ccNodeInfo.index = 1;
++                    EnqueueNodeInfoToRelevantLst(
++                            FmPcdManipGetNodeLstPointedOnThisManip(h_Manip),
++                            &ccNodeInfo, FmPcdManipGetSpinlock(h_Manip));
++                }
++                else
++                    p_CcInformation->index++;
++            }
++        }
++    }
++
++    p_AdTableTmp = p_CcNode->h_AdTable;
++
++    if (!FmPcdLockTryLockAll(h_FmPcd))
++    {
++        FM_PCD_MatchTableDelete((t_Handle)p_CcNode);
++        DBG(TRACE, ("FmPcdLockTryLockAll failed"));
++        return ERROR_CODE(E_BUSY);
++    }
++
++    /* Required action for each next engine */
++    for (tmp = 0; tmp < MIN(p_CcNode->numOfKeys + 1, CC_MAX_NUM_OF_KEYS); tmp++)
++    {
++        if (p_CcNode->keyAndNextEngineParams[tmp].requiredAction)
++        {
++            err = SetRequiredAction(
++                    h_FmPcd,
++                    p_CcNode->keyAndNextEngineParams[tmp].requiredAction,
++                    &p_CcNode->keyAndNextEngineParams[tmp], p_AdTableTmp, 1,
++                    NULL);
++            if (err)
++            {
++                FmPcdLockUnlockAll(h_FmPcd);
++                FM_PCD_MatchTableDelete((t_Handle)p_CcNode);
++                RETURN_ERROR(MAJOR, err, NO_MSG);
++            }
++            p_AdTableTmp = PTR_MOVE(p_AdTableTmp, FM_PCD_CC_AD_ENTRY_SIZE);
++        }
++    }
++
++    FmPcdLockUnlockAll(h_FmPcd);
++
++    return E_OK;
++}
++/************************** End of static functions **************************/
++
++/*****************************************************************************/
++/*              Inter-module API routines                                    */
++/*****************************************************************************/
++
++t_CcNodeInformation* FindNodeInfoInReleventLst(t_List *p_List, t_Handle h_Info,
++                                               t_Handle h_Spinlock)
++{
++    t_CcNodeInformation *p_CcInformation;
++    t_List *p_Pos;
++    uint32_t intFlags;
++
++    intFlags = XX_LockIntrSpinlock(h_Spinlock);
++
++    for (p_Pos = LIST_FIRST(p_List); p_Pos != (p_List);
++            p_Pos = LIST_NEXT(p_Pos))
++    {
++        p_CcInformation = CC_NODE_F_OBJECT(p_Pos);
++
++        ASSERT_COND(p_CcInformation->h_CcNode);
++
++        if (p_CcInformation->h_CcNode == h_Info)
++        {
++            XX_UnlockIntrSpinlock(h_Spinlock, intFlags);
++            return p_CcInformation;
++        }
++    }
++
++    XX_UnlockIntrSpinlock(h_Spinlock, intFlags);
++
++    return NULL;
++}
++
++void EnqueueNodeInfoToRelevantLst(t_List *p_List, t_CcNodeInformation *p_CcInfo,
++                                  t_Handle h_Spinlock)
++{
++    t_CcNodeInformation *p_CcInformation;
++    uint32_t intFlags = 0;
++
++    p_CcInformation = (t_CcNodeInformation *)XX_Malloc(
++            sizeof(t_CcNodeInformation));
++
++    if (p_CcInformation)
++    {
++        memset(p_CcInformation, 0, sizeof(t_CcNodeInformation));
++        memcpy(p_CcInformation, p_CcInfo, sizeof(t_CcNodeInformation));
++        INIT_LIST(&p_CcInformation->node);
++
++        if (h_Spinlock)
++            intFlags = XX_LockIntrSpinlock(h_Spinlock);
++
++        LIST_AddToTail(&p_CcInformation->node, p_List);
++
++        if (h_Spinlock)
++            XX_UnlockIntrSpinlock(h_Spinlock, intFlags);
++    }
++    else
++        REPORT_ERROR(MAJOR, E_NO_MEMORY, ("CC Node Information"));
++}
++
++void DequeueNodeInfoFromRelevantLst(t_List *p_List, t_Handle h_Info,
++                                    t_Handle h_Spinlock)
++{
++    t_CcNodeInformation *p_CcInformation = NULL;
++    uint32_t intFlags = 0;
++    t_List *p_Pos;
++
++    if (h_Spinlock)
++        intFlags = XX_LockIntrSpinlock(h_Spinlock);
++
++    if (LIST_IsEmpty(p_List))
++    {
++        XX_RestoreAllIntr(intFlags);
++        return;
++    }
++
++    for (p_Pos = LIST_FIRST(p_List); p_Pos != (p_List);
++            p_Pos = LIST_NEXT(p_Pos))
++    {
++        p_CcInformation = CC_NODE_F_OBJECT(p_Pos);
++        ASSERT_COND(p_CcInformation);
++        ASSERT_COND(p_CcInformation->h_CcNode);
++        if (p_CcInformation->h_CcNode == h_Info)
++            break;
++    }
++
++    if (p_CcInformation)
++    {
++        LIST_DelAndInit(&p_CcInformation->node);
++        XX_Free(p_CcInformation);
++    }
++
++    if (h_Spinlock)
++        XX_UnlockIntrSpinlock(h_Spinlock, intFlags);
++}
++
++void NextStepAd(t_Handle h_Ad, t_FmPcdCcStatsParams *p_FmPcdCcStatsParams,
++                t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams,
++                t_FmPcd *p_FmPcd)
++{
++    switch (p_FmPcdCcNextEngineParams->nextEngine)
++    {
++        case (e_FM_PCD_KG):
++        case (e_FM_PCD_PLCR):
++        case (e_FM_PCD_DONE):
++            /* if NIA is not CC, create a "result" type AD */
++            FillAdOfTypeResult(h_Ad, p_FmPcdCcStatsParams, p_FmPcd,
++                               p_FmPcdCcNextEngineParams);
++            break;
++#if (DPAA_VERSION >= 11)
++        case (e_FM_PCD_FR):
++            if (p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic)
++            {
++                FillAdOfTypeContLookup(
++                        h_Ad, p_FmPcdCcStatsParams, p_FmPcd,
++                        p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode,
++                        p_FmPcdCcNextEngineParams->h_Manip,
++                        p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic);
++                FrmReplicGroupUpdateOwner(
++                        p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic,
++                        TRUE/* add */);
++            }
++            break;
++#endif /* (DPAA_VERSION >= 11) */
++
++        case (e_FM_PCD_CC):
++            /* if NIA is not CC, create a TD to continue the CC lookup */
++            FillAdOfTypeContLookup(
++                    h_Ad, p_FmPcdCcStatsParams, p_FmPcd,
++                    p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode,
++                    p_FmPcdCcNextEngineParams->h_Manip, NULL);
++
++            UpdateNodeOwner(p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode,
++                            TRUE);
++            break;
++
++        default:
++            return;
++    }
++}
++
++t_Error FmPcdCcTreeAddIPR(t_Handle h_FmPcd, t_Handle h_FmTree,
++                          t_Handle h_NetEnv, t_Handle h_IpReassemblyManip,
++                          bool createSchemes)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree;
++    t_FmPcdCcNextEngineParams nextEngineParams;
++    t_NetEnvParams netEnvParams;
++    t_Handle h_Ad;
++    bool isIpv6Present;
++    uint8_t ipv4GroupId, ipv6GroupId;
++    t_Error err;
++
++    ASSERT_COND(p_FmPcdCcTree);
++
++    /* this routine must be protected by the calling routine! */
++
++    memset(&nextEngineParams, 0, sizeof(t_FmPcdCcNextEngineParams));
++    memset(&netEnvParams, 0, sizeof(t_NetEnvParams));
++
++    h_Ad = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr);
++
++    isIpv6Present = FmPcdManipIpReassmIsIpv6Hdr(h_IpReassemblyManip);
++
++    if (isIpv6Present
++            && (p_FmPcdCcTree->numOfEntries > (FM_PCD_MAX_NUM_OF_CC_GROUPS - 2)))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("need two free entries for IPR"));
++
++    if (p_FmPcdCcTree->numOfEntries > (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("need two free entries for IPR"));
++
++    nextEngineParams.nextEngine = e_FM_PCD_DONE;
++    nextEngineParams.h_Manip = h_IpReassemblyManip;
++
++    /* Lock tree */
++    err = CcRootTryLock(p_FmPcdCcTree);
++    if (err)
++        return ERROR_CODE(E_BUSY);
++
++    if (p_FmPcdCcTree->h_IpReassemblyManip == h_IpReassemblyManip)
++    {
++        CcRootReleaseLock(p_FmPcdCcTree);
++        return E_OK;
++    }
++
++    if ((p_FmPcdCcTree->h_IpReassemblyManip)
++            && (p_FmPcdCcTree->h_IpReassemblyManip != h_IpReassemblyManip))
++    {
++        CcRootReleaseLock(p_FmPcdCcTree);
++        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                     ("This tree was previously updated with different IPR"));
++    }
++
++    /* Initialize IPR for the first time for this tree */
++    if (isIpv6Present)
++    {
++        ipv6GroupId = p_FmPcdCcTree->numOfGrps++;
++        p_FmPcdCcTree->fmPcdGroupParam[ipv6GroupId].baseGroupEntry =
++                (FM_PCD_MAX_NUM_OF_CC_GROUPS - 2);
++
++        if (createSchemes)
++        {
++            err = FmPcdManipBuildIpReassmScheme(h_FmPcd, h_NetEnv,
++                                                p_FmPcdCcTree,
++                                                h_IpReassemblyManip, FALSE,
++                                                ipv6GroupId);
++            if (err)
++            {
++                p_FmPcdCcTree->numOfGrps--;
++                CcRootReleaseLock(p_FmPcdCcTree);
++                RETURN_ERROR(MAJOR, err, NO_MSG);
++            }
++        }
++
++        NextStepAd(
++                PTR_MOVE(h_Ad, (FM_PCD_MAX_NUM_OF_CC_GROUPS-2) * FM_PCD_CC_AD_ENTRY_SIZE),
++                NULL, &nextEngineParams, h_FmPcd);
++    }
++
++    ipv4GroupId = p_FmPcdCcTree->numOfGrps++;
++    p_FmPcdCcTree->fmPcdGroupParam[ipv4GroupId].totalBitsMask = 0;
++    p_FmPcdCcTree->fmPcdGroupParam[ipv4GroupId].baseGroupEntry =
++            (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1);
++
++    if (createSchemes)
++    {
++        err = FmPcdManipBuildIpReassmScheme(h_FmPcd, h_NetEnv, p_FmPcdCcTree,
++                                            h_IpReassemblyManip, TRUE,
++                                            ipv4GroupId);
++        if (err)
++        {
++            p_FmPcdCcTree->numOfGrps--;
++            if (isIpv6Present)
++            {
++                p_FmPcdCcTree->numOfGrps--;
++                FmPcdManipDeleteIpReassmSchemes(h_IpReassemblyManip);
++            }
++            CcRootReleaseLock(p_FmPcdCcTree);
++            RETURN_ERROR(MAJOR, err, NO_MSG);
++        }
++    }
++
++    NextStepAd(
++            PTR_MOVE(h_Ad, (FM_PCD_MAX_NUM_OF_CC_GROUPS-1) * FM_PCD_CC_AD_ENTRY_SIZE),
++            NULL, &nextEngineParams, h_FmPcd);
++
++    p_FmPcdCcTree->h_IpReassemblyManip = h_IpReassemblyManip;
++
++    CcRootReleaseLock(p_FmPcdCcTree);
++
++    return E_OK;
++}
++
++t_Error FmPcdCcTreeAddCPR(t_Handle h_FmPcd, t_Handle h_FmTree,
++                          t_Handle h_NetEnv, t_Handle h_ReassemblyManip,
++                          bool createSchemes)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree;
++    t_FmPcdCcNextEngineParams nextEngineParams;
++    t_NetEnvParams netEnvParams;
++    t_Handle h_Ad;
++    uint8_t groupId;
++    t_Error err;
++
++    ASSERT_COND(p_FmPcdCcTree);
++
++    /* this routine must be protected by the calling routine! */
++    memset(&nextEngineParams, 0, sizeof(t_FmPcdCcNextEngineParams));
++    memset(&netEnvParams, 0, sizeof(t_NetEnvParams));
++
++    h_Ad = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr);
++
++    if (p_FmPcdCcTree->numOfEntries > (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("need one free entries for CPR"));
++
++    nextEngineParams.nextEngine = e_FM_PCD_DONE;
++    nextEngineParams.h_Manip = h_ReassemblyManip;
++
++    /* Lock tree */
++    err = CcRootTryLock(p_FmPcdCcTree);
++    if (err)
++        return ERROR_CODE(E_BUSY);
++
++    if (p_FmPcdCcTree->h_CapwapReassemblyManip == h_ReassemblyManip)
++    {
++        CcRootReleaseLock(p_FmPcdCcTree);
++        return E_OK;
++    }
++
++    if ((p_FmPcdCcTree->h_CapwapReassemblyManip)
++            && (p_FmPcdCcTree->h_CapwapReassemblyManip != h_ReassemblyManip))
++    {
++        CcRootReleaseLock(p_FmPcdCcTree);
++        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                     ("This tree was previously updated with different CPR"));
++    }
++
++    groupId = p_FmPcdCcTree->numOfGrps++;
++    p_FmPcdCcTree->fmPcdGroupParam[groupId].baseGroupEntry =
++            (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1);
++
++    if (createSchemes)
++    {
++        err = FmPcdManipBuildCapwapReassmScheme(h_FmPcd, h_NetEnv,
++                                                p_FmPcdCcTree,
++                                                h_ReassemblyManip, groupId);
++        if (err)
++        {
++            p_FmPcdCcTree->numOfGrps--;
++            CcRootReleaseLock(p_FmPcdCcTree);
++            RETURN_ERROR(MAJOR, err, NO_MSG);
++        }
++    }
++
++    NextStepAd(
++            PTR_MOVE(h_Ad, (FM_PCD_MAX_NUM_OF_CC_GROUPS-1) * FM_PCD_CC_AD_ENTRY_SIZE),
++            NULL, &nextEngineParams, h_FmPcd);
++
++    p_FmPcdCcTree->h_CapwapReassemblyManip = h_ReassemblyManip;
++
++    CcRootReleaseLock(p_FmPcdCcTree);
++
++    return E_OK;
++}
++
++t_Handle FmPcdCcTreeGetSavedManipParams(t_Handle h_FmTree)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree;
++
++    ASSERT_COND(p_FmPcdCcTree);
++
++    return p_FmPcdCcTree->h_FmPcdCcSavedManipParams;
++}
++
++void FmPcdCcTreeSetSavedManipParams(t_Handle h_FmTree,
++                                    t_Handle h_SavedManipParams)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree;
++
++    ASSERT_COND(p_FmPcdCcTree);
++
++    p_FmPcdCcTree->h_FmPcdCcSavedManipParams = h_SavedManipParams;
++}
++
++uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode;
++
++    ASSERT_COND(p_CcNode);
++
++    return p_CcNode->parseCode;
++}
++
++uint8_t FmPcdCcGetOffset(t_Handle h_CcNode)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode;
++
++    ASSERT_COND(p_CcNode);
++
++    return p_CcNode->offset;
++}
++
++uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode;
++
++    ASSERT_COND(p_CcNode);
++
++    return p_CcNode->numOfKeys;
++}
++
++t_Error FmPcdCcModifyNextEngineParamTree(
++        t_Handle h_FmPcd, t_Handle h_FmPcdCcTree, uint8_t grpId, uint8_t index,
++        t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree;
++    t_FmPcd *p_FmPcd;
++    t_List h_OldPointersLst, h_NewPointersLst;
++    uint16_t keyIndex;
++    t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams;
++    t_Error err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR((grpId <= 7), E_INVALID_VALUE);
++
++    if (grpId >= p_FmPcdCcTree->numOfGrps)
++        RETURN_ERROR(MAJOR, E_INVALID_HANDLE,
++                     ("grpId you asked > numOfGroup of relevant tree"));
++
++    if (index >= p_FmPcdCcTree->fmPcdGroupParam[grpId].numOfEntriesInGroup)
++        RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("index > numOfEntriesInGroup"));
++
++    p_FmPcd = (t_FmPcd *)h_FmPcd;
++
++    INIT_LIST(&h_OldPointersLst);
++    INIT_LIST(&h_NewPointersLst);
++
++    keyIndex = (uint16_t)(p_FmPcdCcTree->fmPcdGroupParam[grpId].baseGroupEntry
++            + index);
++
++    p_ModifyKeyParams = ModifyNodeCommonPart(p_FmPcdCcTree, keyIndex,
++                                             e_MODIFY_STATE_CHANGE, FALSE,
++                                             FALSE, TRUE);
++    if (!p_ModifyKeyParams)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++
++    p_ModifyKeyParams->tree = TRUE;
++
++    if (p_FmPcd->p_CcShadow
++            && !TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
++    {
++        XX_Free(p_ModifyKeyParams);
++        return ERROR_CODE(E_BUSY);
++    }
++
++    err = BuildNewNodeModifyNextEngine(p_FmPcd, p_FmPcdCcTree, keyIndex,
++                                       p_FmPcdCcNextEngineParams,
++                                       &h_OldPointersLst, &h_NewPointersLst,
++                                       p_ModifyKeyParams);
++    if (err)
++    {
++        XX_Free(p_ModifyKeyParams);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst,
++                          p_ModifyKeyParams, FALSE);
++
++    if (p_FmPcd->p_CcShadow)
++        RELEASE_LOCK(p_FmPcd->shadowLock);
++
++    return err;
++
++}
++
++t_Error FmPcdCcRemoveKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode,
++                         uint16_t keyIndex)
++{
++
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode;
++    t_FmPcd *p_FmPcd;
++    t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams;
++    t_List h_OldPointersLst, h_NewPointersLst;
++    bool useShadowStructs = FALSE;
++    t_Error err = E_OK;
++
++    if (keyIndex >= p_CcNode->numOfKeys)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE,
++                     ("impossible to remove key when numOfKeys <= keyIndex"));
++
++    if (p_CcNode->h_FmPcd != h_FmPcd)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("handler to FmPcd is different from the handle provided at node initialization time"));
++
++    p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++
++    INIT_LIST(&h_OldPointersLst);
++    INIT_LIST(&h_NewPointersLst);
++
++    p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex,
++                                             e_MODIFY_STATE_REMOVE, TRUE, TRUE,
++                                             FALSE);
++    if (!p_ModifyKeyParams)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++
++    if (p_CcNode->maxNumOfKeys)
++    {
++        if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
++        {
++            XX_Free(p_ModifyKeyParams);
++            return ERROR_CODE(E_BUSY);
++        }
++
++        useShadowStructs = TRUE;
++    }
++
++    err = BuildNewNodeRemoveKey(p_CcNode, keyIndex, p_ModifyKeyParams);
++    if (err)
++    {
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams,
++                                           &h_OldPointersLst,
++                                           &h_NewPointersLst);
++    if (err)
++    {
++        ReleaseNewNodeCommonPart(p_ModifyKeyParams);
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst,
++                          p_ModifyKeyParams, useShadowStructs);
++
++    if (p_CcNode->maxNumOfKeys)
++        RELEASE_LOCK(p_FmPcd->shadowLock);
++
++    return err;
++}
++
++t_Error FmPcdCcModifyKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode,
++                         uint16_t keyIndex, uint8_t keySize, uint8_t *p_Key,
++                         uint8_t *p_Mask)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode;
++    t_FmPcd *p_FmPcd;
++    t_List h_OldPointersLst, h_NewPointersLst;
++    t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams;
++    uint16_t tmpKeyIndex;
++    bool useShadowStructs = FALSE;
++    t_Error err = E_OK;
++
++    if (keyIndex >= p_CcNode->numOfKeys)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                     ("keyIndex > previously cleared last index + 1"));
++
++    if (keySize != p_CcNode->userSizeOfExtraction)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("size for ModifyKey has to be the same as defined in SetNode"));
++
++    if (p_CcNode->h_FmPcd != h_FmPcd)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("handler to FmPcd is different from the handle provided at node initialization time"));
++
++    err = FindKeyIndex(h_FmPcdCcNode, keySize, p_Key, p_Mask, &tmpKeyIndex);
++    if (GET_ERROR_TYPE(err) != E_NOT_FOUND)
++        RETURN_ERROR(
++                MINOR,
++                E_ALREADY_EXISTS,
++                ("The received key and mask pair was already found in the match table of the provided node"));
++
++    p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++
++    INIT_LIST(&h_OldPointersLst);
++    INIT_LIST(&h_NewPointersLst);
++
++    p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex,
++                                             e_MODIFY_STATE_CHANGE, TRUE, TRUE,
++                                             FALSE);
++    if (!p_ModifyKeyParams)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++
++    if (p_CcNode->maxNumOfKeys)
++    {
++        if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
++        {
++            XX_Free(p_ModifyKeyParams);
++            return ERROR_CODE(E_BUSY);
++        }
++
++        useShadowStructs = TRUE;
++    }
++
++    err = BuildNewNodeModifyKey(p_CcNode, keyIndex, p_Key, p_Mask,
++                                p_ModifyKeyParams);
++    if (err)
++    {
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams,
++                                           &h_OldPointersLst,
++                                           &h_NewPointersLst);
++    if (err)
++    {
++        ReleaseNewNodeCommonPart(p_ModifyKeyParams);
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst,
++                          p_ModifyKeyParams, useShadowStructs);
++
++    if (p_CcNode->maxNumOfKeys)
++        RELEASE_LOCK(p_FmPcd->shadowLock);
++
++    return err;
++}
++
++t_Error FmPcdCcModifyMissNextEngineParamNode(
++        t_Handle h_FmPcd, t_Handle h_FmPcdCcNode,
++        t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode;
++    t_FmPcd *p_FmPcd;
++    t_List h_OldPointersLst, h_NewPointersLst;
++    uint16_t keyIndex;
++    t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams;
++    t_Error err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_VALUE);
++
++    keyIndex = p_CcNode->numOfKeys;
++
++    p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++
++    INIT_LIST(&h_OldPointersLst);
++    INIT_LIST(&h_NewPointersLst);
++
++    p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex,
++                                             e_MODIFY_STATE_CHANGE, FALSE, TRUE,
++                                             FALSE);
++    if (!p_ModifyKeyParams)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++
++    if (p_CcNode->maxNumOfKeys
++            && !TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
++    {
++        XX_Free(p_ModifyKeyParams);
++        return ERROR_CODE(E_BUSY);
++    }
++
++    err = BuildNewNodeModifyNextEngine(h_FmPcd, p_CcNode, keyIndex,
++                                       p_FmPcdCcNextEngineParams,
++                                       &h_OldPointersLst, &h_NewPointersLst,
++                                       p_ModifyKeyParams);
++    if (err)
++    {
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst,
++                          p_ModifyKeyParams, FALSE);
++
++    if (p_CcNode->maxNumOfKeys)
++        RELEASE_LOCK(p_FmPcd->shadowLock);
++
++    return err;
++}
++
++t_Error FmPcdCcAddKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode,
++                      uint16_t keyIndex, uint8_t keySize,
++                      t_FmPcdCcKeyParams *p_FmPcdCcKeyParams)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode;
++    t_FmPcd *p_FmPcd;
++    t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams;
++    t_List h_OldPointersLst, h_NewPointersLst;
++    bool useShadowStructs = FALSE;
++    uint16_t tmpKeyIndex;
++    t_Error err = E_OK;
++
++    if (keyIndex > p_CcNode->numOfKeys)
++        RETURN_ERROR(MAJOR, E_NOT_IN_RANGE,
++                     ("keyIndex > previously cleared last index + 1"));
++
++    if (keySize != p_CcNode->userSizeOfExtraction)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("keySize has to be defined as it was defined in initialization step"));
++
++    if (p_CcNode->h_FmPcd != h_FmPcd)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("handler to FmPcd is different from the handle provided at node initialization time"));
++
++    if (p_CcNode->maxNumOfKeys)
++    {
++        if (p_CcNode->numOfKeys == p_CcNode->maxNumOfKeys)
++            RETURN_ERROR(
++                    MAJOR,
++                    E_FULL,
++                    ("number of keys exceeds the maximal number of keys provided at node initialization time"));
++    }
++    else
++        if (p_CcNode->numOfKeys == FM_PCD_MAX_NUM_OF_KEYS)
++            RETURN_ERROR(
++                    MAJOR,
++                    E_INVALID_VALUE,
++                    ("number of keys can not be larger than %d", FM_PCD_MAX_NUM_OF_KEYS));
++
++    err = FindKeyIndex(h_FmPcdCcNode, keySize, p_FmPcdCcKeyParams->p_Key,
++                       p_FmPcdCcKeyParams->p_Mask, &tmpKeyIndex);
++    if (GET_ERROR_TYPE(err) != E_NOT_FOUND)
++        RETURN_ERROR(
++                MAJOR,
++                E_ALREADY_EXISTS,
++                ("The received key and mask pair was already found in the match table of the provided node"));
++
++    p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++
++    INIT_LIST(&h_OldPointersLst);
++    INIT_LIST(&h_NewPointersLst);
++
++    p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex,
++                                             e_MODIFY_STATE_ADD, TRUE, TRUE,
++                                             FALSE);
++    if (!p_ModifyKeyParams)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++
++    if (p_CcNode->maxNumOfKeys)
++    {
++        if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
++        {
++            XX_Free(p_ModifyKeyParams);
++            return ERROR_CODE(E_BUSY);
++        }
++
++        useShadowStructs = TRUE;
++    }
++
++    err = BuildNewNodeAddOrMdfyKeyAndNextEngine(h_FmPcd, p_CcNode, keyIndex,
++                                                p_FmPcdCcKeyParams,
++                                                p_ModifyKeyParams, TRUE);
++    if (err)
++    {
++        ReleaseNewNodeCommonPart(p_ModifyKeyParams);
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams,
++                                           &h_OldPointersLst,
++                                           &h_NewPointersLst);
++    if (err)
++    {
++        ReleaseNewNodeCommonPart(p_ModifyKeyParams);
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst,
++                          p_ModifyKeyParams, useShadowStructs);
++    if (p_CcNode->maxNumOfKeys)
++        RELEASE_LOCK(p_FmPcd->shadowLock);
++
++    return err;
++}
++
++t_Error FmPcdCcModifyKeyAndNextEngine(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode,
++                                      uint16_t keyIndex, uint8_t keySize,
++                                      t_FmPcdCcKeyParams *p_FmPcdCcKeyParams)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode;
++    t_FmPcd *p_FmPcd;
++    t_List h_OldPointersLst, h_NewPointersLst;
++    t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams;
++    uint16_t tmpKeyIndex;
++    bool useShadowStructs = FALSE;
++    t_Error err = E_OK;
++
++    if (keyIndex > p_CcNode->numOfKeys)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE,
++                     ("keyIndex > previously cleared last index + 1"));
++
++    if (keySize != p_CcNode->userSizeOfExtraction)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("keySize has to be defined as it was defined in initialization step"));
++
++    if (p_CcNode->h_FmPcd != h_FmPcd)
++        RETURN_ERROR(
++                MAJOR,
++                E_INVALID_VALUE,
++                ("handler to FmPcd is different from the handle provided at node initialization time"));
++
++    err = FindKeyIndex(h_FmPcdCcNode, keySize, p_FmPcdCcKeyParams->p_Key,
++                       p_FmPcdCcKeyParams->p_Mask, &tmpKeyIndex);
++    if (GET_ERROR_TYPE(err) != E_NOT_FOUND)
++        RETURN_ERROR(
++                MINOR,
++                E_ALREADY_EXISTS,
++                ("The received key and mask pair was already found in the match table of the provided node"));
++
++    p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd;
++
++    INIT_LIST(&h_OldPointersLst);
++    INIT_LIST(&h_NewPointersLst);
++
++    p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex,
++                                             e_MODIFY_STATE_CHANGE, TRUE, TRUE,
++                                             FALSE);
++    if (!p_ModifyKeyParams)
++        RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG);
++
++    if (p_CcNode->maxNumOfKeys)
++    {
++        if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
++        {
++            XX_Free(p_ModifyKeyParams);
++            return ERROR_CODE(E_BUSY);
++        }
++
++        useShadowStructs = TRUE;
++    }
++
++    err = BuildNewNodeAddOrMdfyKeyAndNextEngine(h_FmPcd, p_CcNode, keyIndex,
++                                                p_FmPcdCcKeyParams,
++                                                p_ModifyKeyParams, FALSE);
++    if (err)
++    {
++        ReleaseNewNodeCommonPart(p_ModifyKeyParams);
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams,
++                                           &h_OldPointersLst,
++                                           &h_NewPointersLst);
++    if (err)
++    {
++        ReleaseNewNodeCommonPart(p_ModifyKeyParams);
++        XX_Free(p_ModifyKeyParams);
++        if (p_CcNode->maxNumOfKeys)
++            RELEASE_LOCK(p_FmPcd->shadowLock);
++        RETURN_ERROR(MAJOR, err, NO_MSG);
++    }
++
++    err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst,
++                          p_ModifyKeyParams, useShadowStructs);
++
++    if (p_CcNode->maxNumOfKeys)
++        RELEASE_LOCK(p_FmPcd->shadowLock);
++
++    return err;
++}
++
++uint32_t FmPcdCcGetNodeAddrOffsetFromNodeInfo(t_Handle h_FmPcd,
++                                              t_Handle h_Pointer)
++{
++    t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
++    t_CcNodeInformation *p_CcNodeInfo;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE,
++                              (uint32_t)ILLEGAL_BASE);
++
++    p_CcNodeInfo = CC_NODE_F_OBJECT(h_Pointer);
++
++    return (uint32_t)(XX_VirtToPhys(p_CcNodeInfo->h_CcNode)
++            - p_FmPcd->physicalMuramBase);
++}
++
++t_Error FmPcdCcGetGrpParams(t_Handle h_FmPcdCcTree, uint8_t grpId,
++                            uint32_t *p_GrpBits, uint8_t *p_GrpBase)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree;
++
++    SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE);
++
++    if (grpId >= p_FmPcdCcTree->numOfGrps)
++        RETURN_ERROR(MAJOR, E_INVALID_HANDLE,
++                     ("grpId you asked > numOfGroup of relevant tree"));
++
++    *p_GrpBits = p_FmPcdCcTree->fmPcdGroupParam[grpId].totalBitsMask;
++    *p_GrpBase = p_FmPcdCcTree->fmPcdGroupParam[grpId].baseGroupEntry;
++
++    return E_OK;
++}
++
++t_Error FmPcdCcBindTree(t_Handle h_FmPcd, t_Handle h_PcdParams,
++                        t_Handle h_FmPcdCcTree, uint32_t *p_Offset,
++                        t_Handle h_FmPort)
++{
++    t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree;
++    t_Error err = E_OK;
++
++    SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE);
++    SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE);
++
++    /* this routine must be protected by the calling routine by locking all PCD modules! */
++
++    err = CcUpdateParams(h_FmPcd, h_PcdParams, h_FmPort, h_FmPcdCcTree, TRUE);
++
++    if (err == E_OK)
++        UpdateCcRootOwner(p_FmPcdCcTree, TRUE);
++
++    *p_Offset = (uint32_t)(XX_VirtToPhys(
++            UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr))
++            - p_FmPcd->physicalMuramBase);
++
++    return err;
++}
++
++t_Error FmPcdCcUnbindTree(t_Handle h_FmPcd, t_Handle h_FmPcdCcTree)
++{
++    t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree;
++
++    /* this routine must be protected by the calling routine by locking all PCD modules! */
++
++    UNUSED(h_FmPcd);
++
++    SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE);
++
++    UpdateCcRootOwner(p_FmPcdCcTree, FALSE);
++
++    return E_OK;
++}
++
++t_Error FmPcdCcNodeTreeTryLock(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode,
++                               t_List *p_List)
++{
++    t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode;
++    t_List *p_Pos, *p_Tmp;
++    t_CcNodeInformation *p_CcNodeInfo, nodeInfo;
++    uint32_t intFlags;
++    t_Error err = E_OK;
++
++    intFlags = FmPcdLock(h_FmPcd);
++
++    LIST_FOR_EACH(p_Pos, &p_CcNode->ccTreesLst)
++    {
++        p_CcNodeInfo = CC_NODE_F_OBJECT(p_Pos);
++        ASSERT_COND(p_CcNodeInfo->h_CcNode);
++
++        err = CcRootTryLock(p_CcNodeInfo->h_CcNode);
++
++        if (err)
++        {
++            LIST_FOR_EACH(p_Tmp, &p_CcNode->ccTreesLst)
++            {
++                if (p_Tmp == p_Pos)
++                    break;
++
++                CcRootReleaseLock(p_CcNodeInfo->h_CcNode);
++            }
++            break;
++        }
++
++        memset(&nodeInfo, 0, sizeof(t_CcNodeInformation));
++        nodeInfo.h_CcNode = p_CcNodeInfo->h_CcNode;
++        EnqueueNodeInfoToRelevantLst(p_List, &nodeInfo, NULL);
++    }
++
++    FmPcdUnlock(h_FmPcd, intFlags);
++    CORE_MemoryBarrier();
++
++    return err;
++}
++
++void FmPcdCcNodeTreeReleaseLock(t_Handle h_FmPcd, t_List *p_List)
++{
++    t_List *p_Pos;
++    t_CcNodeInformation *p_CcNodeInfo;
++    t_Handle h_FmPcdCcTree;
++    uint32_t intFlags;
++
++    intFlags = FmPcdLock(h_FmPcd);
++
++    LIST_FOR_EACH(p_Pos, p_List)
++    {
++        p_CcNodeInfo = CC_NODE_F_OBJECT(p_Pos);
++        h_FmPcdCcTree = p_CcNodeInfo->h_CcNode;
++        CcRootReleaseLock(h_FmPcdCcTree);
++    }
++
++    ReleaseLst(p_List);
++
++    FmPcdUnlock(h_FmPcd, intFlags);
++    CORE_MemoryBarrier();
++}
++
++t_Error FmPcdUpdateCcShadow(t_FmPcd *p_FmPcd, uint32_t size, uint32_t align)
++{
++    uint32_t intFlags;
++    uint32_t newSize = 0, newAlign = 0;
++    bool allocFail = FALSE;
++
++    ASSERT_COND(p_FmPcd);
++
++    if (!size)
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("size must be larger then 0"));
++
++    if (!POWER_OF_2(align))
++        RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("alignment must be power of 2"));
++
++    newSize = p_FmPcd->ccShadowSize;
++    newAlign = p_FmPcd->ccShadowAlign;
++
++    /* Check if current shadow is large enough to hold the requested size */
++    if (size > p_FmPcd->ccShadowSize)
++        newSize = size;
++
++    /* Check if current shadow matches the requested alignment */
++    if (align > p_FmPcd->ccShadowAlign)
++        newAlign = align;
++
++    /* If a bigger shadow size or bigger shadow alignment are required,
++     a new shadow will be allocated */
++    if ((newSize != p_FmPcd->ccShadowSize)
++            || (newAlign != p_FmPcd->ccShadowAlign))
++    {
++        intFlags = FmPcdLock(p_FmPcd);
++
++        if (p_FmPcd->p_CcShadow)
++        {
++            FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_FmPcd), p_FmPcd->p_CcShadow);
++            p_FmPcd->ccShadowSize = 0;
++            p_FmPcd->ccShadowAlign = 0;
++        }
++
++        p_FmPcd->p_CcShadow = FM_MURAM_AllocMem(FmPcdGetMuramHandle(p_FmPcd),
++                                                newSize, newAlign);
++        if (!p_FmPcd->p_CcShadow)
++        {
++            allocFail = TRUE;
++
++            /* If new shadow size allocation failed,
++             re-allocate with previous parameters */
++            p_FmPcd->p_CcShadow = FM_MURAM_AllocMem(
++                    FmPcdGetMuramHandle(p_FmPcd), p_FmPcd->ccShadowSize,
++                    p_FmPcd->ccShadowAlign);
++        }
++
++        FmPcdUnlock(p_FmPcd, intFlags);
++
++        if (allocFail)
++            RETURN_ERROR(MAJOR, E_NO_MEMORY,
++                         ("MURAM allocation for CC Shadow memory"));
++
++        p_FmPcd->ccShadowSize = newSize;
++        p_FmPcd->ccShadowAlign = newAlign;
++    }
++
++    return E_OK;
++}
++
++#if (DPAA_VERSION >= 11)
++void FmPcdCcGetAdTablesThatPointOnReplicGroup(t_Handle h_Node,
++                                              t_Handle h_ReplicGroup,
++                                              t_List *p_AdTables,
++                                              uint32_t *p_NumOfAdTables)
++{
++    t_FmPcdCcNode *p_CurrentNode = (t_FmPcdCcNode *)h_Node;
++    int i = 0;
++    void * p_AdTable;
++    t_CcNodeInformation ccNodeInfo;
++
++    ASSERT_COND(h_Node);
++    *p_NumOfAdTables = 0;
++
++    /* search in the current node which exact index points on this current replicator group for getting AD */
++    for (i = 0; i < p_CurrentNode->numOfKeys + 1; i++)
++    {
++        if ((p_CurrentNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine
++                == e_FM_PCD_FR)
++                && ((p_CurrentNode->keyAndNextEngineParams[i].nextEngineParams.params.frParams.h_FrmReplic
++                        == (t_Handle)h_ReplicGroup)))
++        {
++            /* save the current ad table in the list */
++            /* this entry uses the input replicator group */
++            p_AdTable =
++                    PTR_MOVE(p_CurrentNode->h_AdTable, i*FM_PCD_CC_AD_ENTRY_SIZE);
++            memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation));
++            ccNodeInfo.h_CcNode = p_AdTable;
++            EnqueueNodeInfoToRelevantLst(p_AdTables, &ccNodeInfo, NULL);
++            (*p_NumOfAdTables)++;
++        }
++    }
++
++    ASSERT_COND(i != p_CurrentNode->numOfKeys);
++}
++#endif /* (DPAA_VERSION >= 11) */
++/*********************** End of inter-module routines ************************/
++
++/****************************************/
++/*       API Init unit functions        */
++/****************************************/
++
++t_Handle FM_PCD_CcRootBuild(t_Handle h_FmPcd,
++                            t_FmPcdCcTreeParams *p_PcdGroupsParam)
++{
++    t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
++    t_Error err = E_OK;
++    int i = 0, j = 0, k = 0;
++    t_FmPcdCcTree *p_FmPcdCcTree;
++    uint8_t numOfEntries;
++    t_Handle p_CcTreeTmp;
++    t_FmPcdCcGrpParams *p_FmPcdCcGroupParams;
++    t_FmPcdCcKeyAndNextEngineParams *p_Params, *p_KeyAndNextEngineParams;
++    t_NetEnvParams netEnvParams;
++    uint8_t lastOne = 0;
++    uint32_t requiredAction = 0;
++    t_FmPcdCcNode *p_FmPcdCcNextNode;
++    t_CcNodeInformation ccNodeInfo, *p_CcInformation;
++
++    SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL);
++    SANITY_CHECK_RETURN_VALUE(p_PcdGroupsParam, E_INVALID_HANDLE, NULL);
++
++    if (p_PcdGroupsParam->