[OpenWrt-Devel] [PATCH] kernel: generic 4.1 & 4.4 perf: musl compatibility

Felix Fietkau nbd at openwrt.org
Sat Jan 2 07:46:35 EST 2016

On 2015-12-31 13:22, Roman Yeryomin wrote:
> Kevin, are you sure this works?
> I don't have /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
> on my Archer C7
> I did a little bit more simple way adding a header from eglibc. If
> anybody interested I can submit the patch for RFC.
As far as I can see, glibc only supports reading the cache line size for
few architectures, probably fewer than those that provide the sysfs file.

I don't see a generic way to query this on mips and the return code
should be the same as sysconf on uclibc/glibc, so this function makes
sense. It should probably be made static though...

- Felix
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