[OpenWrt-Devel] [PATCH] ar71xx: fix ar724x clock calculation

Alban albeu at free.fr
Tue Sep 15 14:15:31 EDT 2015

On Wed,  9 Sep 2015 11:19:31 +0800
Weijie Gao <hackpascal at gmail.com> wrote:


I'm working a bit on mainline support for the ATH79 and I would really
like to see such patch making it there. I added this patch to my
tree[1] with a few fixes to the log message. Would you mind submitting
it to mainline?

> Signed-off-by: Weijie Gao <hackpascal at gmail.com>

Signed-off-by should be after the log message.
> According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
> input clock as the REF_CLK instead of 5MHz.

I have a similar problem on AR9132, the board I use (WR1043ND) have a
40MHz oscillator however the computation for the clocks assume a 5MHz
input. Sadly I have no datasheet for the AR9132 so I can't fix the
problem myself :/

> The correct CPU PLL calculation procedure is as follows:
> CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.

In the patch in my tree I replaced DIV with FB (for feedback i think,
see [2]) as it then match with the register name used in the patch.


[1] https://github.com/AlbanBedel/linux/tree/ath79
[2] https://en.wikipedia.org/wiki/Phase-locked_loop#Feedback_path_and_optional_divider
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