[OpenWrt-Devel] [PATCH] Bugfix: use correct PLL configuration register bitmask for QCA956x SoC

[Dmitry Ivanov]

Bugfix: use correct PLL configuration register bitmask for
QCA956x SoC.

Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <dima at ubnt.com>
---
 .../patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch     | 4 ++--
 .../patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch      | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index 3b8e6c5..2596e1c 100644
--- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -528,7 +528,7 @@
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x3fff
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x1fff
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff
 +
@@ -540,7 +540,7 @@
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x3fff
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x1fff
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff
 +
diff --git a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index b23c18e..c7e564d 100644
--- a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -528,7 +528,7 @@
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x3fff
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x1fff
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff
 +
@@ -540,7 +540,7 @@
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x3fff
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x1fff
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff
 +
-- 
2.1.4
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