[OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image

Daniel Schwierzeck daniel.schwierzeck at gmail.com
Tue Jan 20 10:13:21 EST 2015

2015-01-20 15:44 GMT+01:00 Ben Mulvihill <ben.mulvihill at gmail.com>:
> On Tue, 2015-01-20 at 14:05 +0100, Daniel Schwierzeck wrote:
>> 2015-01-20 12:28 GMT+01:00 Ben Mulvihill <ben.mulvihill at gmail.com>:
>> >
>> > Some of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1
>> > out. A patch along these lines should fix it:
>> yes, the code is wrong. I have prepared a patch. Thanks for fixing.
> Thank you.
> The linux code in arch/mips/lantiq/xway/clk.c is wrong too I think.
> Shall I submit a patch to make the functions there return the same
> values as the uboot equivalents?

only ltq_ar9_fpi_hz() should be fixed. If bit 0 is set, than DDR/FPI
clock is 1/3 of SYS clock, otherwise 1/2

> Also, just as a matter of interest, what does CGU_SYS_PPESEL_250_MHZ
> actually do? What does PPE stand for?

it means Packet Processing Engine. It is a separate on-chip CPU for
network offloading functions which only runs with a propietary
firmware from Lantiq. On AR9 the PPE clock is fixed to 250 MHz. The HW
manual says the according bit in CGU_SYS register should be set but
maybe this could be ignored.

- Daniel
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