[OpenWrt-Devel] [PATCH 20/23] ar71xx: modify patch 707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

[Zhao, Gang]

From: "Zhao, Gang" <gamerh2o at gmail.com>

Commit v3.12-rc1~21^2~25(MIPS: ath79: Switch to the clkdev framework)
switched to clkdev framework, so the static variables like
ath79_ref_clk are gone. Make needed changes to address this.

Signed-off-by: Zhao, Gang <gang.zhao.42 at gmail.com>
---
 ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 45 +++++++++++++---------
 1 file changed, 27 insertions(+), 18 deletions(-)

diff --git a/target/linux/ar71xx/patches-3.14/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.14/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 00458d2..7adc0eb 100644
--- a/target/linux/ar71xx/patches-3.14/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.14/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -44,21 +44,25 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  config ATH79_NVRAM
 --- a/arch/mips/ath79/clock.c
 +++ b/arch/mips/ath79/clock.c
-@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
+@@ -295,6 +295,91 @@ static void __init ar934x_clocks_init(vo
  	iounmap(dpll_base);
  }
  
 +static void __init qca953x_clocks_init(void)
 +{
++	unsigned long ref_rate;
++	unsigned long cpu_rate;
++	unsigned long ddr_rate;
++	unsigned long ahb_rate;
 +	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 +	u32 cpu_pll, ddr_pll;
 +	u32 bootstrap;
 +
 +	bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 +	if (bootstrap &	QCA953X_BOOTSTRAP_REF_CLK_40)
-+		ath79_ref_clk.rate = 40 * 1000 * 1000;
++		ref_rate = 40 * 1000 * 1000;
 +	else
-+		ath79_ref_clk.rate = 25 * 1000 * 1000;
++		ref_rate = 25 * 1000 * 1000;
 +
 +	pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
 +	out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
@@ -70,8 +74,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +	frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
 +	       QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
 +
-+	cpu_pll = nint * ath79_ref_clk.rate / ref_div;
-+	cpu_pll += frac * (ath79_ref_clk.rate >> 6) / ref_div;
++	cpu_pll = nint * ref_rate / ref_div;
++	cpu_pll += frac * (ref_rate >> 6) / ref_div;
 +	cpu_pll /= (1 << out_div);
 +
 +	pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
@@ -84,8 +88,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +	frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
 +	       QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
 +
-+	ddr_pll = nint * ath79_ref_clk.rate / ref_div;
-+	ddr_pll += frac * (ath79_ref_clk.rate >> 6) / (ref_div << 4);
++	ddr_pll = nint * ref_rate / ref_div;
++	ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
 +	ddr_pll /= (1 << out_div);
 +
 +	clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
@@ -94,34 +98,39 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +		  QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 +
 +	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
-+		ath79_cpu_clk.rate = ath79_ref_clk.rate;
++		cpu_rate = ref_rate;
 +	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
-+		ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
++		cpu_rate = cpu_pll / (postdiv + 1);
 +	else
-+		ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
++		cpu_rate = ddr_pll / (postdiv + 1);
 +
 +	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 +		  QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 +
 +	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
-+		ath79_ddr_clk.rate = ath79_ref_clk.rate;
++		ddr_rate = ref_rate;
 +	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
-+		ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
++		ddr_rate = ddr_pll / (postdiv + 1);
 +	else
-+		ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
++		ddr_rate = cpu_pll / (postdiv + 1);
 +
 +	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 +		  QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 +
 +	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
-+		ath79_ahb_clk.rate = ath79_ref_clk.rate;
++		ahb_rate = ref_rate;
 +	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-+		ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
++		ahb_rate = ddr_pll / (postdiv + 1);
 +	else
-+		ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
++		ahb_rate = cpu_pll / (postdiv + 1);
 +
-+	ath79_wdt_clk.rate = ath79_ref_clk.rate;
-+	ath79_uart_clk.rate = ath79_ref_clk.rate;
++	ath79_add_sys_clkdev("ref", ref_rate);
++	ath79_add_sys_clkdev("cpu", cpu_rate);
++	ath79_add_sys_clkdev("ddr", ddr_rate);
++	ath79_add_sys_clkdev("ahb", ahb_rate);
++
++	clk_add_alias("wdt", NULL, "ref", NULL);
++	clk_add_alias("uart", NULL, "ref", NULL);
 +}
 +
  static void __init qca955x_clocks_init(void)
-- 
1.9.3
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