[OpenWrt-Devel] [PATCH]ramips: Add Ralink RT3XXX USB OHCI driver

John Crispin john at phrozen.org
Fri Jul 18 04:12:42 EDT 2014


what is wrong with 0120-USB-add-OHCI-EHCI-OF-binding.patch ?



On 18/07/2014 09:08, 郭传鈜 wrote:
> Add Ralink RT3XXX USB OHCI driver from Asus RT-N14U GPL code. This 
> driver will make usb1.1 work on mt7620a.Maybe it can also work
> with mt7620n but I have no routers to test this. In 
> 0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch I replaced
> all CONFIG_RALINK_ with CONFIG_SOC_ because I need to use
> rt_mmap.h provided by this patch and I need to edit this file so
> that it can be used in OpenWrt kernel. 'CONFIG_RALINK_    ' in
> Ralink SDK kernel are called 'CONFIG_SOC_    ' in OpenWrt
> kernel(for example,CONFIG_RALINK_MT7620 in Ralink SDK is
> CONFIG_SOC_MT7620) I'm just a student in China so...Sorry for my
> bad English:-D Signed-off-by: 郭传鈜 <gch981213 at gmail.com> --- 
> target/linux/ramips/mt7620a/config-3.10            |   7 + 
> ...NET-ralink-add-mt7621-SDK-ethernet-driver.patch | 192 +++---- 
> .../0402-add-rt3xxx-usb-ohci-driver.patch          | 607 
> +++++++++++++++++++++ 3 files changed, 710 insertions(+), 96 
> deletions(-) create mode 100644 
> target/linux/ramips/patches-3.10/0402-add-rt3xxx-usb-ohci-driver.patch
>
>
> 
diff --git a/target/linux/ramips/mt7620a/config-3.10
> b/target/linux/ramips/mt7620a/config-3.10 index 6805dd9..f0252b8 
> 100644 --- a/target/linux/ramips/mt7620a/config-3.10 +++ 
> b/target/linux/ramips/mt7620a/config-3.10 @@ -1,6 +1,7 @@ 
> CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y 
> CONFIG_ARCH_DISCARD_MEMBLOCK=y 
> CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y 
> +CONFIG_ARCH_HAS_RESET_CONTROLLER=y 
> CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y
> CONFIG_ARCH_REQUIRE_GPIOLIB=y @@ -138,8 +139,10 @@ CONFIG_PINMUX=y
> CONFIG_RALINK=y CONFIG_RALINK_USBPHY=y CONFIG_RALINK_WDT=y
> +CONFIG_RA_NAT_NONE=y # CONFIG_RCU_STALL_COMMON is not set
> CONFIG_RESET_CONTROLLER=y +CONFIG_RT3XXX_OHCI=y #
> CONFIG_SAMSUNG_USB2PHY is not set # CONFIG_SAMSUNG_USB3PHY is not
> set # CONFIG_SAMSUNG_USBPHY is not set @@ -170,6 +173,10 @@
> CONFIG_USB=m CONFIG_USB_ARCH_HAS_XHCI=y CONFIG_USB_COMMON=m #
> CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC
> is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_HCD_PLATFORM is not set
> CONFIG_USB_PHY=y CONFIG_USB_SUPPORT=y # CONFIG_USB_UHCI_HCD is not
> set diff --git 
> a/target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
>
> 
b/target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
> 
> 
index a3a5ec2..8cd726c 100644
> --- 
> a/target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
>
>
> 
+++
b/target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
> @@ -657,8 +657,8 @@ Subject: [PATCH 1/3] foo +/* + FE_INT_STATUS
> +*/ -+#if defined (CONFIG_RALINK_RT5350) || defined 
> (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ -+ 
> defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
> || defined (CONFIG_RALINK_MT7628) ++#if defined (CONFIG_SOC_RT5350)
> || defined (CONFIG_SOC_RT6855) || defined(CONFIG_SOC_RT6855A) || \
> ++ defined (CONFIG_SOC_MT7620) || defined (CONFIG_SOC_MT7621) || 
> defined (CONFIG_SOC_MT7628) + +#define RX_COHERENT      BIT(31) 
> +#define RX_DLY_INT       BIT(30) @@ -673,7 +673,7 @@ Subject: 
> [PATCH 1/3] foo +#define TX_DONE_INT1     BIT(1) +#define 
> TX_DONE_INT0     BIT(0) + -+#if defined (CONFIG_RALINK_MT7621) 
> ++#if defined (CONFIG_SOC_MT7621) +#define RLS_COHERENT BIT(29)
> +#define RLS_DLY_INT      BIT(28) +#define RLS_DONE_INT BIT(0) @@
> -707,7 +707,7 @@ Subject: [PATCH 1/3] foo + TX_DONE_INT1 |
> TX_DONE_INT0 | \ + RX_DONE_INT0 ) + -+#if defined
> (CONFIG_RALINK_MT7621) ++#if defined (CONFIG_SOC_MT7621) +#define
> QFE_INT_ALL		(RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1) +#define
> QFE_INT_DLY_INIT	(RLS_DLY_INT | RX_DLY_INT) + @@ -717,7 +717,7 @@
> Subject: [PATCH 1/3] foo +/* + * SW_INT_STATUS + */ -+#if defined
> (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined
> (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++#if
> defined (CONFIG_SOC_RT3052) || defined (CONFIG_SOC_RT3352) ||
> defined (CONFIG_SOC_RT5350) || defined (CONFIG_SOC_MT7628) +#define
> PORT0_QUEUE_FULL BIT(14) //port0 queue full +#define
> PORT1_QUEUE_FULL        BIT(15) //port1 queue full +#define
> PORT2_QUEUE_FULL        BIT(16) //port2 queue full @@ -736,8 +736,8
> @@ Subject: [PATCH 1/3] foo +#define ESW_IMR			(RALINK_ETH_SW_BASE
> + 0x04) +#define ESW_INT_ALL (PORT_ST_CHG) + -+#elif defined
> (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ -+
> defined (CONFIG_RALINK_MT7620) ++#elif defined (CONFIG_SOC_RT6855)
> || defined(CONFIG_SOC_RT6855A) || \ ++      defined 
> (CONFIG_SOC_MT7620) +#define MIB_INT                 BIT(25) 
> +#define ACL_INT			BIT(24) +#define P5_LINK_CH		BIT(5) @@ -779,7 
> +779,7 @@ Subject: [PATCH 1/3] foo +#define ESW_P5_IntMn 
> (RALINK_ETH_SW_BASE + 0x4508) +#define ESW_P6_IntMn 
> (RALINK_ETH_SW_BASE + 0x4608) + -+#if defined 
> (CONFIG_RALINK_MT7620) ++#if defined (CONFIG_SOC_MT7620) +#define 
> ESW_P7_IntSn		(RALINK_ETH_SW_BASE + 0x4704) +#define ESW_P7_IntMn 
> (RALINK_ETH_SW_BASE + 0x4708) +#endif @@ -787,7 +787,7 @@ Subject: 
> [PATCH 1/3] foo + +#define ESW_PHY_POLLING		(RALINK_ETH_SW_BASE + 
> 0x7000) + -+#elif defined (CONFIG_RALINK_MT7621) ++#elif defined 
> (CONFIG_SOC_MT7621) + +#define ESW_PHY_POLLING
> (RALINK_ETH_SW_BASE + 0x0000) + @@ -799,7 +799,7 @@ Subject: [PATCH
> 1/3] foo +#define P0_LINK_CH		BIT(0) + + -+#endif //
> CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 ||
> CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)// ++#endif
> // CONFIG_SOC_RT3052 || CONFIG_SOC_RT3352 || CONFIG_SOC_RT5350 ||
> defined (CONFIG_SOC_MT7628)// + +#define RX_BUF_ALLOC_SIZE	2000
> +#define FASTPATH_HEADROOM   	64 @@ -832,8 +832,8 @@ Subject:
> [PATCH 1/3] foo +#define RAPSE_OFFSET		0x0040 +#define
> RAGDMA2_OFFSET		0x0060 +#define RACDMA_OFFSET		0x0080 -+#if defined
> (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) ||
> defined(CONFIG_RALINK_RT6855A) || \ -+    defined
> (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined
> (CONFIG_RALINK_MT7628) ++#if defined (CONFIG_SOC_RT5350) || defined
> (CONFIG_SOC_RT6855) || defined(CONFIG_SOC_RT6855A) || \ ++
> defined (CONFIG_SOC_MT7620) || defined (CONFIG_SOC_MT7621) ||
> defined (CONFIG_SOC_MT7628) + +#define RAPDMA_OFFSET		0x0800
> +#define SDM_OFFSET		0x0C00 @@ -849,7 +849,7 @@ Subject: [PATCH
> 1/3] foo +/* RT3883 */ +#define SYSCFG1			(RALINK_SYSCTL_BASE +
> 0x14) + -+#if defined (CONFIG_RALINK_RT5350) || defined
> (CONFIG_RALINK_MT7628) ++#if defined (CONFIG_SOC_RT5350) || defined
> (CONFIG_SOC_MT7628) + +/* 1. PDMA */ +#define TX_BASE_PTR0 
> (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000) @@ -906,8 +906,8 @@ 
> Subject: [PATCH 1/3] foo +#define SDM_RBCNT 
> (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte 
> count +#define SDM_CS_ERR 
> (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx 
> checksum error count + -+#elif defined (CONFIG_RALINK_RT6855) || 
> defined(CONFIG_RALINK_RT6855A) || \ -+      defined 
> (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) ++#elif 
> defined (CONFIG_SOC_RT6855) || defined(CONFIG_SOC_RT6855A) || \ ++ 
> defined (CONFIG_SOC_MT7620) || defined (CONFIG_SOC_MT7621) + +/* 
> Old FE with New PDMA */ +#define PDMA_RELATED            0x0800 @@ 
> -962,13 +962,13 @@ Subject: [PATCH 1/3] foo +//#define FC_DROP_STA 
> RALINK_FRAME_ENGINE_BASE + 0x18 +#define FOE_TS_T 
> RALINK_FRAME_ENGINE_BASE + 0x10 + -+#if defined 
> (CONFIG_RALINK_MT7620) ++#if defined (CONFIG_SOC_MT7620) +#define 
> GDMA1_RELATED       0x0600 +#define GDMA1_FWD_CFG 
> (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00) +#define 
> GDMA1_SHPR_CFG      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 
> 0x04) +#define GDMA1_MAC_ADRL      (RALINK_FRAME_ENGINE_BASE + 
> GDMA1_RELATED + 0x08) +#define GDMA1_MAC_ADRH 
> (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C) -+#elif defined 
> (CONFIG_RALINK_MT7621) ++#elif defined (CONFIG_SOC_MT7621)
> +#define GDMA1_RELATED       0x0500 +#define GDMA1_FWD_CFG 
> (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00) +#define 
> GDMA1_SHPR_CFG      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 
> 0x04) @@ -996,7 +996,7 @@ Subject: [PATCH 1/3] foo +#define 
> GDMA2_MAC_ADRH      (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 
> 0x10) +#endif + -+#if defined (CONFIG_RALINK_MT7620) ++#if defined 
> (CONFIG_SOC_MT7620) +#define PSE_RELATED         0x0500 +#define 
> PSE_FQFC_CFG        (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
> +#define PSE_IQ_CFG          (RALINK_FRAME_ENGINE_BASE + 
> PSE_RELATED + 0x04) @@ -1014,13 +1014,13 @@ Subject: [PATCH 1/3] 
> foo +#endif + + -+#if defined (CONFIG_RALINK_MT7620) ++#if defined 
> (CONFIG_SOC_MT7620) +#define CDMA_RELATED        0x0400 +#define 
> CDMA_CSG_CFG        (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 
> 0x00) +#define SMACCR0		    (RALINK_ETH_SW_BASE + 0x3FE4) +#define 
> SMACCR1		    (RALINK_ETH_SW_BASE + 0x3FE8) +#define CKGCR 
> (RALINK_ETH_SW_BASE + 0x3FF0) -+#elif defined 
> (CONFIG_RALINK_MT7621) ++#elif defined (CONFIG_SOC_MT7621)
> +#define CDMA_RELATED        0x0400 +#define CDMA_CSG_CFG 
> (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
>  +#define CDMP_IG_CTRL        (RALINK_FRAME_ENGINE_BASE + 
> CDMA_RELATED + 0x00) @@ -1037,7 +1037,7 @@ Subject: [PATCH 1/3] foo
> +#define PDMA_FC_CFG	    (RALINK_FRAME_ENGINE_BASE+0x100) + + -+#if
> defined (CONFIG_RALINK_MT7621) ++#if defined (CONFIG_SOC_MT7621)
> +/*kurtis: add QDMA define*/ + +#define CLK_CFG_0
> (RALINK_SYSCTL_BASE + 0x2C) @@ -1242,7 +1242,7 @@ Subject: [PATCH
> 1/3] foo +#define FE_INT_DLY_INIT		(TX_DLY_INT | RX_DLY_INT) + +
> -+#if !defined (CONFIG_RALINK_RT5350) && !defined 
> (CONFIG_RALINK_MT7628) ++#if !defined (CONFIG_SOC_RT5350) && 
> !defined (CONFIG_SOC_MT7628) + +/* 6. Counter and Meter Table */ 
> +#define PPE_AC_BCNT0 
> (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE
> Accounting Group 0 Byte Cnt */ @@ -1306,7 +1306,7 @@ Subject:
> [PATCH 1/3] foo +#define GDM1_JMB_EN   	   (0x1 << 19) +#define
> GDM1_STRPCRC (0x1 << 16) +#define GDM1_UFRC_P_CPU     (0 << 12)
> -+#if defined (CONFIG_RALINK_MT7621) ++#if defined
> (CONFIG_SOC_MT7621) +#define GDM1_UFRC_P_PPE     (4 << 12) +#else
> +#define GDM1_UFRC_P_PPE (6 << 12) @@ -1314,7 +1314,7 @@ Subject:
> [PATCH 1/3] foo + +//GDMA1 broad-cast MAC address frames +#define
> GDM1_BFRC_P_CPU     (0 << 8) -+#if defined (CONFIG_RALINK_MT7621)
> ++#if defined (CONFIG_SOC_MT7621) +#define GDM1_BFRC_P_PPE     (4
> << 8) +#else +#define GDM1_BFRC_P_PPE     (6 << 8) @@ -1322,7
> +1322,7 @@ Subject: [PATCH 1/3] foo + +//GDMA1 multi-cast MAC
> address frames +#define GDM1_MFRC_P_CPU     (0 << 4) -+#if defined 
> (CONFIG_RALINK_MT7621) ++#if defined (CONFIG_SOC_MT7621) +#define 
> GDM1_MFRC_P_PPE     (4 << 4) +#else +#define GDM1_MFRC_P_PPE
> (6 << 4) @@ -1330,13 +1330,13 @@ Subject: [PATCH 1/3] foo +
> +//GDMA1 other MAC address frames destination port +#define
> GDM1_OFRC_P_CPU (0 << 0) -+#if defined (CONFIG_RALINK_MT7621) ++#if
> defined (CONFIG_SOC_MT7621) +#define GDM1_OFRC_P_PPE     (4 << 0)
> +#else +#define GDM1_OFRC_P_PPE     (6 << 0) +#endif + -+#if
> defined (CONFIG_RALINK_RT6856) || defined (CONFIG_RALINK_MT7620) ||
> defined (CONFIG_RALINK_MT7621) ++#if defined (CONFIG_SOC_RT6856) ||
> defined (CONFIG_SOC_MT7620) || defined (CONFIG_SOC_MT7621) +/*
> checksum generator registers are removed */ +#define ICS_GEN_EN
> (0 << 2) +#define UCS_GEN_EN          (0 << 1) @@ -1476,7 +1476,7
> @@ Subject: [PATCH 1/3] foo + +struct _PDMA_RXD_INFO4_ +{ -+#if 
> defined (CONFIG_RALINK_MT7620) ++#if defined (CONFIG_SOC_MT7620) + 
> unsigned int    FOE_Entry           : 14; +    unsigned int
> CRSN : 5; +    unsigned int    SPORT		: 3; @@ -1487,7 +1487,7 @@ 
> Subject: [PATCH 1/3] foo +    unsigned int    IP4			: 1; + unsigned
> int    IP6			: 1; +    unsigned int    UN_USE1		: 4; -+#elif
> defined (CONFIG_RALINK_MT7621) ++#elif defined (CONFIG_SOC_MT7621)
> +    unsigned int    FOE_Entry           : 14; +    unsigned int
> CRSN		: 5; +    unsigned int    SP			: 4; @@ -1560,7 +1560,7 @@
> Subject: [PATCH 1/3] foo + +struct _PDMA_TXD_INFO4_ +{ -+#if
> defined (CONFIG_RALINK_MT7620) ++#if defined (CONFIG_SOC_MT7620) +
> unsigned int    VPRI_VIDX : 8; +    unsigned int    SIDX
> : 4; +    unsigned int    INSP                : 1; @@ -1569,7
> +1569,7 @@ Subject: [PATCH 1/3] foo +    unsigned int    FP_BMAP
> : 8; + unsigned int    TSO			: 1; +    unsigned int    TUI_CO		: 3;
>  -+#elif defined (CONFIG_RALINK_MT7621) ++#elif defined 
> (CONFIG_SOC_MT7621) +    unsigned int    VLAN_TAG		:17; // 
> INSV(1)+VPRI(3)+CFI(1)+VID(12) +    unsigned int    RESV : 2; +
> unsigned int    UDF                 : 6; @@ -1607,7 +1607,7 @@
> Subject: [PATCH 1/3] foo +}; + + -+#if defined 
> (CONFIG_RALINK_MT7621) ++#if defined (CONFIG_SOC_MT7621) 
> +/*========================================= +      QDMA TX 
> Descriptor Format define 
> +=========================================*/ @@ -1683,8 +1683,8 @@ 
> Subject: [PATCH 1/3] foo + +/* proc definition */ + -+#if !defined 
> (CONFIG_RALINK_RT6855) && !defined(CONFIG_RALINK_RT6855A) && \ -+ 
> !defined (CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7621) 
> ++#if !defined (CONFIG_SOC_RT6855) && !defined(CONFIG_SOC_RT6855A) 
> && \ ++    !defined (CONFIG_SOC_MT7620) && !defined 
> (CONFIG_SOC_MT7621) +#define CDMA_OQ_STA 
> (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c) +#define GDMA1_OQ_STA 
> (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50) +#define PPE_OQ_STA 
> (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54) @@ -1692,27 +1692,27 
> @@ Subject: [PATCH 1/3] foo +#endif + +#define
> PROCREG_CONTROL_FILE "/var/run/procreg_control" -+#if defined
> (CONFIG_RALINK_RT2880) ++#if defined (CONFIG_SOC_RT2880) +#define
> PROCREG_DIR "rt2880" -+#elif defined (CONFIG_RALINK_RT3052) ++#elif
> defined (CONFIG_SOC_RT3052) +#define PROCREG_DIR
> "rt3052" -+#elif defined (CONFIG_RALINK_RT3352) ++#elif defined 
> (CONFIG_SOC_RT3352) +#define PROCREG_DIR             "rt3352" 
> -+#elif defined (CONFIG_RALINK_RT5350) ++#elif defined 
> (CONFIG_SOC_RT5350) +#define PROCREG_DIR             "rt5350" 
> -+#elif defined (CONFIG_RALINK_RT2883) ++#elif defined 
> (CONFIG_SOC_RT2883) +#define PROCREG_DIR             "rt2883" 
> -+#elif defined (CONFIG_RALINK_RT3883) ++#elif defined 
> (CONFIG_SOC_RT3883) +#define PROCREG_DIR             "rt3883" 
> -+#elif defined (CONFIG_RALINK_RT6855) ++#elif defined 
> (CONFIG_SOC_RT6855) +#define PROCREG_DIR             "rt6855" 
> -+#elif defined (CONFIG_RALINK_MT7620) ++#elif defined 
> (CONFIG_SOC_MT7620) +#define PROCREG_DIR             "mt7620" 
> -+#elif defined (CONFIG_RALINK_MT7621) ++#elif defined 
> (CONFIG_SOC_MT7621) +#define PROCREG_DIR             "mt7621" 
> -+#elif defined (CONFIG_RALINK_MT7628) ++#elif defined 
> (CONFIG_SOC_MT7628) +#define PROCREG_DIR             "mt7628" 
> -+#elif defined (CONFIG_RALINK_RT6855A) ++#elif defined 
> (CONFIG_SOC_RT6855A) +#define PROCREG_DIR             "rt6855a" 
> +#else +#define PROCREG_DIR             "rt2880" @@ -1789,10 
> +1789,10 @@ Subject: [PATCH 1/3] foo + +    unsigned int 
> phy_rx_ring0, phy_rx_ring1; + -+#if defined (CONFIG_RALINK_RT3052) 
> || defined (CONFIG_RALINK_RT3352) || \ -+    defined 
> (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || \ -+ 
> defined(CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)
> || \ -+    defined(CONFIG_RALINK_MT7621) || defined 
> (CONFIG_RALINK_MT7628) ++#if defined (CONFIG_SOC_RT3052) ||
> defined (CONFIG_SOC_RT3352) || \ ++    defined (CONFIG_SOC_RT5350)
> || defined (CONFIG_SOC_RT6855) || \ ++
> defined(CONFIG_SOC_RT6855A) || defined (CONFIG_SOC_MT7620) || \ ++ 
> defined(CONFIG_SOC_MT7621) || defined (CONFIG_SOC_MT7628) + //send
> signal to user application to notify link status changed + struct
> work_struct  kill_sig_wq; +#endif @@ -1904,8 +1904,8 @@ Subject:
> [PATCH 1/3] foo +#define RAETH_QDMA_QUEUE_MAPPING 0x89FA +#define
> RAETH_QDMA_READ_CPU_CLK         0x89FB + -+#if defined
> (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ -+
> defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
> ++#if defined (CONFIG_SOC_RT6855) || defined(CONFIG_SOC_RT6855A) ||
> \ ++    defined (CONFIG_SOC_MT7620) || defined(CONFIG_SOC_MT7621) +
> +#define REG_ESW_WT_MAC_MFC 0x10 +#define REG_ESW_WT_MAC_ATA1
> 0x74 @@ -1949,10 +1949,10 @@ Subject: [PATCH 1/3] foo +#endif + +
> -+#if defined(CONFIG_RALINK_RT3352) || defined
> (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++#if
> defined(CONFIG_SOC_RT3352) || defined (CONFIG_SOC_RT5350) ||
> defined (CONFIG_SOC_MT7628) +#define REG_ESW_MAX			0x16C -+#elif
> defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) ||
> \ -+      defined (CONFIG_RALINK_MT7620) ++#elif defined
> (CONFIG_SOC_RT6855) || defined(CONFIG_SOC_RT6855A) || \ ++
> defined (CONFIG_SOC_MT7620) +#define REG_ESW_MAX			0x7FFFF +#else
> //RT305x, RT3350 +#define REG_ESW_MAX			0xFC @@ -2101,8 +2101,8 @@
> Subject: [PATCH 1/3] foo +int debug_proc_init(void); +void 
> debug_proc_exit(void); + -+#if defined (CONFIG_RALINK_RT6855) || 
> defined(CONFIG_RALINK_RT6855A) || \ -+           defined 
> (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) ++#if 
> defined (CONFIG_SOC_RT6855) || defined(CONFIG_SOC_RT6855A) || \ ++ 
> defined (CONFIG_SOC_MT7620) || defined(CONFIG_SOC_MT7621) +void 
> enable_auto_negotiate(int unused); +#else +void 
> enable_auto_negotiate(int ge); @@ -2830,7 +2830,7 @@ Subject: 
> [PATCH 1/3] foo +#define RX_RING_BASE	((int)(ESRAM_BASE + 0x7000))
>  +#define TX_RING_BASE	((int)(ESRAM_BASE + 0x7800)) + -+#if 
> defined(CONFIG_RALINK_RT2880) ++#if defined(CONFIG_SOC_RT2880) 
> +#define NUM_TX_RINGS 	1 +#else +#define NUM_TX_RINGS 	4 @@
> -2859,7 +2859,7 @@ Subject: [PATCH 1/3] foo +#define NUM_RX_DESC
> 256 +#define NUM_TX_DESC     256 +#endif -+#if 
> defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620) 
> ++#if defined(CONFIG_SOC_RT3883) || defined(CONFIG_SOC_MT7620) 
> +#define NUM_RX_MAX_PROCESS 2 +#else +#define NUM_RX_MAX_PROCESS 16
> @@ -2869,7 +2869,7 @@ Subject: [PATCH 1/3] foo +#define DEV_NAME 
> "eth0" +#define DEV2_NAME       "eth3" + -+#if defined 
> (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621) ++#if 
> defined (CONFIG_SOC_RT6855A) || defined (CONFIG_SOC_MT7621) 
> +#define GMAC0_OFFSET    0xE000 +#define GMAC2_OFFSET    0xE006 
> +#else @@ -2877,7 +2877,7 @@ Subject: [PATCH 1/3] foo +#define 
> GMAC2_OFFSET    0x22 +#endif + -+#if defined(CONFIG_RALINK_RT6855A)
> ++#if defined(CONFIG_SOC_RT6855A) +#define IRQ_ENET0	22 +#else
> +#define IRQ_ENET0	11 	/* hardware interrupt #3, defined in RT2880
> Soc Design Spec Rev 0.03, pp43 */ @@ -3198,7 +3198,7 @@ Subject:
> [PATCH 1/3] foo +extern int (*ra_classifier_hook_rx)(struct sk_buff
> *skb, unsigned long cur_cycle); +#endif /* CONFIG_RA_CLASSIFIER */
> + -+#if defined (CONFIG_RALINK_RT3052_MP2) ++#if defined
> (CONFIG_SOC_RT3052_MP2) +int32_t mcast_rx(struct sk_buff * skb);
> +int32_t mcast_tx(struct sk_buff * skb); +#endif @@ -3247,7 +3247,7
> @@ Subject: [PATCH 1/3] foo +#endif // CONFIG_PSEUDO_SUPPORT //
> +#endif // (CONFIG_ETHTOOL // + -+#ifdef CONFIG_RALINK_VISTA_BASIC
> ++#ifdef CONFIG_SOC_VISTA_BASIC +int is_switch_175c = 1; +#endif +
> @@ -3611,7 +3611,7 @@ Subject: [PATCH 1/3] foo + 
> cpu_ptr->txd_info3.QID = 0; +#endif + -+#if defined 
> (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) 
> && !defined (CONFIG_RALINK_MT7628) ++#if defined 
> (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_SOC_RT5350) && 
> !defined (CONFIG_SOC_MT7628) +	if (skb->ip_summed == 
> CHECKSUM_PARTIAL){ +	    cpu_ptr->txd_info4.TUI_CO = 7; +	}else { 
> @@ -3679,7 +3679,7 @@ Subject: [PATCH 1/3] foo + + 
> cpu_ptr->txd_info4.TSO = 0; +        cpu_ptr->txd_info3.QID = 
> M2Q_table[skb->mark]; -+#if defined
> (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350)
> && !defined (CONFIG_RALINK_MT7628) ++#if defined 
> (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_SOC_RT5350) && 
> !defined (CONFIG_SOC_MT7628) +	if (skb->ip_summed == 
> CHECKSUM_PARTIAL){ +	    cpu_ptr->txd_info4.TUI_CO = 7; +	}else { 
> @@ -3834,7 +3834,7 @@ Subject: [PATCH 1/3] foo +	num_of_txd = 1; 
> +#endif + -+#if defined(CONFIG_RALINK_MT7621) ++#if 
> defined(CONFIG_SOC_MT7621) + if(sysRegRead(0xbe00000c)==0x00030101)
> { + ei_xmit_housekeeping(0); +    } @@ -4177,7 +4177,7 @@ Subject: 
> [PATCH 1/3] foo +#define RALINK_PCI_CONFIG_ADDR 		    	0x20 
> +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG   	0x24 + -+#if 
> defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883) 
> ++#if defined(CONFIG_SOC_RT2880) || defined(CONFIG_SOC_RT2883) 
> +#define RALINK_PCI_PCICFG_ADDR 		*(volatile u32
> *)(RALINK_PCI_BASE + 0x0000) +#define RALINK_PCI_PCIRAW_ADDR
> *(volatile u32 *)(RALINK_PCI_BASE + 0x0004) +#define
> RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
> @@ -4193,7 +4193,7 @@ Subject: [PATCH 1/3] foo +#define
> RALINK_PCI_ARBCTL 		*(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
> +#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
> 0x0050) + -+#elif defined(CONFIG_RALINK_RT3883) ++#elif
> defined(CONFIG_SOC_RT3883) + +#define RALINK_PCI_PCICFG_ADDR
> *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) +#define
> RALINK_PCI_PCIRAW_ADDR 		*(volatile u32 *)(RALINK_PCI_BASE +
> 0x0004) @@ -4224,7 +4224,7 @@ Subject: [PATCH 1/3] foo +#define
> RALINK_PCI1_SUBID 		*(volatile u32 *)(RALINK_PCI_BASE +
> RT3883_PCIE_OFFSET + 0x0038) +#define RALINK_PCI1_STATUS
> *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050) +
> -+#elif defined(CONFIG_RALINK_RT6855) || defined
> (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628) ++#elif
> defined(CONFIG_SOC_RT6855) || defined (CONFIG_SOC_MT7620) ||
> defined(CONFIG_SOC_MT7628) + +#define RALINK_PCI_PCICFG_ADDR
> *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) +#define
> RALINK_PCI_PCIRAW_ADDR 		*(volatile u32 *)(RALINK_PCI_BASE +
> 0x0004) @@ -4260,7 +4260,7 @@ Subject: [PATCH 1/3] foo +#define
> RALINK_PCI1_DERR		*(volatile u32 *)(RALINK_PCI_BASE +
> RT6855_PCIE1_OFFSET + 0x0060) +#define RALINK_PCI1_ECRC		*(volatile
> u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) + -+#elif
> defined (CONFIG_RALINK_MT7621) ++#elif defined (CONFIG_SOC_MT7621)
> + +#define RALINK_PCI_PCICFG_ADDR 		*(volatile u32
> *)(RALINK_PCI_BASE + 0x0000) +#define RALINK_PCI_PCIRAW_ADDR
> *(volatile u32 *)(RALINK_PCI_BASE + 0x0004) @@ -4310,7 +4310,7 @@
> Subject: [PATCH 1/3] foo +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET
> (RALINK_PCI_BASE + 0x9000) +#define RALINK_PCIEPHY_P2_CTL_OFFSET
> (RALINK_PCI_BASE + 0xA000) + -+#elif defined(CONFIG_RALINK_RT3052)
> || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350) 
> ++#elif defined(CONFIG_SOC_RT3052) || defined(CONFIG_SOC_RT3352)
> || defined(CONFIG_SOC_RT5350) +#else +#error "undefined in PCI" 
> +#endif @@ -4486,7 +4486,7 @@ Subject: [PATCH 1/3] foo +#ifndef 
> __RALINK_MMAP__ +#define __RALINK_MMAP__ + -+#if defined 
> (CONFIG_RALINK_RT2880_SHUTTLE) ++#if defined 
> (CONFIG_SOC_RT2880_SHUTTLE) + +#define RALINK_SYSCTL_BASE 
> 0xA0300000 +#define RALINK_TIMER_BASE		0xA0300100 @@ -4527,7 
> +4527,7 @@ Subject: [PATCH 1/3] foo +#define RALINK_PCM_RST (1<<19)
> + + -+#elif defined (CONFIG_RALINK_RT2880_MP) ++#elif defined
> (CONFIG_SOC_RT2880_MP) + +#define RALINK_SYSCTL_BASE 0xA0300000
> +#define RALINK_TIMER_BASE		0xA0300100 @@ -4567,7 +4567,7 @@
> Subject: [PATCH 1/3] foo +#define RALINK_FE_RST (1<<18) +#define
> RALINK_PCM_RST			(1<<19) + -+#elif defined (CONFIG_RALINK_RT3052)
> ++#elif defined (CONFIG_SOC_RT3052) + +#define RALINK_SYSCTL_BASE
> 0xB0000000 +#define RALINK_TIMER_BASE 0xB0000100 @@ -4625,7 +4625,7
> @@ Subject: [PATCH 1/3] foo +#define RALINK_SW_RST			(1<<23)
> +#define RALINK_EPHY_RST			(1<<24) + -+#elif defined
> (CONFIG_RALINK_RT3352) ++#elif defined (CONFIG_SOC_RT3352) +
> +#define RALINK_SYSCTL_BASE		0xB0000000 +#define RALINK_TIMER_BASE
> 0xB0000100 @@ -4693,7 +4693,7 @@ Subject: [PATCH 1/3] foo +#define
> RALINK_GE1_CLK_EN		(1<<16) + + -+#elif defined
> (CONFIG_RALINK_RT5350) ++#elif defined (CONFIG_SOC_RT5350) +
> +#define RALINK_SYSCTL_BASE		0xB0000000 +#define RALINK_TIMER_BASE
> 0xB0000100 @@ -4759,7 +4759,7 @@ Subject: [PATCH 1/3] foo +#define
> RALINK_UPHY0_CLK_EN		(1<<18) +#define RALINK_GE1_CLK_EN		(1<<16) +
> -+#elif defined (CONFIG_RALINK_RT2883) ++#elif defined
> (CONFIG_SOC_RT2883) + +#define RALINK_SYSCTL_BASE		0xB0000000
> +#define RALINK_TIMER_BASE 0xB0000100 @@ -4815,7 +4815,7 @@
> Subject: [PATCH 1/3] foo +#define RALINK_OTG_RST			(1<<22) +#define
> RALINK_PCIE_RST			(1<<23) + -+#elif defined (CONFIG_RALINK_RT3883)
> ++#elif defined (CONFIG_SOC_RT3883) + +#define RALINK_SYSCTL_BASE
> 0xB0000000 +#define RALINK_TIMER_BASE		0xB0000100 @@ -4883,7
> +4883,7 @@ Subject: [PATCH 1/3] foo +#define RALINK_UPHY0_CLK_EN
> (1<<18) +#define RALINK_GE1_CLK_EN		(1<<16) + -+#elif defined 
> (CONFIG_RALINK_RT6855) ++#elif defined (CONFIG_SOC_RT6855) + 
> +#define RALINK_SYSCTL_BASE		0xB0000000 +#define RALINK_TIMER_BASE 
> 0xB0000100 @@ -4952,7 +4952,7 @@ Subject: [PATCH 1/3] foo +#define 
> RALINK_PCIE1_CLK_EN		(1<<27) + + -+#elif defined 
> (CONFIG_RALINK_MT7620) ++#elif defined (CONFIG_SOC_MT7620) + 
> +#define RALINK_SYSCTL_BASE		0xB0000000 +#define RALINK_TIMER_BASE 
> 0xB0000100 @@ -5039,7 +5039,7 @@ Subject: [PATCH 1/3] foo +#define 
> CPLL_DIV_RATIO                  (0x3UL << CPLL_DIV_RATIO_SHIFT) 
> +#define BASE_CLOCK                      40      /* Mhz */ + 
> -+#elif defined (CONFIG_RALINK_MT7621) ++#elif defined 
> (CONFIG_SOC_MT7621) + +#define RALINK_SYSCTL_BASE		0xBE000000 
> +#define RALINK_TIMER_BASE		0xBE000100 @@ -5154,7 +5154,7 @@ 
> Subject: [PATCH 1/3] foo +#define RALINK_TESTSTAT			0xBE000018 
> +#define RALINK_TESTSTAT2		0xBE00001C + -+#elif defined 
> (CONFIG_RALINK_MT7628) ++#elif defined (CONFIG_SOC_MT7628) + 
> +#define RALINK_SYSCTL_BASE		0xB0000000 +#define RALINK_TIMER_BASE 
> 0xB0000100 @@ -5289,7 +5289,7 @@ Subject: [PATCH 1/3] foo + 
> **************************************************************************
>
>
> 
+ */
> + -+#if defined (CONFIG_RALINK_MT7621) || defined 
> (CONFIG_RALINK_MT7628) ++#if defined (CONFIG_SOC_MT7621) ||
> defined (CONFIG_SOC_MT7628) +#define RT2880_UART_RBR_OFFSET  0x00
> +#define RT2880_UART_TBR_OFFSET  0x00 +#define
> RT2880_UART_IER_OFFSET  0x04 @@ -5325,14 +5325,14 @@ Subject:
> [PATCH 1/3] foo +#define DLM(x) *(volatile u32
> *)((x)+RT2880_UART_DLM_OFFSET) + + -+#if defined 
> (CONFIG_RALINK_RT2880) || \ -+    defined (CONFIG_RALINK_RT2883)
> || \ -+    defined (CONFIG_RALINK_RT3883) || \ -+    defined 
> (CONFIG_RALINK_RT3352) || \ -+    defined (CONFIG_RALINK_RT5350)
> || \ -+    defined (CONFIG_RALINK_RT6855) || \ -+    defined 
> (CONFIG_RALINK_MT7620) || \ -+    defined (CONFIG_RALINK_RT3052) 
> ++#if defined (CONFIG_SOC_RT2880) || \ ++    defined 
> (CONFIG_SOC_RT2883) || \ ++    defined (CONFIG_SOC_RT3883) || \ ++ 
> defined (CONFIG_SOC_RT3352) || \ ++    defined (CONFIG_SOC_RT5350) 
> || \ ++    defined (CONFIG_SOC_RT6855) || \ ++    defined 
> (CONFIG_SOC_MT7620) || \ ++    defined (CONFIG_SOC_RT3052) + 
> +#define UART_RX		0	/* In:  Receive buffer (DLAB=0) */ + @@ 
> -5852,13 +5852,13 @@ Subject: [PATCH 1/3] foo +#define 
> _SURFBOARDINT_H + +/* Number of IRQ supported on hw interrupt 0. */
> -+#if defined (CONFIG_RALINK_RT2880) ++#if defined 
> (CONFIG_SOC_RT2880) +#define RALINK_CPU_TIMER_IRQ 	 6	/* mips
> timer */ +#define SURFBOARDINT_GPIO	 7	/* GPIO */ +#define 
> SURFBOARDINT_UART1	 8	/* UART Lite */ +#define SURFBOARDINT_UART
> 9 /* UART */ +#define SURFBOARDINT_TIMER0	 10	/* timer0 */ -+#elif 
> defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352)
> || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350)
> || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
>  ++#elif defined (CONFIG_SOC_RT3052) || defined
> (CONFIG_SOC_RT3352) || defined (CONFIG_SOC_RT2883) || defined
> (CONFIG_SOC_RT5350) || defined (CONFIG_SOC_RT6855) || defined
> (CONFIG_SOC_MT7620) +#define RALINK_CPU_TIMER_IRQ 	 5	/* mips timer
> */ +#define SURFBOARDINT_GPIO	 6	/* GPIO */ +#define
> SURFBOARDINT_DMA	 7	/* DMA */ @@ -5879,7 +5879,7 @@ Subject: [PATCH
> 1/3] foo +#define RALINK_INT_PCIE1	 14	/* PCIE1 */ + + -+#elif
> defined (CONFIG_RALINK_MT7628) ++#elif defined (CONFIG_SOC_MT7628)
> +#define SURFBOARDINT_SYSCTL      0      /* SYSCTL */ +#define 
> SURFBOARDINT_PCM         4      /* PCM */ +#define 
> SURFBOARDINT_GPIO        6      /* GPIO */ @@ -5904,7 +5904,7 @@ 
> Subject: [PATCH 1/3] foo +#define RALINK_INT_PCIE0         2
> /* PCIE0 */ + + -+#elif defined (CONFIG_RALINK_MT7621) ++#elif
> defined (CONFIG_SOC_MT7621) + +#define SURFBOARDINT_FE	 	 3	/* FE
> */ +#define SURFBOARDINT_PCIE0 	 4	/* PCIE0 */ @@ -5941,7 +5941,7
> @@ Subject: [PATCH 1/3] foo +#define RALINK_INT_PCIE1 
> SURFBOARDINT_PCIE1 +#define RALINK_INT_PCIE2	 SURFBOARDINT_PCIE2 +
>  -+#elif defined (CONFIG_RALINK_RT3883) ++#elif defined 
> (CONFIG_SOC_RT3883) +#define RALINK_CPU_TIMER_IRQ     5      /* 
> mips timer */ +#define SURFBOARDINT_GPIO        6      /* GPIO */ 
> +#define SURFBOARDINT_DMA         7      /* DMA */ @@ -5975,7 
> +5975,7 @@ Subject: [PATCH 1/3] foo + * Surfboard registers are 
> memory mapped on 32-bit aligned boundaries and + * only word
> access are allowed. + */ -+#if defined (CONFIG_RALINK_MT7621) ||
> defined (CONFIG_RALINK_MT7628) ++#if defined (CONFIG_SOC_MT7621) ||
> defined (CONFIG_SOC_MT7628) +#define RALINK_IRQ0STAT
> (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT +#define RALINK_IRQ1STAT
> (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT +#define RALINK_INTTYPE
> (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL diff --git 
> a/target/linux/ramips/patches-3.10/0402-add-rt3xxx-usb-ohci-driver.patch
>
> 
b/target/linux/ramips/patches-3.10/0402-add-rt3xxx-usb-ohci-driver.patch
> 
> 
new file mode 100644
> index 0000000..a26a79d --- /dev/null +++ 
> b/target/linux/ramips/patches-3.10/0402-add-rt3xxx-usb-ohci-driver.patch
>
>
> 
@@ -0,0 +1,607 @@
> +diff -ruN a/drivers/usb/host/ehci-rt3xxx.c 
> b/drivers/usb/host/ehci-rt3xxx.c +--- 
> a/drivers/usb/host/ehci-rt3xxx.c	1970-01-01 08:00:00.000000000 
> +0800 ++++ b/drivers/usb/host/ehci-rt3xxx.c	2014-07-16 
> 16:22:32.201266536 +0800 +@@ -0,0 +1,202 @@ ++/* ++ * Ralink 
> 3XXX(3883) EHCI Host Controller Driver ++ * ++ * Author: Ying Yuan 
> Huang <yyhuang at ralinktech.com.tw> ++ * Based on "ehci-fsl.c" by 
> Randy Vinson <rvinson at mvista.com> ++ * ++ * 2009 (c) Ralink 
> Technology, Inc. This file is licensed under ++ * the terms of the 
> GNU General Public License version 2. This program ++ * is
> licensed "as is" without any warranty of any kind, whether express
> ++ * or implied. ++ */ ++ ++#include <linux/platform_device.h>
> ++#include "ralink_usb.h" ++ ++ ++void static inline rt_writel(u32
> val, unsigned long reg) ++{ ++    *(volatile u32 *)(reg) = val; ++}
> ++ ++static inline u32 rt_readl(unsigned long reg) ++{ ++
> return (*(volatile u32 *)reg); ++} ++ ++static int
> rt_set_host(void) ++{ ++	u32 val = rt_readl(SYSCFG1); ++	// host
> mode ++	val |= USB0_HOST_MODE; ++	rt_writel(val, SYSCFG1); ++} ++
> ++static int rt_usbhost_reset(void) ++{ ++	u32 val = 
> rt_readl(RT2880_RSTCTRL_REG); ++	val |= RALINK_UHST_RST; ++ 
> rt_writel(val, RT2880_RSTCTRL_REG); ++	val &= ~(RALINK_UHST_RST); 
> ++	rt_writel(val, RT2880_RSTCTRL_REG); ++	mdelay (100); ++} ++ 
> ++static int rt3xxx_ehci_init(struct usb_hcd *hcd) ++{ ++	struct 
> ehci_hcd *ehci = hcd_to_ehci(hcd); ++	int retval = 0; ++ ++	/* No 
> USB-PCI space. */ ++	ehci->caps = hcd->regs /* + 0x100 */; ++ 
> ehci->regs = hcd->regs /* + 0x100 */ + 
> HC_LENGTH(ehci,ehci_readl(ehci, &ehci->caps->hc_capbase)); ++ 
> ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++
> ++ ehci_reset(ehci); ++ ++	retval = ehci_init(hcd); ++	if (retval)
> ++ return retval; ++ ++	ehci_port_power(ehci, 0); ++ ++	return 
> retval; ++} ++ ++static const struct hc_driver 
> rt3xxx_ehci_hc_driver = { ++	.description		= hcd_name, ++ 
> .product_desc		= "Ralink EHCI Host Controller", ++	.hcd_priv_size =
> sizeof(struct ehci_hcd), ++	.irq			= ehci_irq, ++	.flags			= 
> HCD_MEMORY | HCD_USB2, ++	.reset			= rt3xxx_ehci_init, ++	.start =
> ehci_run, ++	.stop			= ehci_stop, ++	.shutdown		= ehci_shutdown, ++
> .urb_enqueue		= ehci_urb_enqueue, ++	.urb_dequeue		= 
> ehci_urb_dequeue, ++	.endpoint_disable	= ehci_endpoint_disable, ++ 
> .get_frame_number	= ehci_get_frame, ++	.hub_status_data	= 
> ehci_hub_status_data, ++	.hub_control		= ehci_hub_control, ++#if 
> defined(CONFIG_PM) ++	.bus_suspend		= ehci_bus_suspend, ++ 
> .bus_resume		= ehci_bus_resume, ++#endif ++ ++	.relinquish_port =
> ehci_relinquish_port, ++	.port_handed_over       = 
> ehci_port_handed_over, ++	.clear_tt_buffer_complete       = 
> ehci_clear_tt_buffer_complete, ++	.endpoint_reset		= 
> ehci_endpoint_reset, ++ ++}; ++ ++static int 
> rt3xxx_ehci_probe(struct platform_device *pdev) ++{ ++	struct 
> usb_hcd *hcd; ++	const struct hc_driver *driver = 
> &rt3xxx_ehci_hc_driver; ++	struct resource *res; ++	int irq; ++
> int retval; ++ ++	if (usb_disabled()) ++		return -ENODEV; ++ ++	res
> = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++	if (!res) {
> ++ dev_err(&pdev->dev, "Found HC with no IRQ.\n"); ++		return 
> -ENODEV; ++	} ++	irq = res->start; ++ ++	hcd = 
> usb_create_hcd(driver, &pdev->dev, "rt3xxx" 
> /*dev_name(&pdev->dev)*/); ++	if (!hcd) { ++		retval = -ENOMEM; ++ 
> goto fail_create_hcd; ++	} ++ ++	res = platform_get_resource(pdev, 
> IORESOURCE_MEM, 0); ++	if (!res) { ++		dev_err(&pdev->dev,	"Found 
> HC with no register addr.\n"); ++		retval = -ENODEV; ++		goto 
> fail_request_resource; ++	} ++	hcd->rsrc_start = res->start; ++ 
> hcd->rsrc_len = res->end - res->start + 1; ++ ++	if 
> (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, 
> driver->description)) { ++		dev_dbg(&pdev->dev, "controller
> already in use\n"); ++		retval = -EBUSY; ++		goto
> fail_request_resource; ++ } ++ ++	hcd->regs =
> ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); ++	if (hcd->regs
> == NULL) { ++		dev_dbg(&pdev->dev, "error mapping memory\n"); ++
> retval = -EFAULT; ++		goto fail_ioremap; ++	} ++ ++	// reset host
> controller ++ //rt_usbhost_reset(); ++ ++	// wake up usb module
> from power saving mode... ++	try_wake_up(); ++ ++#ifdef
> CONFIG_USB_GADGET_RT ++#warning 
> "*********************************************************" 
> ++#warning	"*    EHCI will yield USB port0 to device controller! *"
> ++#warning 
> "*********************************************************"" 
> ++#else ++	// change port0 to host mode ++	rt_set_host(); ++#endif
>  ++ ++	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
>  ++	if (retval) ++		goto fail_add_hcd; ++ ++	return retval; ++ 
> ++fail_add_hcd: ++	iounmap(hcd->regs); ++fail_ioremap: ++ 
> release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 
> ++fail_request_resource: ++	usb_put_hcd(hcd); ++fail_create_hcd:
> ++ dev_err(&pdev->dev, "RT3xxx EHCI init fail. %d\n", retval); ++ 
> return retval; ++} ++ ++static int rt3xxx_ehci_remove(struct 
> platform_device *pdev) ++{ ++	struct usb_hcd *hcd = 
> platform_get_drvdata(pdev); ++ ++	/* ehci_shutdown() is supposed
> to be called implicitly in ++	   ehci-hcd common code while
> removing module, but it isn't. */ ++	ehci_shutdown(hcd); ++ ++ 
> usb_remove_hcd(hcd); ++	iounmap(hcd->regs); ++ 
> release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ 
> usb_put_hcd(hcd); ++ ++//	if(!usb_find_device(0x0, 0x0)) // No any 
> other USB host controller. ++//		try_sleep(); ++ ++	return 0; ++} 
> ++ ++MODULE_ALIAS("rt3xxx-ehci"); ++ ++static struct 
> platform_driver rt3xxx_ehci_driver = { ++	.probe = 
> rt3xxx_ehci_probe, ++	.remove = rt3xxx_ehci_remove, ++	.shutdown = 
> usb_hcd_platform_shutdown, ++	.driver = { ++		.name = 
> "rt3xxx-ehci", ++	}, ++}; ++ ++ +diff -ruN 
> a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig +--- 
> a/drivers/usb/host/Kconfig	2014-07-16 16:06:25.353735000 +0800
> ++++ b/drivers/usb/host/Kconfig	2014-07-16 16:22:32.202266541 +0800
> +@@ -371,6 +371,11 @@ + + if USB_OHCI_HCD + ++config RT3XXX_OHCI
> ++ bool "Ralink OHCI HCD support" ++	depends on USB_OHCI_HCD ++ 
> default y ++ + config USB_OHCI_HCD_OMAP1 + 	bool "OHCI support for 
> OMAP1/2 chips" + 	depends on ARCH_OMAP1 +diff -ruN 
> a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c +--- 
> a/drivers/usb/host/ohci-hcd.c	2014-06-17 04:43:06.000000000 +0800 
> ++++ b/drivers/usb/host/ohci-hcd.c	2014-07-16 16:22:32.204266552 
> +0800 +@@ -1191,6 +1191,11 @@ + #define PLATFORM_DRIVER 
> ohci_hcd_tilegx_driver + #endif + ++#if defined 
> (CONFIG_RT3XXX_OHCI) || defined (CONFIG_RT3XXX_OHCI_MODULE) 
> ++#include "ohci-rt3xxx.c" ++#define RT3XXX_PLATFORM_DRIVER 
> ohci_hcd_rt3xxx_driver ++#endif ++ + #ifdef 
> CONFIG_USB_OHCI_HCD_PLATFORM + #include "ohci-platform.c" +
> #define PLATFORM_DRIVER		ohci_platform_driver +@@ -1208,6 +1213,7
> @@ + !defined(S3C2410_PLATFORM_DRIVER) && \ + 
> !defined(EXYNOS_PLATFORM_DRIVER) && \ + 
> !defined(EP93XX_PLATFORM_DRIVER) && \ ++ 
> !defined(RT3XXX_PLATFORM_DRIVER) && \ + 
> !defined(AT91_PLATFORM_DRIVER) && \ + !defined(NXP_PLATFORM_DRIVER)
> && \ + !defined(DAVINCI_PLATFORM_DRIVER) && \ +@@ -1301,6 +1307,12
> @@ + goto error_exynos; + #endif + ++#ifdef RT3XXX_PLATFORM_DRIVER
> ++ retval = platform_driver_register(&RT3XXX_PLATFORM_DRIVER); ++
> if (retval < 0) ++		goto error_rt3xxx; ++#endif ++ + #ifdef 
> EP93XX_PLATFORM_DRIVER + 	retval = 
> platform_driver_register(&EP93XX_PLATFORM_DRIVER); + 	if (retval < 
> 0) +@@ -1350,6 +1362,10 @@ + 
> platform_driver_unregister(&AT91_PLATFORM_DRIVER); +  error_at91:
> + #endif ++#ifdef RT3XXX_PLATFORM_DRIVER ++ 
> platform_driver_unregister(&RT3XXX_PLATFORM_DRIVER); ++ 
> error_rt3xxx: ++#endif + #ifdef EP93XX_PLATFORM_DRIVER + 
> platform_driver_unregister(&EP93XX_PLATFORM_DRIVER); + 
> error_ep93xx: +@@ -1426,6 +1442,9 @@ + #ifdef 
> EP93XX_PLATFORM_DRIVER + 
> platform_driver_unregister(&EP93XX_PLATFORM_DRIVER); + #endif 
> ++#ifdef RT3XXX_PLATFORM_DRIVER ++ 
> platform_driver_unregister(&RT3XXX_PLATFORM_DRIVER); ++#endif + 
> #ifdef EXYNOS_PLATFORM_DRIVER + 
> platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER); + #endif
> +diff -ruN a/drivers/usb/host/ohci-platform.c 
> b/drivers/usb/host/ohci-platform.c +--- 
> a/drivers/usb/host/ohci-platform.c	2014-07-16 16:06:24.374730000 
> +0800 ++++ b/drivers/usb/host/ohci-platform.c	2014-07-16 
> 16:22:32.205266558 +0800 +@@ -222,10 +222,10 @@ + #define 
> ohci_platform_resume	NULL + #endif /* CONFIG_PM */ + +-static
> const struct of_device_id ralink_ohci_ids[] = { +-	{ .compatible = 
> "ralink,rt3xxx-ohci", }, +-	{} +-}; ++//static const struct 
> of_device_id ralink_ohci_ids[] = { ++//	{ .compatible = 
> "ralink,rt3xxx-ohci", }, ++//	{} ++//}; + + static const struct 
> platform_device_id ohci_platform_table[] = { + 	{ "ohci-platform", 
> 0 }, +@@ -247,6 +247,6 @@ + 		.owner	= THIS_MODULE, + 		.name	= 
> "ohci-platform", + 		.pm	= &ohci_platform_pm_ops, +- 
> .of_match_table = of_match_ptr(ralink_ohci_ids), ++// 
> .of_match_table = of_match_ptr(ralink_ohci_ids), + 	} + }; +diff 
> -ruN a/drivers/usb/host/ohci-rt3xxx.c 
> b/drivers/usb/host/ohci-rt3xxx.c +--- 
> a/drivers/usb/host/ohci-rt3xxx.c	1970-01-01 08:00:00.000000000 
> +0800 ++++ b/drivers/usb/host/ohci-rt3xxx.c	2014-07-16 
> 15:28:05.081089000 +0800 +@@ -0,0 +1,216 @@ ++/* ++ * RT3883 OHCI 
> HCD (Host Controller Driver) for USB. ++ * ++ * (C) Copyright 2009 
> Ralink Tech Company ++ * ++ * Bus Glue for Ralink OHCI controller.
>  ++ * ++ * Written by YYHuang <yy_huang at ralinktech.com.tw> ++ * 
> Based on fragments of previous driver by Russell King et al. ++ * 
> ++ * This file is licenced under the GPL. ++ */ ++ ++#include 
> <linux/clk.h> ++#include <linux/device.h> ++#include 
> <linux/signal.h> ++#include <linux/platform_device.h> ++#include 
> <linux/dma-mapping.h> ++#include <linux/of.h> ++ ++#include 
> "ralink_usb.h" ++ ++static struct usb_ohci_pdata 
> ohci_rt3xxx_defaults; ++ ++static int usb_hcd_rt3xxx_probe(const 
> struct hc_driver *driver, struct platform_device *pdev) ++{ ++	int 
> retval; ++	struct usb_hcd *hcd; ++	struct resource *res_mem; ++ 
> struct usb_ohci_pdata *pdata; ++	int irq; ++//	int err = -ENOMEM; 
> ++ ++	/* ++	 * use reasonable defaults so platforms don't have to 
> provide these. ++	 * with DT probing on ARM, none of these are set.
> ++	 */ ++	if (!pdev->dev.platform_data) ++ pdev->dev.platform_data
> = &ohci_rt3xxx_defaults; ++	if (!pdev->dev.dma_mask) ++
> pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; ++	if
> (!pdev->dev.coherent_dma_mask) ++		pdev->dev.coherent_dma_mask =
> DMA_BIT_MASK(32); ++ ++	pdata = pdev->dev.platform_data; ++ ++	irq
> = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++
> dev_err(&pdev->dev, "no irq provided"); ++ return irq; ++	} ++ ++
> res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++	if
> (!res_mem) { ++		dev_err(&pdev->dev, "no memory resource
> provided"); ++		return -ENXIO; ++	} ++ ++//	if (pdata->power_on) {
> ++//		err = pdata->power_on(dev); ++//		if (err < 0) ++//			return
> err; ++//	} ++ ++	if (pdev->resource[1].flags != IORESOURCE_IRQ) {
> ++		dev_dbg(&pdev->dev, "resource[1] is not IORESOURCE_IRQ\n"); ++
> return -ENOMEM; ++	} ++ ++	hcd = usb_create_hcd(driver, &pdev->dev,
> "rt3xxx-ohci"); ++	if (hcd == NULL) ++		return -ENOMEM; ++ ++
> hcd->rsrc_start = pdev->resource[0].start; ++	hcd->rsrc_len =
> pdev->resource[0].end - pdev->resource[0].start + 1; ++	if 
> (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { 
> ++		usb_put_hcd(hcd); ++		retval = -EBUSY; ++		goto err1; ++	} ++ 
> ++	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); ++	if 
> (hcd->regs == NULL) { ++		dev_dbg(&pdev->dev, "ioremap failed\n");
>  ++		retval = -ENOMEM; ++		goto err2; ++	} ++ ++	try_wake_up(); ++
>  ++	ohci_hcd_init(hcd_to_ohci(hcd)); ++ ++	retval =
> usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED |
> IRQF_SHARED); ++	if (retval == 0) ++		return retval; ++ ++
> try_sleep(); ++ iounmap(hcd->regs); ++err2: ++
> release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++err1: ++
> usb_put_hcd(hcd); ++ ++	return retval; ++} ++ ++static int
> usb_hcd_rt3xxx_remove(struct usb_hcd *hcd, struct platform_device
> *pdev) ++{ ++	struct usb_ohci_pdata *pdata = 
> pdev->dev.platform_data; ++ ++	usb_remove_hcd(hcd); ++ try_sleep();
> ++	iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start,
> hcd->rsrc_len); ++ usb_put_hcd(hcd); ++	platform_set_drvdata(pdev,
> NULL); ++ ++//	if (pdata->power_off) ++//		pdata->power_off(pdev);
> ++ ++	if (pdata == &ohci_rt3xxx_defaults) ++
> pdev->dev.platform_data = NULL; ++ ++ return 0; ++} ++ ++static int
> ohci_rt3xxx_start(struct usb_hcd *hcd) ++{ ++	struct ohci_hcd *ohci
> = hcd_to_ohci(hcd); ++	int ret; ++ ++	if ((ret = ohci_init(ohci)) <
> 0) ++		return ret; ++ ++	if ((ret = ohci_run(ohci)) < 0) { ++
> dev_err(hcd->self.controller, "can't start %s\n", ++
> hcd->self.bus_name); ++		ohci_stop(hcd); ++		return ret; ++	} ++ ++
> return 0; ++} ++ ++static struct hc_driver ohci_rt3xxx_hc_driver =
> { ++	.description		= hcd_name, ++ .product_desc		= "RT3xxx OHCI
> Controller", ++	.hcd_priv_size		= sizeof(struct ohci_hcd), ++	.irq
> = ohci_irq, ++	.flags			= HCD_USB11 | HCD_MEMORY, ++	.start			=
> ohci_rt3xxx_start, ++	.stop = ohci_stop, ++	.shutdown		=
> ohci_shutdown, ++	.urb_enqueue		= ohci_urb_enqueue, ++	.urb_dequeue
> = ohci_urb_dequeue, ++ .endpoint_disable	= ohci_endpoint_disable,
> ++	.get_frame_number	= ohci_get_frame, ++	.hub_status_data	=
> ohci_hub_status_data, ++ .hub_control		= ohci_hub_control, ++#ifdef
> CONFIG_PM ++ .bus_suspend		= ohci_bus_suspend, ++	.bus_resume		= 
> ohci_bus_resume, ++#endif ++	.start_port_reset	= 
> ohci_start_port_reset, ++}; ++ ++extern int usb_disabled(void); ++
>  ++ ++static int ohci_hcd_rt3xxx_drv_probe(struct platform_device 
> *pdev) ++{ ++	int ret; ++ ++	ret = -ENODEV; ++ ++	if 
> (!usb_disabled()) ++		ret = 
> usb_hcd_rt3xxx_probe(&ohci_rt3xxx_hc_driver, pdev); ++ ++	return 
> ret; ++} ++ ++static int ohci_hcd_rt3xxx_drv_remove(struct 
> platform_device *pdev) ++{ ++	struct usb_hcd *hcd = 
> platform_get_drvdata(pdev); ++ ++	return
> usb_hcd_rt3xxx_remove(hcd, pdev); ++ ++//	if(!usb_find_device(0x0,
> 0x0)) // No any other USB host controller. ++//		try_sleep(); ++
> ++//	return 0; ++} ++ ++static const struct of_device_id
> ralink_ohci_ids[] = { ++	{ .compatible = "ralink,rt3xxx-ohci", },
> ++	{} ++}; ++ ++//static const struct platform_device_id
> ohci_rt3xxx_table[] = { ++//	{ "ohci-rt3xxx", 0 }, ++//	{ } ++//};
> ++MODULE_DEVICE_TABLE(of, ralink_ohci_ids); ++ ++static struct
> platform_driver ohci_hcd_rt3xxx_driver = { ++	.probe		=
> ohci_hcd_rt3xxx_drv_probe, ++	.remove		=
> ohci_hcd_rt3xxx_drv_remove, ++	.shutdown	= 
> usb_hcd_platform_shutdown, ++	.driver		= { ++		.name	= 
> "rt3xxx-ohci", ++		.owner	= THIS_MODULE, ++		.of_match_table = 
> of_match_ptr(ralink_ohci_ids), ++	}, ++}; ++ 
> ++MODULE_ALIAS("platform:rt3xxx-ohci"); +diff -ruN 
> a/drivers/usb/host/ralink_usb.h b/drivers/usb/host/ralink_usb.h 
> +--- a/drivers/usb/host/ralink_usb.h	1970-01-01 08:00:00.000000000 
> +0800 ++++ b/drivers/usb/host/ralink_usb.h	2014-07-16 
> 16:22:32.206266563 +0800 +@@ -0,0 +1,60 @@ ++ ++ ++#ifndef 
> __RALINK_USB_H__ ++ ++#include <asm/rt2880/rt_mmap.h> ++ ++#define 
> SYSCFG1			(RALINK_SYSCTL_BASE + 0x14) ++#define USB0_HOST_MODE 
> (1UL<<10) ++ ++#define RT2880_CLKCFG1_REG      (RALINK_SYSCTL_BASE 
> + 0x30) ++ ++#define RT2880_RSTCTRL_REG      (RALINK_SYSCTL_BASE + 
> 0x34) ++#define RALINK_UHST_RST         (1<<22) ++#define 
> RALINK_UDEV_RST         (1<<25) ++ ++inline static void 
> try_wake_up(void) ++{ ++	u32 val; ++ ++	val = 
> le32_to_cpu(*(volatile u_long *)(RT2880_CLKCFG1_REG)); ++#if 
> defined (CONFIG_SOC_RT3883) || defined (CONFIG_SOC_RT3352) || 
> defined (CONFIG_SOC_MT7620) ++	val = val | (RALINK_UPHY0_CLK_EN | 
> RALINK_UPHY1_CLK_EN) ; ++#elif defined (CONFIG_SOC_RT5350) ++	/* 
> one port only */ ++	val = val | (RALINK_UPHY0_CLK_EN) ; ++#else 
> ++#error	"no define platform" ++#endif ++ ++	*(volatile u_long 
> *)(RT2880_CLKCFG1_REG) = cpu_to_le32(val); ++	udelay(10000);	// 
> enable port0 & port1 Phy clock ++ ++	val = le32_to_cpu(*(volatile 
> u_long *)(RT2880_RSTCTRL_REG)); ++	val = val & ~(RALINK_UHST_RST | 
> RALINK_UDEV_RST); ++	*(volatile u_long *)(RT2880_RSTCTRL_REG) = 
> cpu_to_le32(val); ++	udelay(10000);	// toggle reset bit 25 & 22 to 
> 0 ++} ++ ++inline static void try_sleep(void) ++{ ++	u32 val; ++
> ++ val = le32_to_cpu(*(volatile u_long *)(RT2880_CLKCFG1_REG));
> ++#if defined (CONFIG_SOC_RT3883) || defined (CONFIG_SOC_RT3352)
> || defined (CONFIG_SOC_MT7620) ++	val = val & ~(RALINK_UPHY0_CLK_EN
> | RALINK_UPHY1_CLK_EN); ++#elif defined (CONFIG_SOC_RT5350) ++	val
> = val & ~(RALINK_UPHY0_CLK_EN); ++#else ++#error	"no define 
> platform" ++#endif ++	*(volatile u_long *)(RT2880_CLKCFG1_REG) = 
> cpu_to_le32(val); ++	udelay(10000);  // disable port0 & port1 Phy 
> clock ++ ++	val = le32_to_cpu(*(volatile u_long 
> *)(RT2880_RSTCTRL_REG)); ++	val = val | (RALINK_UHST_RST | 
> RALINK_UDEV_RST); ++	*(volatile u_long *)(RT2880_RSTCTRL_REG) = 
> cpu_to_le32(val); ++	udelay(10000);  // toggle reset bit 25 & 22
> to 1 ++} ++ ++#endif /* __RALINK_USB_H__ */ +diff -ruN 
> a/drivers/usb/Kconfig b/drivers/usb/Kconfig +--- 
> a/drivers/usb/Kconfig	2014-07-16 16:06:24.400730000 +0800 ++++ 
> b/drivers/usb/Kconfig	2014-07-16 16:22:32.211266591 +0800 +@@
> -25,6 +25,7 @@ + 	# MIPS: + 	default y if MIPS_ALCHEMY + 	default y
> if MACH_JZ4740 ++	default y if SOC_MT7620 + 	# more: + 	default PCI
> + +@@ -49,6 +50,7 @@ + 	default y if ARCH_MMP + 	default y if 
> MACH_LOONGSON1 + 	default y if PLAT_ORION ++	default y if 
> SOC_MT7620 + 	default PCI + + # some non-PCI HCDs implement xHCI
> 
_______________________________________________
openwrt-devel mailing list
openwrt-devel at lists.openwrt.org
https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel


More information about the openwrt-devel mailing list