[OpenWrt-Devel] [PATCH] [LANTIQ] Add XWAY cpu-feature-overrides.h

[José Vázquez Fernández]

Add XWAY cpu-feature-overrides.h file.

This patch adds cpu-feature-overrides.h file for the XWAY family, based 
in the one in FALCON.
Because Amazon SE was deprecated, cpu_has_dsp and cpu_has_mips16 have 
been set, while cpu_has_mt has been undefined due to the lack of mt ASE 
in the Danube.
With this file the kernel size is reduced about 30KB in the XWAY subtarget.
Tested in a Danube based router with no problems and with a little 
improvement in the USB port when using mass storage devices and wireless 
dongles.

Signed off by: José Vázquez Fernández <ppvazquezfer at gmail.com>


--- a/arch/mips/include/asm/mach-lantiq/xway/cpu-feature-overrides.h 
1970-01-01 01:00:00.000000000 +0100
+++ b/arch/mips/include/asm/mach-lantiq/xway/cpu-feature-overrides.h 
2014-07-01 12:37:07.790313378 +0200
@@ -0,0 +1,58 @@
+/*
+ *  Lantiq XWAY specific CPU feature overrides
+ *
+ *  Copyright (C) 2014 José Vázquez Fernández
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *	Copyright (C) 2003, 2004 Ralf Baechle
+ *	Copyright (C) 2004 Maciej W. Rozycki
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as 
published
+ *  by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_XWAY_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_XWAY_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb		1
+#define cpu_has_4kex		1
+#define cpu_has_3k_cache	0
+#define cpu_has_4k_cache	1
+#define cpu_has_tx39_cache	0
+#define cpu_has_sb1_cache	0
+#define cpu_has_fpu		0
+#define cpu_has_32fpr		0
+#define cpu_has_counter		1
+#define cpu_has_watch		1
+#define cpu_has_divec		1
+
+#define cpu_has_prefetch	1
+#define cpu_has_ejtag		1
+#define cpu_has_llsc		1
+
+#define cpu_has_dsp		1
+#define cpu_has_mips16		1
+#define cpu_has_dsp2		0
+#define cpu_has_mdmx		0
+#define cpu_has_mips3d		0
+#define cpu_has_smartmips	0
+#define cpu_has_vz		0
+
+#define cpu_has_mips32r1	1
+#define cpu_has_mips32r2	1
+#define cpu_has_mips64r1	0
+#define cpu_has_mips64r2	0
+
+#define cpu_has_vint		1 /* MIPSR2 vectored interrupts */
+#define cpu_has_veic		1 /* MIPSR2 external interrupt controller mode */
+
+#define cpu_has_64bits		0
+#define cpu_has_64bit_zero_reg	0
+#define cpu_has_64bit_gp_regs	0
+#define cpu_has_64bit_addresses	0
+
+#define cpu_dcache_line_size()	32
+#define cpu_icache_line_size()	32
+
+#endif /* __ASM_MACH_XWAY_CPU_FEATURE_OVERRIDES_H */
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