[OpenWrt-Devel] AR9344 pcie fails to start (sometimes)

[Helmut Schaa]

On Wed, Dec 10, 2014 at 1:54 PM, John Crispin <blogic at openwrt.org> wrote:
>
>
> On 10/12/2014 13:43, Helmut Schaa wrote:
>> Hi,
>>
>> Did anyone else see issues with ar9344 PCIe not coming up sometimes
>> (it is really rare in my case)?
>>
>> Good boot dmesg:
>>
>> [    0.070000] registering PCI controller with io_map_base unset
>> [    0.280000] bio: create slab <bio-0> at 0
>> [    0.280000] PCI host bridge to bus 0000:00
>> [    0.280000] pci_bus 0000:00: root bus resource [mem
>> 0x10000000-0x13ffffff]
>> [    0.280000] pci_bus 0000:00: root bus resource [io  0x0000]
>> [    0.280000] pci_bus 0000:00: No busn resource found for root bus,
>> will use [bus 00-ff]
>> [    0.280000] pci 0000:00:00.0: [168c:0030] type 00 class 0x028000
>> [    0.280000] pci 0000:00:00.0: invalid calibration data
>> [    0.290000] pci 0000:00:00.0: reg 10: [mem 0x00000000-0x0001ffff
>> 64bit]
>> [    0.290000] pci 0000:00:00.0: reg 30: [mem 0x00000000-0x0000ffff
>> pref]
>> [    0.290000] pci 0000:00:00.0: supports D1
>> [    0.290000] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
>> [    0.290000] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 00
>> [    0.290000] pci 0000:00:00.0: BAR 0: assigned [mem
>> 0x10000000-0x1001ffff 64bit]
>> [    0.290000] pci 0000:00:00.0: BAR 6: assigned [mem
>> 0x10020000-0x1002ffff pref]
>> [    0.290000] pci 0000:00:00.0: using irq 40 for pin 1
>>
>> Bad boot dmesg:
>>
>> [    0.070000] ar724x-pci ar724x-pci: PCIe link is down
>> [    0.070000] registering PCI controller with io_map_base unset
>> [    0.280000] bio: create slab <bio-0> at 0
>> [    0.280000] PCI host bridge to bus 0000:00
>> [    0.280000] pci_bus 0000:00: root bus resource [mem
>> 0x10000000-0x13ffffff]
>> [    0.280000] pci_bus 0000:00: root bus resource [io  0x0000]
>> [    0.280000] pci_bus 0000:00: No busn resource found for root bus,
>> will use [bus 00-ff]
>> [    0.280000] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 00
>>
>> In this state no device is detected on the PCI bus.
>>
>> Any ideas?
>>
>
> we had the same bug on mtk targets recently to fix it we did

Thanks, do you have a link to the appropriate commit somewhere?

> * made sure the /PCIE_RST goes high before pulling it low and then up
> again so that it gets a proper toggle and not just half of one.
> * put the pci core into reset before rebooting the system
>
> i would start by testing the first one to see if the pcie device gets a
> proper card reset upon boot up and also check the timings. my tests
> showed that 50ms is the minimum required. however that number is just
> trial and error so it might be SoC or card specific

I'll give it a try but it really happens rarely, so lots of boot
cycles to reproduce.

Helmut
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