[OpenWrt-Devel] Documentation of AR71xx per-module reset timings?

Heiner Kallweit hkallweit1 at gmail.com
Sat Dec 6 17:12:06 EST 2014

On AR71xx the reset of each module uses such a sequence:

<delay 1>
<delay 2>

Seems like the reset bits are not self-clearing and polling
for the reset to be finished is not possible.

Is there any Atheros documentation of the per-module reset timing available?
(Or are the required delays just based on trial & error?)
At least in the Atheros reference manuals I found nothing.

Thanks, Heiner
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